JPH04184791A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To enable reduction in a clock cycle of a clock signal and response to a burst lead cycle of a microprocessor by a method wherein data of multiple units are read out simultaneously to hold and an output sequence of the data, an incremental or decremental order of an address, is selected to output. CONSTITUTION:A memory cell array 1 reads out data DTA-DTD for four words by a high-order address signal ADU simultaneous and a data holding circuit 2 holds the DTA-DTD temporarily. In addition, an output sequence decision circuit 3 inputs a clock signal CK, a burst control signal BC, an incremental/ decremental sequence switching signal UDS and a low-order signal ADL (A0, A1) and determines in which sequence the data DTA-DTD are outputted, in an incremental or decremental order to turn one each of switching signals SWA-SWD to '1' level according to the sequence selected. Then, an output circuit 4 outputs (DT0) the data as held in a data holding circuit 2 sequentially according to the switching signals SWA-SWD. This enables reduction in a clock cycle and response to a microprocessor which performs a wrap around transfer in the incremental or decremental order.

Description

[Detailed description of the invention] [Industrial application field] Regarding memory.

[Conventional technology]

A 32-bit microprocessor with a built-in cache memory of several KB will change the block size of the cache memory (for example, 16
bytes) of data. At this time, a microprocessor with a 32-bit data width transfers data four times, which takes time. Therefore, in order to shorten the transfer time, many microprocessors are equipped with a birthday F function that reads the second and subsequent data every clock cycle.

However, as the operating frequency of a 32-bit microprocessor increases, the period corresponding to 1 clock cycle (hereinafter referred to as 1 clock period) becomes shorter, and the general-purpose high-speed S
RAM will no longer be able to handle burst reads.

Therefore, as a conventional technique, as shown in FIG. 6, an address up counter 50 and multiplexers 60A and 60B are built into the semiconductor memory, and the address is automatically counted up in the semiconductor memory to output consecutive four words of data. A burst read function was supported by reading T o every clock cycle.

[Problem to be solved by the invention]

The conventional semiconductor memory described above has an address up counter 50 and multiplexers 60A and 60B built-in, and is configured to up-count addresses and read four consecutive words of data, so it has the following two drawbacks.

First of all, the semiconductor memory described above has an address up counter 50 and multiplexers 60A and 60A in a general-purpose memory.
0B, and basically accesses the memory cell array IA every time, so if one clock cycle becomes shorter than the access time of the memory cell array, it will not be able to handle burst read for one clock cycle.

Second, in the semiconductor memory described above, the counter wraps around in the ascending order of the address, so 64 of the 32-bit microprocessors with a burst read function are arranged in ascending order by the first word accessed, taking into account the data bus width. Or, it cannot support those that perform descending order wraparound transfer. As shown in Fig. 7, in the case of a 4-word bar street to a memory system with a 64-bit data bus width, if the first access is to area A, the subsequent access order is from area B to area C. →The access order of area D is ascending, but the first access is B.
This is because, in the case of accessing an area, the subsequent access order is a wraparound in descending order of A area → D area → C area.

An object of the present invention is to provide a microprocessor that can handle a clock signal with a short clock cycle, and that performs wrap-around transfer in ascending and descending order based on the first word accessed, taking into account the 64-bit data width. The object of the present invention is to provide a semiconductor memory that can also be used.

[Means to solve the problem]

The semiconductor memory of the present invention includes a reading means for simultaneously reading out data in a preset unit of a memory cell array in units of multiple units, and a holding circuit that temporarily holds the data in multiple units read by the reading means. an output order determining circuit that determines the output order of the data held in the holding circuit; and an output circuit that sequentially outputs the data held in the holding circuit according to the output order determined by the output order determining circuit. have.

Further, the output order determining circuit is configured to be able to select either ascending order or descending order of addresses as the output order of data held in the holding circuit.

[Margin below]

Pretext side] Next, implementation of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The memory cell array 1 is divided into four parts, and four words worth of data DTA,
Read D'rB, DTC+DTo simultaneously.

The data holding circuit 2 holds 4 words worth of data DTA-DTl) from the memory cell array 1 at - time.

Input ADL (AO, A1) and 4 words of data D
Decide which order to output ↑, ~DTt, in ascending order or descending order, and according to that order, switch signal 3W A=S
One by one among the Wo's are set to the "1" level one by one.

The output circuit 4 includes gate circuits 41A to 41D, and sequentially applies pressure (DTO) to the data held in the data holding circuit 2 according to switching signals SWA to SW.

FIG. 2 is a circuit diagram showing a specific example of the output order determining circuit 3 shown in FIG. 1.

The holding circuit 31 receives the input lower address signal ADL (
AO, A 1, hereinafter referred to as lower address AO, A1)
is held and its output is output to the data 32.

The decoder 32 receives the input lower address AO.

One of the decoder output signals DOA to DOD according to A1
Q output of any one of the registers 35A to 35°, that is, the switching signal SW A”SW
Raise one of o's houses to "1" level. Table 1 shows the lower addresses AO and AI in the decoder 32 and the switching signal SW.
The truth table of A to SWD is shown.

[Margin below]

The registers 35A to 35D in Table 1 form a shift register, and the Q output of the register set by the decoder output signal DOA=DOD is transferred to the adjacent register by the burst control clock signal BCK output from the burst control circuit 33. Shifted. At this time, which adjacent register is to be shifted is determined by the ascending order/descending order switching signal UDS, and in this embodiment, the lower address AO is "0".
It is set so that it is in ascending order when it is "1", and it is set in descending order when it is "1".

The burst control circuit 33 inputs the clock signal CK and the burst control signal BC, determines the shift timing of the registers 35A to 35D with the output burst control clock signal B (, and determines the shift timing of the registers 35A to 35D with the register set signal R8. The timing of setting DOD to the registers 35A to 35D is determined, and the holding circuit 31 is set using the latch signal HL.
Determine the latch timing of

The gates of the gate circuits 41A to 41D are opened according to the switching signals SWA to SWo from the pressure order determining circuit 3, and the data held in the data holding circuit 2 becomes the output data DTO.
is output as

Next, the operation of this embodiment will be explained.

In this embodiment, a case will be considered in which the access to data D T s is the first access with a data width of 32 bits as shown in FIG. An operation timing chart in this case is shown in FIG.

In this case, since the lower address AO is "1', the ascending order/descending order switching signal U is set so that the burst read order is descending order.
Enter DS.

For example, the multiplexer 34 outputs the ascending/descending switching signal UDS.
selects the switching signal SWi+ and inputs it to the D input of the register 35A.

Since the lower addresses Al and AD are "01", the decoder output signal DOB is "1" and the others are "0", and accordingly the switching signal SWB is "l" and the other switching signals SW
A, SWC, SWn become "0". Prior to this, in memory cell array 1, 4
One word worth of data DTA-DTD is simultaneously read out and held in data holding circuit 2.

Only the switching signal SWB from the output order determining circuit 3 is “1”
Therefore, the gate circuit 41. The gate of only one is opened and data DTB is output from the output circuit 4.

Next, the switching signal SWB is input to the register 35A by the burst control clock signal BCK controlled by the burst control circuit 33, and the switching signal SWA becomes "1" and the register 35. The output of is “0” when the switching signal SWo is input.
becomes.

Similarly, the switching signals SWC and SWD are also "0", and only the switching signal SWA is "1". As a result, the gate circuit 41
The gate of A is opened, the gate of gate circuit 4L is closed, and data DTA is applied from output circuit 4.

Thereafter, data DTD and DTC are sequentially output in the same manner.

When the first access is to data D To, similarly, the data is read in a descending order of burst read in the order of data DTD→data DTC→data DT yo→data DTA.

When the first access is to data DTA, DTc, if the ascending order/descending order switching signal is set in ascending order, each data DTA→DEDT YO→Data DTC−Data DT,,Data DT,−Data DTD→Data DTA→
The reading ratio is performed in the order of data DTB.

FIG. 5 is a block diagram of an output order determining circuit according to a second embodiment of the present invention.

The up/down counter 36 operates in burst mode for the first input lower addresses Al and AO, both circuits 33
At each clock period of the burst control clock signal from A, a count-up is performed in the case of ascending order, and a count-down is performed in the case of descending order, and up/down count signals ADCI and ADC2 are outputted.

The decoder 32A outputs an up/down count signal A D
C+, ADC decodes C2 and outputs switching signal SWA~
Set one of the SWDs to "1".

〔Effect of the invention〕

As explained above, the present invention has a configuration in which multiple units of data are simultaneously read and held, and the output order of these data is selected to be either ascending order or descending order of addresses. Since the read ratio is read from the memory cell array and held, it is possible to cope with the shortening of the clock cycle of the clock signal, and it is also suitable for microprocessors with burst read functions, especially 32
Although it is a 64-bit data bus width, even though it is a 64-bit data bus width, the burst read order is switched to ascending or descending order of addresses depending on the first word accessed during burst read. There is an effect that can be done.

[Brief explanation of drawings]

1 and 2 are a block diagram of a first embodiment of the present invention and a circuit diagram showing a specific example of the output order determining circuit of this embodiment, and FIGS. 3 and 4 are respectively shown in FIG. 5 is a block diagram of the output order determining circuit of the second embodiment of the present invention, and FIG. 6 and FIG. FIG. 7 is a block diagram of an example of a conventional semiconductor memory and a memory map of a memory cell array for explaining the problems of this example. 1. IA...Memory cell array, 2...
・Data holding circuit, 3,3A...Output order determining circuit, 4...Output circuit, 31...Holding circuit, 32.32A decoder, 33.33A...・・・
・Burst control circuit, 34A to 34D...Multiplexer, 35A to 35D...Register, 3
6...Up/down counter, 41A~41
．． )...Gate circuit, 50, address up counter, 60A, 60B...Multiplexer I Gl~G8...AND gate, ■, ~
Work...Inverter. Agent Patent Attorney Susumu Uchihara Du Shima 1 Figure J Zusei 5 Figure 4

Claims (1)

[Scope of Claims] 1. A reading means for simultaneously reading a plurality of preset units of data from a memory cell array, and a holding circuit for temporarily holding the plurality of units of data read by the reading means. , an output order determining circuit that determines the output order of the data held in the holding circuit, and an output circuit that sequentially outputs the data held in the holding circuit according to the output order determined by the output order determining circuit. A semiconductor memory characterized by having. 2. The semiconductor memory according to claim 1, wherein the output order determining circuit is capable of selecting either ascending order or descending order of addresses as the output order of the data held in the holding circuit.