JPS5853383B2 - Information transfer mechanism in data processing systems - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mechanism for effecting information transfer in an electronic data processing system.

The present invention is suitable for use in a modular type processor that uses a plurality of sub-processors, and more specifically, a common bus provided between a plurality of sub-processors,
It is suitable for transferring information via an interface provided between the bus and a control processor that performs control and diagnostic tasks in the processor.

Furthermore, the invention is suitable for use in data processing systems in which lower performance units are interconnected or communicate with higher performance units via a bus system.

For low-performance data processors, the price/performance ratio is key.

For this reason, the technology, which is suitable for large processors, cannot be applied to odd-type processors.

Fully parallel bus systems that can transfer information bit-parallel or byte-parallel are not only very expensive;
It is prone to errors.

Parallelism not only makes such systems very expensive, but also makes the data structure inflexible due to the fixed data format, so in some situations certain functions, such as diagnostic facilities, may be There are some things that must be omitted.

This is an important bottleneck in the case of low-performance data processing systems, since price, flexibility, and reliability are considerations that cannot be ignored.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to improve the bus system (bus, its input/output gates and control) hitherto used for information transfer, resulting in a significant cost reduction and a highly flexible data structure. Along with making it possible,
The aim is to enable an economically acceptable increase in reliability through special diagnostic functions.

Embodiments of the present invention will be described below with reference to the drawings.

Figure 1 shows a processor (P) 10 and an input/output unit) (I
1 illustrates an electronic data processing system consisting of 15;

The processor 10 has a plurality of sub-processors (Pl to P
n) 13, these sub-processors are interconnected via a bus 14 and a Maintenance and Service Processor Interface (hereinafter "MSPI").
) 12 via the maintenance and service processor (
11 (hereinafter abbreviated as "MSP").

The processor 10 modularly designed in this way is
It consists of a plurality of sub-processors, each individually assigned a task in the system.

For example, sub-processor Pn is processor 10 and ■
Controls communication between 10 units 150.

A control processor such as MSPll and a plurality of sub-processors P1 to Pn communicate via a bus system 14, so that the control processor 11 and sub-processors 1
An MSP 112 is provided on each side of 3.

The control processor 11 does not communicate with intelligent sub-processors by itself, but it does communicate with these sub-processors if its interface with respect to the bus 14 is the same or similar to that of the sub-processors. can do.

The processor 10 also includes a storage device (ST) 16, which is connected via a storage bus 17 to the bus 14 and to certain sub-processors 13, which act as a storage control unit.

However, these connections are not shown to simplify the drawing.

In the case of low-performance electronic data processing systems, the cost of distributing information within a central control is key.

For example, employing serial rather than parallel information transfer can significantly reduce the total costs involved.

This will be confirmed by the various tasks that bus 14 must perform within processor 10.

Between the MSPll and other functional units such as sub-processor 13, bus 14 performs the following tasks.

Initial microprogram loading after system reset Power supply voltage monitoring on and off - Communication between MSPll and sub-processor 13 and I10 unit 150 Logical interface error logging between sub-processor 13 and MSPll - Error checking - MANUAL OPERATION MODE SETTING FIG. 2 illustrates the manner in which information is transferred via bus 14 of FIG.

In FIG. 2, this bus has been subdivided into buses 26a and 26b.

Data transfer with MSPII and sub processor 13
Data transfer to and from MSPII takes place serially via ring bus 26b, which is constituted by line FML from MSPll and line TML to MSPII.

Interface information register (IIR) 21゜Each sub-
Data register (DR) 22 of processor 13 and address register (AR) 23 of sub-processor 13
is a shift register in structure, consisting of chained latch circuits that can be loaded or read serially or in parallel.

All data and addresses are shifted or transferred bit serially from the interface information register 21 to the registers of each sub-processor 13.

Data from each sub-processor 13 is also transferred bit serially to the interface information register 21.

The information transferred via line FML can be either data or addresses.

A signal on line ADL that controls a switch (SW) 24 in each sub-processor 13 determines whether the information being transferred at a given time is to be interpreted as data or an address.

If the information transferred via line FML at a given time is to be interpreted as an address, the ff1llll signal on line ADL activates switch 24 so that said information can reach address register 23. set.

The information path in this case begins with the interface information register 21, and the line FML, its branch 24b, switch 2
4 and its output line 24c to address register 2.
3.

Address transfer is controlled such that all sub-processor selection addresses transferred via line FML are transferred to the address registers 23 of the various sub-processors P1 to Pn.

Since the circuits for connecting each sub-processor 13 and the bus 14 in FIG. 1 have the same configuration, only the circuit related to sub-processor P1 is shown in FIG.

If the information transferred via line FML is to be interpreted as data, this data has previously been assigned to the data address of the sub-processor selected by its address.
Supplied only to register 22.

The control mechanism required for this transfer operates as follows.

That is, the identification logic of each sub-processor 13 examines the address previously provided to its address register 23 by forwarding it to an address decoder and comparator (ADEC&COMP) 27.

This decoder and comparator 27 is connected to the associated sub-processor 1
The address stored in address register 23 is compared with the address previously transferred to address register 23.

If these addresses are equal, decryption and comparator 2
7 sends a control signal to switch 24 via line 27a;
By switching the switch to the other position, the information transferred via lines FML and 24b is thereafter provided to data register 22 via its output 24a.

This data is made available from each stage of data register 22 to a given data sink of each sub-processor 13 via parallel output 22a.

Switch 24 is controlled by two types of control signals.

That is, the first signal on line ADL sets switch 24 before transferring address information so that it can reach address register 23.

The second signal is generated when the address decoder and comparator 27 associated with each sub-processor 13 detects the address of the associated sub-processor.

The output signal of this address decoding and comparator 27 switches the switch 24 of the sub-processor 13 which has detected its own address, so that the data transferred via line F'ML is henceforth transferred to the data of this sub-processor 13. Register 22 can now be reached.

The data held in the data registers 22 of any sub-processor P1 to Pn is not necessarily made available only to the associated sub-processor 13, but rather to the interface information register in MSP I 12 via line TML. It is also possible to transfer the data serially to 21.

This transfer allows data generated in sub-processor 13 to be transferred bit-serially to MSPll.

Various technical solutions can be used to shift information pulses in or out of data register 22 or address register 23.

For example, the control logic (CTRL L
) 20 can transfer a gate control signal with a predetermined duration via line CGL.

This duration is chosen to be a suitable length so that shift clock control (SCTL) 25 provides the required number of clock pulses at each sub-processor 13, which depends substantially on the number of register stages. It can occur at the interface.

In the simplest case, this shift, clock control 25 is set to 1
clock circuit, which applies a common clock (CLS) to all units as their primary power in case of synchronous operation, and which is transmitted via the line CGL (25b). A gate control signal having a time can be applied as the second power.

For example, if 10 shift pulses are required, the length of this gate control signal is equal to the time clock signal CGL.
10 clock pulses are chosen such that they can pass through this gate circuit.

The Lucorella shift clock pulses provided by this gate circuit in the shift clock control 25 are supplied to the shift inputs of the shift registers.

Other shift pulse generation methods suitable for asynchronous operation of each sub-processor 13 and system elements are shown on line C.
This includes transferring shift pulses directly from MSP 112 via GL.

Thus, the shift pulses are generated in the control logic 20 or, if generated elsewhere, are transferred as a function thereof.

The method of generating shift pulses is illustrated in detail in FIGS. 4, 4a and 5.

FIG. 4 shows a method of generating shift pulses suitable for asynchronous operation of each sub-processor 13.

With reference to FIG. 4a, it will be appreciated that the time clock pulses on line CLS are generated continuously.

The gate control signal transferred via line CGL (25b) clocks shift clock control 25 for a time sufficient to transfer the required number of shift-pulses (10 in our example) to output line 25a. Open the gate 40 inside.

FIG. 5 shows a shift pulse control 25 suitable for synchronous operation.

This shift clock control 25 is controlled by the switch 24 in FIG.
Consists of a single line leading to .

Details of switch 24 are shown in FIG.

The central elements of this switch are two-pole, double-throw contacts 61 and 62 of an electromechanical or purely electronic relay, which are connected to the switch control (SW-C) via lines 24d and 27a.
(TL) 60.

Dashed line 63 shows the functional connection between switch control 60 and contacts 61 and 62.

Switch 24 allows the selected data register 2 to be connected while the information inputs of address register 23 and data register 22 are permanently connected to line FML.
It is also possible to switch only the two shift clock inputs and outputs.

In FIG. 6, contacts 61 and 62 are in the position set by the control signal on line 27a.

In this position, line 24b is connected to line 24c and line 25
a is connected to line 24f.

When contacts 61 and 62 are set to the other position by the control signal on line 24d, line 24b becomes connected to line 24a and line 25a becomes connected to line 24e.

Thus, by the action of the control signal on the line ADL provided for determining whether the information transferred via the line FML is to be interpreted as an address or data, the switch 24 causes the information line FML and the shift・Pulse line 25
a to the address 2 register 23.

The control signal on line 27a generated when address decoding and comparator 27 detects its own address (the address of the associated sub-processor) switches the position of contacts 61 and 62, thus switching the position of information line FML and the shift pulse. Line 25a is then connected to data register 22.

FIG. 8 shows a switch 24 in electronic form.

The central element of this switch is a latch circuit 80, which is set by the signal on line 24d and reset by the signal on line 27a.

In the set position, output A1 provides an output signal corresponding to a binary 1 and output A2 provides an output signal corresponding to a binary O.

In the reset position, the signal states of these two outputs are inverted.

For example, the pulse on line 24d goes to output A1 which provides an output signal corresponding to a binary 1, conditioning AND gates 81 and 83.

If signals are present on lines 24b and 25a, these signals are transferred to lines 24c and 24f via AND gates 83 and 81, respectively.

This means that the information line FML and shift pulse line 25a
corresponds to being connected to the address register 23, respectively.

The pulses transferred via line 27a are e.g.
Since it resets the 0, a signal corresponding to a binary 1 becomes available at its output A2.

This signal activates AND gates 82 and 84.

When switch 24 is reset in this manner, information line FML and shift pulse line 25a are connected to data register 22 via lines 24a and 24e, respectively.

The generation of the shift pulse is as described above in connection with FIGS. 4, -4a and 5, but below with reference to FIG. Explain how it occurs.

As previously discussed, the output signal on line 27a is generated by address decoder and comparator 27.

More specifically, when the address supplied to address register 23 during the preceding transfer step corresponds to the address of its associated sub-processor (eg, sub-processor P1 in FIG. 2); This address decoder and comparator 27 produces its output signal on line 27a.

For this purpose, a comparator (COMP) 71 is provided, to which the two addresses to be compared with each other are applied.

When the address of the sub-processor to be selected is transferred to the address register 23 of each processor 13,
It is supplied to comparator 71 via line 23a.

The address associated with this sub-processor 13 is in an internal address register (A-REG) 70, which is loaded with the address of the sub-processor via an internal line 72 at initial microprogram loading time.

This address can also be used manually by the comparator 710.

If these two addresses are equal, comparator 71 provides its output to AND gate 7301.

The other input of the AND gate 73 is connected to the clock line CLS, which pulses the required time to the comparator 7.
The output signal of switch 2 is transferred to line 27a, so that the output signal of switch 2
4 to switch from address register 23 to data register 22.

The above operations are the basic operations of the basic circuitry provided for data transfer in the sub-processor 13.

The functions that can be performed via path 14 of FIG. 1 are described below.

A distinction should be made between functions that can be performed on an active sub-processor and functions that can only be performed on a stopped sub-processor.

The group of functions that can only be performed when sub-processor 13 is active includes sensing the status of the sub-processor.

To increase reliability, this feature ensures that the address is first verified and then the current status of sub-processor 13 is messaged to MSP 112 of FIG.

Said group also includes the input of information, ie the loading of control registers (not shown) in the selected sub-processor 13.

This is for controlling selected sub-processors 13 during the performance of manual operations related to startup and shutdown or similar functions.

Thus, the control registers and the information stored in them function similar to console switch settings that control manual operation.

Finally, this group also includes programmed data transfers between the MSPll of FIG. 1 and selected sub-processors 13.

By the operation of these functions, various bytes in the microprogram of the requested sub-processor 13 are converted into MS.
Bits can be replaced or added serially with the help of PLL.

This feature is bidirectional and a given sub-processor 1
3 allows certain bytes to be replaced or added in the control program of the MSPII or other sub-processor.

Functions that can only be performed for a stopped sub-processor 13 include sensing chained latches that ultimately form a shift register, loading shift register chains, and loading shift register chains. It involves reading and writing memory cells connected in an array.

Before explaining the operations necessary to realize these functions, the circuit configuration of the MSP II 2 provided between the MSP II, the bus 14, and the sub-processor 130 will be explained in detail.

The upper part of FIG. 3 shows the main circuit elements of MSPII2.

Related elements include shift, register (SRL) 31
．． Included are a register register (ECR) 30 addressable by three addresses A to C, a control logic (CL) 32 forming a shift counter, and a sense register (ESR) 33 addressable by two addresses D and E.

Shift registers 31 can be set in parallel by external control registers 30 and sensed by sense registers 33.

Furthermore, as already explained in connection with FIG.
Register 31 can transfer its information serially to line FML or receive information serially via line TML.

The functions of the external control register 30 during this time are as follows.

Setting Address A This function causes data with the correct parity to be written into shift register 31.

Data at address B without setting parity is written into shift register 31.

Address C setting Control logic 32 is configured as follows.

As is clear from the above content, bits 0 and υ1 are reserved bits for control functions that will be added later.

Bit 2 is for setting switch 24 in FIG.
This bit is set in switch 2 so that the information transferred via line FML reaches address register 23 in FIG.
Set 4.

Bit 3 serves to provide a setting pulse to the control decoder (CDEC) 34 available in each sub-processor 13.

This setting pulse acts to energize the selected gate based on the transferred control information or the sensed information after being decoded by the decoder 34.

Thus, this printing pulse performs its purest time control function while performing a given function.

The last bits 4 to 7 indicate in a binary code the length by which the information should be serially shifted, specifically for each sub-processor 13.
applies to shift registers.

This binary code indicating the shift length is converted in the control decoder 34 of each subprocessor 13 into the required number of shift pulses or into a clock signal having a specific duration.

This latter clock signal is used by a given sub-processor 13
allows the required number of locally generated time clock pulses to reach the shift registers.

This makes it possible to perform synchronous or asynchronous transfers, as already explained in connection with FIGS. 4, 4a and 5.

Sense register 330 functionality is controlled by addresses D and E.

Sensing by address D means that the contents of the shift register are sensed and the correct parity for this data is generated.

During control by address E, the following data is sensed.

Control logic 32 operates to perform multiple tasks.

First, the logic counts the shift steps and thus determines the total shift length, which is determined by the information set in external control register 30 by address C.

Furthermore, as specified by bit 2 of the information set in Taop register 30 by address C, line ADL
is conditioned.

If bit 3 of the information set in control register 30 by address C is a binary 1, control logic 32
A set pulse is applied to the setting line included in bus 38 of the figure.

The game this line controls performs a transfer operation in the selected sub-processor 13 or as the last function of the sensing order in that sub-processor or to the MSP 112 or other sub-processor; or These operations are inhibited and the gate is thus guided by this signal as to which function to perform on the data stream.

This bit 3, set by address C, acts on control logic 32 of FIG. 3 to generate a setting pulse.

This bit is generated in control logic 32 when the gating control signal for transferring the required number of shift pulses is turned off.

If desired, generation of the set signal may be delayed until the trailing edge of the gate control signal is detected.

This applies both to the gate control signals that transfer addresses and to the data required for shifting.

In the sub-processor 13 the setting signal is fed to another gate whose other input is connected to an information line via which particular shift registers of the sub-processor are loaded in parallel. sell.

Also, the setting signal in the selected sub-processor 13 can be logically combined with other signals obtained, for example, by decoding internal addresses.

These other signals may also be combined with signals such as those generated by signals at particular bit positions of data register 22.

Setting pulses can be used to control parallel operation of internal registers.

If the address is shifted by 14 steps, 8+1 bits will be produced from shift register 31, followed by 4+1 zero bits.

Although this system operates on a byte organization having 8 information bits plus 1 parity bit per byte, it is also possible to choose a random data organization, the address organization described below being one example.

The sequence of serial data transfer is shown below.

Referring to this diagram, during the sequence of serial data transfer,
It can be seen that the parity bin (P) of the byte is transferred first, followed by the upper bit 0, and finally the lower bit 7.

A random number of bytes can be transferred by chaining, but this number is based on the selected shift step-code, which is a function of the total number of shift steps performed during the transfer operation. The maximum number of shift steps allowed must not be exceeded.

Strictly speaking, this applies only to generating gate open signals from shift step codes for gates (see FIG. 4) that transfer shift clocks.

If the solution according to Figure 5 is chosen, the shift
The step limit, and therefore the number of bytes transferred, is not limited by such code, but is derived by other methods from within the system.

The sub-processor of FIG. 3 (e.g. Pl or P
The circuit configuration of (n) is slightly different from that of FIG.

The functions of switch 24, shift pulse control 25, registers 22 and 23, address decoding and comparator 27 illustrated in FIG. 2 are integrated into two components 34 and 35, the former circuitry 34 controlling The latter circuitry 35 is called the address decoder and serializer/parallelizer (ADEC&S/D).

The inputs and outputs of the address decoder and serializer/parallelizer 35 are chain input (CHI) and chain output (CHO), which are provided for the operations of the arrays described below.

Additionally, there are inputs and outputs called BDTs, which are provided for byte-by-byte data transfer.

Finally there is an output called IAPD, which is used for preliminary address decoding in the subprocessor.

Not specifically shown in the circuitry belonging to the sub-processor (eg, Pl) are control registers and status latch circuits for sensing orders in the sub-processor.

This order sensing is accomplished with the aid of a control program that monitors specific bits that occur in specific registers at intervals between processing steps of sequential orders to be fired and is used to indicate order service requests.

The circuit configuration of sub-processor 13 further includes transfer registers 100 and 101 shown in FIG.

These registers are provided to transfer data to and from the sub-processor to MSP 112 or to other sub-processors.

The following display shows, for example, address formats usable in the sub-processor under discussion.

This address format allows for two types of addressing: short and long.

In the case of short-form addressing, MSPl in Figure 1
l generates only one byte as an address.

This byte consists of the subprocessor address and the high part of the internal address.

The remainder of the address consists of O pits.

As is clear from the address format display above, short form addressing allows for four internal addresses.

In other words, the address for order sensing described above, the address for extended order sensing, the address of transfer register 100 (FIG. 10a) to which data is transferred from the outside, and the address of transfer register 101 (FIG. 10a) that transfers data to the outside. 10
This means that the address shown in Figure b) is allowed.

In this case, 6 external '' means external to each sub-processor.

Fourteen shift steps are required to transfer this address over bus 14 (FIG. 1).

That is, 1 shift step for parity bit P1 and 6 shift steps for subprocessor address.
Step, 2 shifts for the upper part of the internal address
This means that one shift step for P2 (step, parity pick) and finally four shift steps for the lower part of the internal address are required.

However, the bits forming part of the second byte always consist of binary O's in the case of short-form addressing.

A total of 64 sub-processors can be addressed by the 6-bit positions of the sub-processor address.

Additionally, since the address format shown above includes 6 bits for internal addresses, these bits allow registers 100 and 101, as well as other shift register chains contained in sub-processor 13, to be 64 internal circuit groups can be addressed.

The reserved bits 0 and 1 mentioned above can be used, for example, for address extension.

The long form of addressing found in the address format shown above consists of a first byte with 9 pits and a second byte with 5 bits.

Therefore, this form of addressing requires additional lower 4 addresses to address the 64 internal circuit groups.
Requires bits.

A number of dynamic functions can be performed for the running sub-processor 13.

These dynamic functions include, for example, order sensing functions that use the following format:

The enhanced order sensing functionality uses the following format:

The order sensitive format indicates that bits 0 through 5 are associated with the subprocessor address and bits 6 and 7 are associated with the status of the addressed subprocessor 13.

Using such information, sub-processor 13 can communicate with MSPl via bus 14 and MSP 112 (FIG. 1).
can message its status to

Bit 6 of this format may be reserved, for example, for a program controlled sub-processor request (PCUR), and bit γ may be reserved to indicate abnormal status in any sub-processor circuit.

Bits 0-6 can be associated with random tasks to be defined in the future for enhanced order sensing functionality, and bit 7 can be associated with MSP 11 requests (MSP
REQ).

The order sensing or extended order sensing information via MSP 112 is entered into the circuit 35 of the selected sub-processor, or more precisely into the shift register of the serializer/parallelizer; This occurs after the internal address corresponding to this circuit has been selected and the setting pulse has been generated as described above.

As shown in Figures 10a and 10b, microprogram controlled sub-processors may be used to transfer information to and from the sub-processors on a byte-by-byte basis.

In general, the data format is not subject to any restrictions, so the format can be easily replaced with another format by appropriately selecting the widths of the shift pulse and sink register.

Byte register 100 (XTU
-REG) is for transferring one byte from the outside via line 102 to the selected sub-processor 13.

This byte is either serially transferred externally via line 104 or made available in parallel form to its associated sub-processor 13 via line 106.

Transfers in the reverse direction through register 101 shown in Figure 10b occur in a similar manner.

In this case, the byte is sub-processor 13 or 1EJj1
0γ to register 101 (XFU-REG) and serially to the outside via line 105.

It is also possible to load this register externally via line 103.

Register 100 receives data serially from the MSPll (FIG. 1) and transfers the data in parallel form to the associated sub-processor 13.

On the other hand, registers 101 receive these data in parallel form from their associated sub-processors 13 and transfer the data serially to their associated sub-processors 13.

Each of these registers can be addressed using the short form addressing described above.

Multi-byte transfers are controlled by two launch circuits (PCUR and MSP REQ), not shown.
The latch is controlled by bit 6 of the order sensitive format or bit 7 of the extended order sensitive format.

These latch circuits can be sensed by MSP 11 (FIG. 1) and their respective sub-processors 13.

Latch circuit controlled by bit 7 (MSPR
EQ) is set in register 100 (10th a
3) is set and a setting pulse is applied via the line or bus previously described in connection with FIG.

However, this latch circuit can only be reset by its associated sub-processor 13.

A latch circuit (PCUR) controlled by bit 6 of the conventional order sense function is set by its associated subprocessor 13.

Resetting occurs when the internal address of the register 101 is selected and the setting pulse is transferred via the previously mentioned bus or line. For the execution of static functions, the sub-processor 13 It must be stopped by a specific setting of a control register (not shown) or by an error stop of the sub-processor.

All shift registers in each sub-processor 13 can be selected by long form addressing as described above.

After a particular register is selected, the register can be read and loaded serially.

There are no practical restrictions on the length of a shift register made up of chained latch circuits, but the maximum length is 28 (25
6) It will be easier to handle if it reaches the stage.

Important information, such as test information, is preferably placed at the beginning of the chain so that it can be read by the tested logic.

In this case, the data transfer sequence starts with parity and
Following the high order bits and finally ending with the low order bits.

These bits must be passed sequentially along the data path and must not be interrupted by other signals.

If the sub-processors 13 and the rest of the system are manufactured in integrated technology, it becomes difficult to place the shift register on the same chip, so more than one chip must be used. There is.

This necessarily means that the boundary (CH) of the logical unit (LU)
B) leads to a discrepancy between physical unit boundaries.

The latter boundary is, for example, defined by a chip boundary.

In order to be able to easily replace machine circuits at their point of use, it is important, for example, to know the physical boundaries of defective circuits.

For this reason, such boundaries must be easily discernible.

For a shift register comprised of serially chained latch circuits (SRLs), such a physical boundary is illustrated at 110 in FIG.

The chain of latch circuits is thus arranged in such a way that the first stage of the shift register after the next chip boundary is a so-called test stage (CHK 5RL) and is accessible via line 118.

Mechanically, the first stage of the shift register following this stage is the final stage (LF) of the functional unit (LU).
5RL).

These stages are lines 115, 116, 117, 119
You can contact us via .

To identify the chip boundary (CHB), the output 113 of the test stage is connected to the output of the last functional stage (LPSRL) via an inverter 114.

This results in an inhomogeneity of the data structure that can be identified by known technical means.

Another mode of operation is illustrated in FIG. 9 in which the storage array (ARR) is addressed for writing and reading.

Data manual shift register (DIR) 9L Address shift register (ADR) 92 and data output register (DoR) 93 are connected to form a shift register chain by connecting lines 9γ and 98 between these registers.

Data is written into this shift register chain via the input line (CHI) and read out via the output line (CHO).

When data is written to storage array 90, first the address information and then the information to be written becomes available.

The latter information is then shifted through shift registers 91 and 92 by the action of the shift clock, and when the shifting is complete, provides register 92 with a full address and register 91 with full input data.

Address information is then applied to array 90 via line 95 and input data is applied via line 94.

When reading, address information is first given, followed by a number of binary 0s corresponding to the number of stages of data input register 91.

This information is then updated so that the full address information is
It is shifted until it becomes available again in register 92.

Data output registers 93 are then loaded in parallel with read data from the addressed storage locations.

Subsequently, the read data placed in the data output register 93 is shifted out via the output line (CHO),
It is then made available to the associated sub-processor 13 at the necessary point.

Referring to FIG. 3, there is a data input line (CHI
) and data output line (CHO) for each sub-processor 1.
3 is connected to the address decoding and serialization/parallelization device 35.

In this case, the operations connected to the array are also controlled by a control decoder 34 and a circuit 35, for example.

However, the interface information register 21 is also suitable for this purpose.

However, in that case, the interface control register 21
is the address decoding and serialization/parallelization device 35 shift/
Rather than being connected to registers, it is necessary to connect them in the form of a ring to shift registers 91-93.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a modular processor that is composed of a plurality of sub-processors and incorporates the present invention, and FIG.
The figure is a block diagram showing circuits in the interface of each subprocessor and maintenance and service processor necessary for connection with the bus, and FIG. 3 is a block diagram showing another embodiment of the circuits in FIG. 2. , 4A and 5 are diagrams showing the structure and operation of shift clock control for various shift registers used in the embodiment of the present invention, and FIG. 6 is a block diagram of the switch used in the embodiment of the present invention. , FIG. 7 is a block diagram of an address decoder and comparator used in an embodiment of the present invention, FIG. 8 is a block diagram of a purely electronic relay, and FIG. 9 is a chain diagram used for writing and reading matrix storage. Figures 0A and 10B are block diagrams of circuits containing formula shift registers.
FIG. 11 is a diagram illustrating an arrangement for detecting the physical boundaries of a plurality of physical blocks when the stages of a shift register are dividedly arranged into a plurality of physical blocks. 11... Maintenance and service processor, 12
...Maintenance and service processor interface, 13...Sub processor, 14...
. . . interconnection bus, 21 --- interface information register, 22 . . . data register,
23...Address register, 24...
・Switch, 25...Shift clock control,
27...Address decoding and comparator, FML...
...Information input line, TML...Information output line,
ADL... Control line.

Claims (1)

[Claims] 1. A data system in which a control processor and a plurality of processing units are connected in a branched manner via a common bus, and addresses and data are transmitted in bit series between the control processor and the processing units. In the processing system: Each of the processing units is provided with a shift register constituted by a chained latch circuit as an address register and a data register, respectively, and the address register and the data register are provided in each of the processing units. are respectively connected to an information input line of the common bus and a shift control line defining a shift amount through switches respectively provided in the common bus; the data register is also connected to an information output line of the common bus; an address control line is connected to the switch to provide a control signal to the switch during address transfer to connect all address registers of the processing unit in parallel to the information input line and the shift control line; Each of the units is provided with a respective address comparator for comparing the address transferred via the information input line with the address of the associated processing unit, and each of the address comparators is configured to By switching the associated switch, the subsequent data transferred via the information input line is transferred to the data input line of the associated processing unit under the control of the shift control line.
An information transfer mechanism in a data processing system that operates to transfer information to a register.