GB1501035A - Data processing apparatus - Google Patents

Abstract

1501035 Data processing systems; selective signalling INTERNATIONAL BUSINESS MACHINES CORP 15 June 1976 [10 July 1975] 24804/76 Headings G4A and G4H A plurality of modules, e.g. integrated circuit sub-processors, Pl-Pn are connected to a common serial bus FML over which data and addresses are transmitted, and each module includes a switch SW which is actuated by a common control line ADL to connect the bus to an address decoder 27, and which is actuated by that corresponding address decoder to connect the bus to a data input 24a of the associated module when the address of that module has been recognized. The sub-processors may communicate over the bus with a control processor via an interface HSPI and may perform functions such as storage or I/O control. The common bus may be effectively a loop 26b which includes a shift register IIR in the control processor interface. The address and data outputs of the switch SW in each sub-processor may be connected to address and data shift registers AR, DR for which shift pulses are generated locally and are gated, 25, by a control signal CGL of appropriate duration from the interface or which are supplied directly from the interface. Alternatively the interface may transmit a coded signal representing the data length for decoding in a selected subprocessor to generate or gate the appropriate number of shift pulses. Control logic at the control processor interface may also generate and/or check the parity of information transferred over the bus and may generate a SET signal which initiates parallel transfer of data to or from a shift register in the selected subprocessor to be logically combined in a subprocessor with a decoded internal address or a particular bit of a data register. A sub-processor may include a storage array for which the associated data input, address and data output registers are serially connected in a chain, Fig. 9 (not shown).