GB1501035A - Data processing apparatus - Google Patents
Data processing apparatusInfo
- Publication number
- GB1501035A GB1501035A GB2480476A GB2480476A GB1501035A GB 1501035 A GB1501035 A GB 1501035A GB 2480476 A GB2480476 A GB 2480476A GB 2480476 A GB2480476 A GB 2480476A GB 1501035 A GB1501035 A GB 1501035A
- Authority
- GB
- United Kingdom
- Prior art keywords
- data
- address
- bus
- interface
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0653—Configuration or reconfiguration with centralised address assignment
- G06F12/0661—Configuration or reconfiguration with centralised address assignment and decentralised selection
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Complex Calculations (AREA)
Abstract
1501035 Data processing systems; selective signalling INTERNATIONAL BUSINESS MACHINES CORP 15 June 1976 [10 July 1975] 24804/76 Headings G4A and G4H A plurality of modules, e.g. integrated circuit sub-processors, Pl-Pn are connected to a common serial bus FML over which data and addresses are transmitted, and each module includes a switch SW which is actuated by a common control line ADL to connect the bus to an address decoder 27, and which is actuated by that corresponding address decoder to connect the bus to a data input 24a of the associated module when the address of that module has been recognized. The sub-processors may communicate over the bus with a control processor via an interface HSPI and may perform functions such as storage or I/O control. The common bus may be effectively a loop 26b which includes a shift register IIR in the control processor interface. The address and data outputs of the switch SW in each sub-processor may be connected to address and data shift registers AR, DR for which shift pulses are generated locally and are gated, 25, by a control signal CGL of appropriate duration from the interface or which are supplied directly from the interface. Alternatively the interface may transmit a coded signal representing the data length for decoding in a selected subprocessor to generate or gate the appropriate number of shift pulses. Control logic at the control processor interface may also generate and/or check the parity of information transferred over the bus and may generate a SET signal which initiates parallel transfer of data to or from a shift register in the selected subprocessor to be logically combined in a subprocessor with a decoded internal address or a particular bit of a data register. A sub-processor may include a storage array for which the associated data input, address and data output registers are serially connected in a chain, Fig. 9 (not shown).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19752530887 DE2530887C3 (en) | 1975-07-10 | 1975-07-10 | Control device for information exchange |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1501035A true GB1501035A (en) | 1978-02-15 |
Family
ID=5951191
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB2480476A Expired GB1501035A (en) | 1975-07-10 | 1976-06-15 | Data processing apparatus |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS5853383B2 (en) |
DE (1) | DE2530887C3 (en) |
FR (1) | FR2317704A1 (en) |
GB (1) | GB1501035A (en) |
IT (1) | IT1063307B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4328543A (en) | 1980-03-25 | 1982-05-04 | Ibm Corporation | Control architecture for a communications controller |
GB2217074A (en) * | 1988-03-17 | 1989-10-18 | Nittan Co Ltd | Monitoring/control system |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5085266U (en) * | 1973-12-06 | 1975-07-21 | ||
EP0037458B1 (en) * | 1980-02-29 | 1984-07-11 | International Business Machines Corporation | Time division multiple access satellite communications controller |
JPS61139868A (en) * | 1984-12-13 | 1986-06-27 | Fujitsu Ltd | Broadcast bus control system |
JPS62226263A (en) * | 1986-03-27 | 1987-10-05 | Nec Corp | Multiprocessor device |
FR2664077B1 (en) * | 1990-06-29 | 1993-06-04 | Alcatel Transmission | DEVICE FOR REMOTE MANAGEMENT OF A PLURALITY OF ELECTRONIC SUB-ASSEMBLIES. |
JP2552784B2 (en) * | 1991-11-28 | 1996-11-13 | 富士通株式会社 | Parallel data processing control method |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49114846A (en) * | 1973-02-28 | 1974-11-01 | ||
FR2256706A5 (en) * | 1973-12-27 | 1975-07-25 | Cii |
-
1975
- 1975-07-10 DE DE19752530887 patent/DE2530887C3/en not_active Expired
-
1976
- 1976-05-17 FR FR7615580A patent/FR2317704A1/en active Granted
- 1976-06-15 GB GB2480476A patent/GB1501035A/en not_active Expired
- 1976-06-16 IT IT2436876A patent/IT1063307B/en active
- 1976-07-07 JP JP51080000A patent/JPS5853383B2/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4328543A (en) | 1980-03-25 | 1982-05-04 | Ibm Corporation | Control architecture for a communications controller |
GB2217074A (en) * | 1988-03-17 | 1989-10-18 | Nittan Co Ltd | Monitoring/control system |
GB2217074B (en) * | 1988-03-17 | 1992-03-18 | Nittan Co Ltd | Monitoring/control system |
Also Published As
Publication number | Publication date |
---|---|
FR2317704A1 (en) | 1977-02-04 |
IT1063307B (en) | 1985-02-11 |
DE2530887A1 (en) | 1977-01-13 |
FR2317704B1 (en) | 1979-04-06 |
DE2530887B2 (en) | 1979-10-31 |
DE2530887C3 (en) | 1980-07-17 |
JPS5853383B2 (en) | 1983-11-29 |
JPS5211740A (en) | 1977-01-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |