GB2217074A

GB2217074A - Monitoring/control system

Info

Publication number: GB2217074A
Application number: GB8905343A
Authority: GB
Inventors: Tetsuo Kimura
Original assignee: Nittan Co Ltd
Current assignee: Nittan Co Ltd
Priority date: 1988-03-17
Filing date: 1989-03-08
Publication date: 1989-10-18
Anticipated expiration: 2009-03-08
Also published as: JPH01236400A; GB8905343D0; GB2217074B; JP2561120B2

Abstract

A monitoring/control system has a central monitoring/control apparatus (1) and one or more terminal devices (20) connected to the central monitoring/control apparatus (1) through a common transmission line (21), such that the central monitoring/control apparatus (1) can make access to a desired terminal device (20) by address polling. Each terminal device (20) has an address setting device (2) in which an address particular to the terminal device and having a predetermined number of bits is set. The central monitoring/control apparatus (1) is capable of transmitting address data to the terminal devices (20). The number of bits of the address data is variable within a range which does not exceed the number of bits of the particular address set in the address setting device (2). Each terminal device (20) has a coincidence detection circuit (4) which compares the address data with the portion of the particular address having the same number of bits as the address data transmitted from the central monitoring/control apparatus (1), and the terminal device (20) having coincidence is accessed. <IMAGE>

Description

MONITORING/CONTROL SYSTEM The present invention relates to a monitoring/control system having a central monitoring/cotrol apparatus capable of monitoring and control of a plurality of objects which are mainly but not exclusively temperature sensors, smoke-density sensors burglar sensors and so forth disposed at various locations in a building.

A monitoring/control system has been known in which monitoring/control objects such as sensors are monitored and/or controlled by a central monitoring/control apparatus in a centralized manner through terminal devices associated with the respective monitoring/control objects. This type of monitoring/control system essentially requires that different addresses are allocated for different terminals, in order to enable identification of the terminal device which is being in communication with the central monitoring/control apparatus.

To this end, each of the terminal devices is provided with an address setting device for the purpose of setting an address thereon. In operation, the central monitoring/control apparatus polls the terminal devices one after another by appointing the addresses of these terminal devices. A typical known address setting device of this kind has a DIP switch, a digital code switch or a semiconductor memory (ROM) having a predetermined number of bits,as disclosed, for example, in Japanese Utility Model Laid-Open No. 60-82389 entitled "Information Transmission Apparatus", specification of the United States Patent No.

4,658,243 entitled "Surveillance Control Apparatus for Security System", and Japanese Utility Model Laid-Open No.

61-126393 entitled "Fire Detector". The number of bits of the address which are set in this address setting device is fixed to be, for example, 8 (eight), so that the central monitoring/control apparatus is required to transmit address data of the fixed bit number to the respective terminal devices for the purpose of identifying these terminal devices.

The known monitoring/control system encounters the following problems, due to the fact that the number of bits of the address set in the address setting device is fixed to be,for example, 8. For instance, when the number of the terminal devices is increased beyond, for example, 256, it becomes necessary that the address data has a greater number of bits than 8, in order to enable identification of each of more than 256 addresses. In such a case, the user is obliged to prepare terminal devices having address setting devices capable of setting addresses of, for example, 9 bits, while modifying the address data to be transmitted from the central monitoring/control apparatus so as to obtain matching between the addresses of the respective terminal devices and the address data.

Conversely, in some cases, the number of the terminal devices of the monitoring/control -system is smaller than the number which corresponds to the number of bits, e.g., 256, which can be set in the address setting device. In such cases, however, polling of the terminals can safely be effected with address data composed of bits of a number smaller than the fixed number of bits. Polling of the terminal devices with address data of the fixed bit number, therefore, is wasteful because some of bits included in the data are useless, and inclusion of such useless bits undesirably impairs the data transmission efficiency.

Thus, the use of address of a fixed number of bits is not preferred because such address may require a modification of the whole system or a reduction in the transmission efficiency, when a change in the number of the terminal devices is expected or when applied to different systems having different number of terminals.

In order to obviate these problems, it has been proposed that a multiplicity of types of systems designed to handle address data of different number of bits are prepared-for the user's selection. This proposal, however, burdens the manufacturers because of the necessity for preparation of systems which operate with address data of a bit number of very few demands. This solution,therefore,is uneconomical and, hence, not preferred.

On the other hand, Japanese Patent Laid-Open No. 6286936, entitled "System for setting address in secondary station" discloses a system in which a plurality of secondary stations are connected in series and the addresses of these serial secondary stations are automatically set in the sequence of the serial connection in terms of count values counted by a counter of a primary station. In this system, however, the addresses of the secondary stations are set in a fixed order, i.e., in accordance with the sequence of the series connection of the secondary stations. In other words, in this system, no consideration has been paid to the fact that the operator can freely set a desired address on the respective secondary stations. This system, therefore, only has a small adaptability and fails to meet a diversified demand.

Accordingly, an object of the present invention is to provide a monitoring/control system having a wide adaptability and capable of operating with a high transmission efficiency.

The present invention provides a monitoring/control system having a central monitoring/control apparatus and at least one terminal device connected to the central monitoring/control apparatus through a communication line so as to be accessible by the monitoring/control apparatus by address polling, wherein:: each terminal device comprises address setting means capable of storing therein an address particular to the terminal device and having a predetermined number of bits, and coincidence detection means for comparing the particular address stored in the address setting means with address data transmitted from the central monitoring/control apparatus so as to determine whether the particular address coincides with the address data, the address data transmitted from the central monitoring/control apparatus having a number of bits which is variable within a range which does not exceed the number of bits of the particular address stored in the address setting means; and the coincidence detection means of each of the terminal devices is arranged to compare the address data (preferably, only) with a portion of the particular address having the same number of bits as the address data, so that the terminal device in which coincidence is detected is accessed by the central monitoring/control apparatus.

Other objects, features and advantages of the present invention will become clear from the following description of the preferred embodiments.

In the drawings: Fig. 1 is a block diagram of an embodiment of the monitoring/control system in accordance with the present invention; Fig. 2 is an illustration of a format of address data to be transmitted from a central monitoring/control apparatus to terminal devices; Fig. 3 is a block diagram of another embodiment of the monitoring/control system of the present invention, incorporating a microcomputer in each terminal device; and Fig.4 is a flow chart showing the flow of the process executed in the monitoring/control system shown in Fig. 3.

Referring first to Fig. 1, a monitoring/control system embodying the present invention has a central monitoring/control apparatus 1 to which one or more terminal devices 20 are connected through a common transmission line 21. In Fig. 1, only one terminal device 20 is shown for the purpose of clarification of the drawings. For the same reason, sensors and so forth as the objects of the monitoring and/or control by the central monitoring/control apparatus l,-connected to the respective terminal devices 20, are omitted.

The system is arranged such that each terminal device 20 can store an address ADo. The address ADo is particular to the terminal device 20 and is composed of N bits, where N being approximately the greatest number which is considered to be necessary in the monitoring/control system. When the bit number N is 20, the system can employ up to about 1,050,000 terminal devices, with each device storing its own address. However, if the system employs, for example, 16 terminal devices 20, the address of each terminal device 20 can be expressed only by four bits.

In such a case, only four bits out of N bits constituting the address ADo, e.g., four bits as counted from the most significant bit, are used as effective address.

On the other hand, the central monitoring/control apparatus 1 is capable of transmitting, in sequence, a start code ST, an address data AD and an address end code ED in accordance with a format as shown in Fig. 2, thereby polling the terminal devices 20.

The format shown in Fig. 2 is digitized with three values: namely, a positive valve (+1), zero (0) and a negative value (-1). The start code ST is expressed by two bits in the form of pulses: more specifically, a negative pulse (-1) and a positive pulse (+1). The start code ST is followed by an address data AD having n bits. Each of the n bits defining the address data AD has the form of a pulse of either zero level (0) or a plus level (+1). The number n of bits of the address data AD is variable within a range which does not exceed N, so that the bit number n can be optimized in accordance with the number of the terminal devices employed in the system. The address end code ED mentioned above is transmitted subsequently to the address data AD. The address end code ED is composed of two bits in the form of a pulse of (-1) level and a pulse of (0) level.The central monitoring/control apparatus 1 polls the terminals devices 20 by transmitting the series of data composed of the start code ST, address data AD and the address end code ED, thereby specifying a terminal device 20. The apparatus 1 then transmits to the specified terminal device 20 a control data CN for the monitoring/control object corresponding to the specified terminal device 20. Subsequently, a monitoring data which represents the result of the monitoring/control operation of the object is sent back as a return data RT from the terminal device 20. Each of the control data CN and the return data RT has a definite number of bits or,alternatively, these data are separated by an end code.

Formats of the control data CN and the return data RT are not described because they do not constitute any critical portion of the present invention.

Although the format shown in Fig. 2 makes use of 2 bits (2 pulses) for each of the start code ST and the address end code ED, this is only illustrative and the start code ST and the address end code ED can have any other suitable forms provided that they are discriminated from other data such as the address data AD, control data CN and so forth.

It is also possible to allocate only one pulse, i.e., one bit, to each of the start code ST and the address end code ED, if the circumstance allows the use of pulses of different levels or widths in addition to the abovementioned three pulses (+1), (0) and (-).

Referring back to Fig. 1, each terminal device 20 includes the following parts: a clock circuit 22 capable of producing a clock signal CLK of a frequency which is synchronous with the frequency of the pulse train, i.e., bit train, of the format as shown in Fig. 2 transmitted from the central monitoring/control apparatus 1; an address setting device 2 in which an address ADo composed of N bits and particular to each terminal device 20 is set; a code detection circuit 5 for detecting a start code ST and an address end code ED; a shift register 3 adapted to fetch the address ADo from the address setting device 2 when a start code ST is detected by the code detection circuit 5; a coincidence detection circuit 4 which is cleared when the start code ST is detected by the code detection circuit 5 and which is adapted to compare, in a bit-by-bit fashion, the address data AD of n bits which are sent in a bitserial manner from the central monitoring/control apparatus 1 with the corresponding n bits out of the N bits determining the address ADo which has been fetched by the shift register 3, thereby detecting the coincidence of the address data AD with the n bits out of the address ADo; a gate circuit 6 adapted to open a gate for a time period corresponding to the number of bits of the control data CN when in receipt of a coincidence signal CO from the coincidence detection circuit 4; a shift register 7 adapted to fetch, when the gate of the gate circuit 6 is open, the control data CN from the central monitoring/control apparatus 1; a gate circuit 8 adapted to open a gate with a time delay corresponding to the bit number of the control data CN after the delivery of the coincidence signal CO from the coincidence detection circuit 4; a shift register 9 adapted to receive the monitoring data, i.e.,the return data RT, from the monitoring/control object (not shown) when the gate of the gate circuit 8 is open; and an impedance conversion circuit 10 adapted to send the return data RT received by the shift register 9 back to the central monitoring/control apparatus 1 after conversion of the return data RT into, for example, electrical signals.

The clock signal CLK from the clock circuit 22 is delivered to the code detection circuit 5, shift register 3, coincidence detection circuit 4,gate circuit 6 and the gate circuit 8 so as to be used as time references in the data sampling performed by each circuit and as a timing signal for sending of the return data RT back to the central monitoring/control apparatus 1.

The coincidence detection circuit 4 includes, for example, an EXCLUSIVE OR circuit and a flip-flop circuit.

In operation, the EXCLUSIVE OR circuit receives both the particular address ADo from the shift register 3 and the address data AD from the central monitoring/control apparatus 1 so as to compare, in a bit-by-bit fashion, the corresponding bits of the address data AD and the address ADo down to n-th bits as counted from, for example, the most significant bit, and produces EXCLUSIVE OR for each of the successive pairs of the corresponding bits. When a discordance is found between the corresponding bits of the address data AD and the address ADo, the coincidence detection circuit 4 stops to compute the EXCLUSIVE OR for further pairs of bits, i.e., stops the comparing operation.

This state of discordance is then latched by the flip-flop circuit. Thus, the coincidence detection circuit 4 delivers the coincidence signal CO only when the discordance state is not latched by the flip-flop circuit at the time when the address end code ED is detected.

The operation of this monitoring/control apparatus is as follows.

An address ADo is set beforehand in each terminal device 20 corresponding to each of the monitoring/control objects. Though each address ADo has N bits, only n bits, e.g., n bits out of the N bits as counted from, for example, the most significant bit, are used as effective address, the bit number n being determined in accordance with the number of the terminal devices 20 which are employed in the monitoring/control system. Therefore, the operator is required to set only the effective address portion in the address setting device 2.

The setting of the effective address portion is conducted in the respective address setting devices of all the terminal devices 20. When the start code ST is delivered to each terminal device 20 from the central monitoring/control device 1, the code detection circuit 5 of each terminal device 20 detects the start code ST so that the coincidence detection circuit 4 is reset in each terminal device. At the same time, the shift register 3 fetches the address ADo of N bits from the address setting device 2.

Subsequently, the central monitoring/control apparatus 1 operates to set up an address data AD of the same bit number n as the effective address portion of the terminal device 20,and delivers the address data AD to the respective terminal devices in a bit-by-bit fashion. Upon receipt of the address data AD, the coincidence detection circuit 4 of each terminal device 20 operates to compare the n-bit address data AD with the n-bit effective address portion of the address ADo fetched by the shift register 3, in a bit-by-bit fashion. This comparison is executed until the address end code ED is received from the central monitoring/control apparatus 1, and whether the address data AD coincides with the effective address portion is determined at the time when the address end code ED is detected by the code detection circuit 5.

When coincidence is obtained between the n-bit address data AD and the n-bit effective address, the coincidence detection circuit 4 produces the coincidence signal CO.

As a result, the gate of the gate circuit 6 in this terminal device 20 is opened to allow the control data CN from the central monitoring/control apparatus 1 to be delivered to the shift register 7 of this terminal device 20 in a bit-serial manner. The bit-serial data is then converted into parallel data by the shift register 7 and the thus obtained parallel control data is delivered to the monitoring/control object connected to this terminal device 20.

As has been described, the central monitoring/control apparatus 1 is capable of delivering the required control data CN to a specific monitoring/control object through the terminal device 20 associated with such monitoring/control object. After the delivery of the control data CN to the monitoring/control object, the gate circuit 8 is opened so that the monitoring data, which represents the result of the control effected by the control data CN, is fed to the shift register 9 as the return data RT. The shift register 9 then converts the return data RT into a serial data which is then supplied to the impedance conversion circuit 10.

The impedance conversion circuit 10 converts the serial data into electrical current signal and then sends the thus obtained electrical current signal back to the central monitoring/control apparatus 1, whereby the monitoring/control operation is completed with the specified monitoring/control object.

Any demand for employment of a greater number of the terminal devices 20 in the monitoring/control system can be met by an increase in the number n of bits of the effective address portion and a corresponding increase in the number n of bits of the address data AD within the range which does not exceed the bit number N of the address ADo. For instance, a demand for modification of a monitoring/control system employing 16 terminals devices 20 into a system employing 1024 terminal devices 20 can be met by increasing the number n of bits of the effective address portion and the number n of bits of the address data from 4 to 10.

It will be seen that, in the above-described embodiment of the monitoring/control system of the present invention, expansion of the monitoring/control system for greater number of terminal devices can be achieved simply by changing the number n of bits of the effective address portion and the address data AD, in contrast to conventional systems of this kind which require a significant change in the system hardware.

Conversely, a demand for a reduction in the number of the terminal devices 20 employed in a system can be met by a reduction in the number n of bits of the effective address portion and corresponding reduction in the number n of bits of the address data AD. For instance, a modification of a monitoring/control system employing 16 terminal devices 20 into a system employing 8 terminal devices 20 can be accomplished by reducing the number n of bits of the effective address portion and the address data AD from 4 to 3.

As will be seen from the foregoing description, in the monitoring/control system embodying the present invention, the operator can freely set the address ADo, i.e., the effective address as desired in the address setting device 2, and furthermore can easily and freely change the number n of bits of the effective address portion and the number n of bits of the address data. Thus, the number n of bits of the effective address portion and the number n of bits of the address data AD can be determined at the discretion of the operator in accordance with factors such as the scale or size of the building in which the monitoring/control system is to be installed and/or the number of the terminal devices 20 to be used in the system. The monitoring/control system of the invention operable with the address data AD of the thus determined bit number n does not require transmission of useless bits of the address data AD, thus ensuring a high transmission efficiency and offering a wider adaptability. In particular, a further widening of application of the monitoring/control system together with a remarkable reduction in the production cost is attainable if each of the terminal devices 20 is an integrated circuit.

In the described embodiment, the central monitoring/control apparatus 1 is capable of transmitting address data AD of the same bit number n as that of the effective address portion of the address ADo particular to the terminal device 20. The invention does not exclude such a modification that the address data transmitted by the central monitoring/control apparatus 1 has bits of a number which is smaller than the number of bits of the effective address portion of the address ADo. In such a modification, the coincidence detection circuit 4 compares the address data AD from the central monitoring/control apparatus 1 with such a part of the effective address that has the same number of bits, as counted, for example, from the most significant bit of the effective address portion, as the number of bits of the address data AD.Such a modification enables polling of the terminal devices 20 in terms of groups.

It is assumed here that a plurality of terminal devices 20 are installed in groups at a number of locations within a building, i.e., that one group of terminal devices are installed at a certain location of a building and some others are installed at a different location of a building.

In such a case, all the terminal devices of a group may have addresses ADo, i.e., effective addresses in which upper bits as counted from the most significant bits coincide with each other. With this arrangement, the central monitoring/control apparatus can access and control the terminal devices in a group-by-group manner by transmitting the address data AD having bits of a number approximately corresponding to the number of the groups of the terminal devices.

Fig. 3 is a block diagram of the monitoring/control system, in which a microcomputer is used in each terminal device.

A terminal device, denoted by 30, is under the control of a central processing unit (referred to as "CPU") which is a microcomputer 13. A transmission circuit 11 is connected to the CPU 13 through an interface 15.

Similarly, an address setting device 12 is connected to the CPU 13 through an interface 16. A memory device 14 capable of storing data such as the results of control is also connected to the CPU 13. The control data CN is adapted to be delivered through an interface 17 to the monitoring/control object (not shown) such as a sensor, and the monitoring or return data RT from such object is adapted to be delivered to the CPU 13 through the interface 17.

The operation of the monitoring/control system ofthe type shown in Fig. 3 will be described with specific reference to Fig. 4 which is a flow chart of the control process.

An initializing routine is executed in Step a when the power supply is turned on. Then, a format such as that shown in Fig. 2 is transmitted from the central monitoring/control apparatus 1 to each terminal device 30.

When the first data or pulse is received by each terminal device 30 in Step b, the CPU 13 of each terminal device 30 operates to determine whether the received data is the start code ST in Step c. If the start code ST is confirmed, the process proceeds to Step e in which a judgment is conducted as to whether the data which is received subsequently to the start code ST is a negative pulse which represents the address end code ED. If the answer is NO, the CPU 13 judges that this data corresponds to one of the bits of the address data AD and operates to enable the memory device 14 to store this data therein (Step f). If one or more bits of the address data have already been stored in the memory device 14, these bits are shifted one by one to the left as viewed in the sequence of bits while storing the data of the newly read bit (Step q).

When the data of all the bits of the address data have been stored, the process proceeds to Step h which executes counting of the number of bits of the address data AD. The process then returns to Step d so as to read next data. If the next data is judged to be a negative pulse which represents the address end code ED in Step e, the CPU 13 sequentially extracts, from the address ADo set in the address setting device 12, data having bits of the same number as that counted in Step h, as counted from the most significant bit of the address ADo, and determines the thus extracted data as being an effective address (Step i).

After the extraction of the effective address, the process proceeds to Step i in which the extracted effective address is compared with the address data AD. This comparison is executed in each terminal device 30 and any terminal device which shows discordance between the extracted effective address and the address data AD is determined to be one of the terminal devices which are not to be accessed by the central monitoring/control apparatus 1. The process with such a terminal device 30, therefore, returns to Step b for commencing the routine for detecting the start code ST.

If coincidence is obtained during the comparison executed in Step i between the effective address of one of the terminal devices 30and the address data AD transmitted from the central monitoring/control apparatus 1, such terminal device 30 is decided to be the very one that is to be accessed by the central monitoring/control apparatus 1.

The CPU 13 of the thus specified terminal device 30 then starts to execute a routine for receiving the control data CN from the central monitoring/control device 1 in Step k.

The data of all the bits of the control data CN are thus transmitted from the central monitoring/control apparatus 1 and are received by the terminal device 30 and then to the monitoring/control object associated with this terminal device 30,thus monitoring and/or controlling the object.

Return data RT representative of the result of the monitoring and/or the control is then derived from the monitoring/control object and picked up by the terminal device 30, which then conducts an operation for enabling the return data RT to be sent back to the central monitoring/control apparatus 1 in a bit-by-bit fashion (Step m). The monitoring and/or control of the aimed terminal device 30 is thus completed and the process returns to the first routine which begins with the execution of Step b for reading of the bit-serial data transmitted from the central monitoring/control apparatus 1.

The transmission of the address end code ED representative of the completion of transmission of the address data AD from the central monitoring/control apparatus 1 is not always necessary and may be dispensed with if suitable measure is taken to inform the terminal device of the completion of receipt of the address data.

For instance, the code detection circuit 5 used in the described embodiment for the purpose of detecting the start and address end codes may be substituted by a combination of a start code detection circuit and a presettable counter circuit in which a predetermined bit number is set. In this case, the counter circuit starts the counting operation when the start code ST is detected by the code detection circuit 5 and overflow signal from the counter circuit can be used in place of the address end code ED.

Claims

1. A monitoring/control system having a central monitoring/control apparatus and at least one terminal device connected to the central monitoring/control apparatus through a communication line so as to be accessible by the monitoring/control apparatus by address polling, wherein:: each terminal device comprises address setting means capable of storing therein an address particular to the terminal device and having a predetermined number of bits, and coincidence detection means for comparing the particular address stored in the address setting means with address data transmitted from the central monitoring/control apparatus so as to determine whether the particular address coincides with the address data, the address data transmitted from the central monitoring/control apparatus having a number of bits which is variable within a range which does not exceed the number of bits of the particular address stored in the address setting means; and the coincidence detection means of each of the terminal devices is arranged to compare the address data with a portion of the particular address having the same number of bits as the address data, so that the terminal device in which coincidence is detected is accessed by the central monitoring/control apparatus.

2. A monitoring/control system according to claim 1, wherein the number of bits of the particular address stored in the address setting means is approximately equal to the maximum number of the terminal devices which it is possible to incorporate in the monitoring/control system, and only a portion of the particular address is used as an effective address which is to be compared with the address data transmitted from the central monitoring/control apparatus.

3. A monitoring/control system according to claim 1 or claim 2, wherein the number of bits of the address data transmitted from the central monitoring/control apparatus is approximately equal to the number of the terminal devices actually incorporated in the system.

4. A monitoring/control system according to at least claim 2, wherein the address data transmitted from the central monitoring/control apparatus has the same number of bits as the effective address.

5. A monitoring/control system according to any one of the preceding claims, wherein the terminal devices are arranged in groups and the number of bits of the address data transmitted from the central monitoring/control apparatus is approximately equal to the number of the groups of the terminal devices.

6. -A monitoring/control system according to at least claim 2, wherein the number of bits of the address data transmitted from the central monitoring/control apparatus is not greater than the number of bits of the effective address in order to enable polling of the terminals in a group-by-group fashion.

7. A monitoring/control system substantially as described with reference to the accompanying drawings.

8. All novel features and combinations thereof.