GB1584004A - Data processing system - Google Patents

Description

PATENT SPECIFICATION ( 11) 1 584 004

e ( 21) Application No 26629/79 ( 22) Filed 1 Jun 1977 ( 19) ( 62) Divided out of No 1584003 ( 31) Convention Application No 693551 ( 32) Filed 7 Jun 1976 in ' 3 t ( 33) United States of America (US) tn ( 44) Complete Specification Published 4 Feb 1981 _ ( 51) INT CL 3 GO 6 F 11/30 ( 52) Index at Acceptance G 4 A FM ( 54) DATA PROCESSING SYSTEM ( 71) We, AMDAHLCORPORATION, a Corporationorganised andexistingunderthe laws of the State of California, United States of America, of 1250 East Arques Avenue, Sunnyvale, State of California 94086, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is

to be performed, to be particularly described in and by the following statement 5

The present invention relates to a data processing system.

In high-speed, large-scale data processing systems, the ability to detect the state of any latch or other circuit within the data processing system is desirable particularly for analysis and detecting of fault conditions Prior art systems have frequencly direct-wired key points within the data processing system to a control panel or console to illuminate the console 10 lamps to thereby give an indication of the status of storage circuits within the system The direct-wired approach however becomes unwieldly for large data processing systems because the number of illuminating lamps on the system console becomes too large for useful or convenient operator analysis.

Other prior art systems have employed the computing capability of the data processing 15 system to log out data using the conventional data paths of the data processing system to store the state of circuits within prescribed locations of systems storage The use of the conventional data paths within the storage system has the problem that if the data path or control circuitry associated with that data path is faulty, the information lagged out is in error making fault location and isolation difficult and time consuming 20 According to the present invention there is provided a data processing system implemented employing integrated circuit chips each having a plurality of circuits in first data paths for storing information in accordance with data manipulations carried out in accordance with first programs of instructions, the improvement comprising, scanout apparatus on each chip for addressing and accessing the states of said circuits 25 independently of said first data paths and in accordance with second programs of instructions,.

and a digital computer responsive to said second programs for addressing circuits on each of 3 said chips and for receiving the data indicating the state of said addressed circuits.

Specific embodiments of the invention will now be described with reference to the accom 30 panying drawings, in which:

Fig 1 depicts a block diagram of the overall data processing system of the present invention.

Fig 2 depicts a schematic representation of the console unit of the system of Fig 1.

Fig 3 depicts a schematic representation of the interface controller and the console control 35 interface within the console unit of Fig 2.

Fig 4 depicts a schematic representation of the manner in which the data processing system of Fig 1 is arrayed with multi-chip carriers (MCC) which are addressed and accessed by the console control interface of Fig 3.

Fig 5 depicts a schematic representation of the physical array of a typical MCC 40 Fig 6 depicts a schematic representation of the manner in which the chips on a typical MCC are logically arrayed.

Fig 7 depicts a schematic representation of several data paths within the execution unit of the Fig 1 system.

Fig 8 depicts a schematic representation of the chip arrangement of the 1 H register which 45 2 1,584,004 2 forms part of the data path in the apparatus of Fig 7.

Fig 9 depicts a schematic representation of the chip associated with one bit in the fig 8 circuitry.

Fig 10 depicts a schematic representation of the log chip associated with the MCC containing the circuitry of Fig8 5 Fig 11 depicts a schematic representation of an alternate embodiment of the chip selection circuitry.

DETAILED DESCRIPTION

Overall System In Fig 1, the data processing system of the present invention is shown to include a main 10 store 2, a storage control unit 4, an instruction unit 8, an execution unit 10, a channel unit 6 with associated I/O and a console unit 12 The system of Fig 1 operates under control of principal system instructions where an organized group of those instructions forms a system program System instructions and the data upon which the instructions operate are introduced from the I/O equipment via the channel unit 6 through the storage control unit 5 into 15 the main store 2 From the main store 2, system instructions and data are fetched by the instruction unit 8 through the storage control 4 and are processed so as to control the execution within the execution unit 10 The system of Fig 1 is described in more detail in United States Patent No 3840861 which description is hereby incorporated by reference in the present specification for the purpose of teaching the overall general operation of an 20 environmental instruction-controlled data processing system.

Referring to Fig 4, the logic and other circuits comprising all or a major portion of the system of Fig 1 are implemented on multi-chip carriers (MCC) 602 where each carrier includes a plurality of integrated circuit chips as generally indicated in Fig 5 For example, up to 64 multi-chip carriers 602 indicated as MCC( 0,0,,MCC( 7,7) Each of those carriers 25 typically includes up to 42 chips in a 6 X 7 rectangular array as indicated in Fig 5.

Console Unit In Fig 2, the console unit 12 of Fig 1 is shown in further detail Console 1 includes a digital computer 501 which is interconnected with a 32 K memory 502 in a conventional manner.

The digital computer 501 is connected to a plurality of controllers such as a disc controller 30 516, a channel controller 411, a panel controller 513 and an interface controller 511.

Additional controllers may be connected to the indicated computer 501 in an analagous manner.

The disc controller 516 interfaces between the computer 501 and 256 K disc file system 528 The channel controller 411 is one of the channel controllers associated with the channel 35 unit 6 of Fig 1 The panel controller 513 interfaces between the digital computer 501 and the control panel 524 The interface controller 511 interfaces between the console control interface 525 and the digital computer 501.

The computer 501 is typically a Nova 1200 computer marketed by Data General Corporation The details of operation of such a computer and the manner in which control units such 40 as the controllers 411, 511, 513 and 516 of Fig 2 interface with the computer 501 are described in the publication entitled, "How to use the Nova Computers", DG NM-5, Data General Corporation, April, 1971.

The interface controller 511, connected to the digital computer 501 by the 48-bit bus 535 connects to the console control interface by the bus 533 The console control interface 45 (CCI)525 is connected via a scanout bus 436 to circuits throughout the data processing system of Fig 1 The I-unit C-unit, S-unit interconnections from the console control interface 525 are further described hereinafter.

Console Control Interface and Interface Controller In Fig 3, the console control interface 525 and the interface controller 511 and their 50 interconnections are shown in further detail The Console control interface (CCI)525 includes a 16-bit command register (CR)551 having a 16-bit command bus output 540 which connects as an input to the I-unit and C-unit as hereinafter described Interface 525 further includes 16-bit addressing registers 552 and 553 which form the 32-bit output address bus 542 which interconnects with address paths in the I-unit and S-unit of the data processing 55 system.

Interface 525 further includes 16-bit data registers 554 and 555 having outputsforming the 32-bit console data bus 543 which functions as a console data input to the data paths in the C-unit, S-unit and I-unit of the data processing system of Fig 1.

The console registers 551 through 556 and the gates 561 through 565 are addressed by the 60 decoded outputs from the decoder 567 which decodes and selects one of those eleven entities in response to the address in the 4-bit storage address register 574 within the interface controller 511.

Interface 525 additionally includes a 9-bit scanout address register 556 which specifies, via 9-bit scanout address bus 590, circuits within the data processing system which are to be 65 3 1,584,004 3 scanned out.

Interface 525 further includes the 64-bit scanout data bus 591 which is connected to the 16-bit scanout gates 561 through 564 Also, a 16-bit gated state bus 592 connects to the state gates 572 to the console computer 501 via selection circuit 576 and bus 535 the decoder 567 receives the 4-bit input from the storage address register 574 and decodes that 4-bit address 5 to one of the eleven lines 621-1 through 521-11 The select lines 621-7 through 621-11 are operative to select the scan gates 561 through 564 and the state gate 565, respectively The gates 561 through 565 are each 16-bits and receive the buses 634-1 through 634-4 which form the 64-bit scanout data bus 591 The gated state bus 592 derives state information from the I-unit in the data processing system of Fig1 10 Interface 525 additionally includes the console interface control (CIC) 570 which includes logic circuitry establishing outputs in response to inputs which are collectively identified as lines 541 Specifically, the START line functions to initiate clock signals in the I-unit for establishing timing signals throughout the system of Fig 1 The S, I and C VALID lines 545, one for eachof the S, I and C units, respectively, function to signal when one or more of the 15 respective selected units is to be energized to receive commands from the console unit When the respective S, 1 and C units have received a VALID signal they signify receipt of that signal via the S, I and C COMP lines 544, one for each of the units S, I and C, respectively The I-unit active state line 595 signals the STOP, PSW WAIT, CHECK STOP and METERING state conditions as they occur in the system of Fig 1 The OP END line senses the timing pulses 20 associated with the system of Fig 1 and if the delay between pulses exceeds a fixed duration an error condition exists in the system of Fig 1 The OP END line is input to a hang detect circuit 581 which senses the time duration between timing pulses and produces an output to signal an undue delay.

The control 570, the hang detect circuit 581, and the STOP line through the active state 25.

(AS) gates 582 indicate the state of the Fig 1 system via the lines 584 connected to the select circuits 576 Gates 583 sense the 8-bit interruption mask register (IMR) 579 The gates 582 and the register 579 have a one-for-one bit correlation which is for bits 0, 1,, 7 the commands S COMP, C COMP, STOP, PSW WAIT, CHECK STOP, HANG DETECTOR and METERING, respectively 30 The interrupt Mask register 579 controls the settings of the DONE line from gate 583.

Since there is a one-for-one correspondence between the bits in the IMR 579 and the bits in the active state gates 582, the activization of a bit in the active state gate sets the DONE line if the corresponding bit in the register 579 is not set If the bit in register 579 is set, then the DONE line output from gate 583 is not set 35 The enable register 578 stores three bits of information which define which one or ones of the S, I and C VALID lines 545 are to be energized Bit 0 signifies selection of the S-unit, bit 1 the selection of the I-unit and bit 2 the selection of the C-unit The remaining decoded conditions of the 3 bits in the register 578 are "don't care" conditions.

The CIC 570 is responsive to an input START line which also causes energization of the 40 output START line Additionally the START CIC input line initiates operation of the control circuitry 570 The input line CLEAR CIC functions to clear the CIC logic circuit 570 in anticipation of a new command for the Fig 1 system from the computer 501.

Multi-chip Structure Referring now to Fig 4, the scanout address bus 590 from the scanout data register 556 of 45 Fig 3 connects in parallel to a plurality of MCC's 602 for addressing a particular chip on each MCC and for further addressing a particular latch on the address chip for each MCC The state of the addressed latch appears as an output on the respective one of the scanout lines 603 For example, the addressed latch on MCC( 0,0) has its output on scanout line 603 ( 0,0).

In a similar manner, each of the 64 MCC's of Fig 4 has a corresponding output line 603 50 producing, therefore, the 64-bit bus 591 Bus 591 is the scanout data bus 591 which connects as an input to the scan gates 561 through 564 in Fig 3.

Referring now to Fig 5, a typical MCC 602 is shown comprised of 42 chips 606 The chips are arrayed, for convenience, in seven rows numbered 1 through 7 and in six columns lettered A through F Each of the logic chips 606 includes a plurality of circuits for implementing the 55 logical and storage functions carried on in the system of Fig 1 Further, at least one of the chips, for example, chip 1 F in Fig 5 is a scanout or log ship which receives the 9-bit scanout address bus 590 and provides the 1-bit scanout line 603 which, together with the other one-line scanouts from the other MCC's, forms the scanout data bus While the location 1 F has been selected for the log chip in Fig 5 any one of the chip locations may in fact contain the 60 log chip since the physical location in the array is not critical In Fig 5, each MCC is typically shown including up to 42 chips where each chip has a unique physical location on its chip carriers.

In Fig 6, the physical MCC of Fig 5 is redefined in terms of its logical accessibility by the scanout apparatus of the present invention The logical MCC of Fig 6 is defined to include 32 65 ' 1,584,004 4 1,584,004 4 addressable logical chips were each logical chip 608 in Fig 6 includes at least one physical chip 606 of Fig 5 Because there are only 32 addressable chips in Fig 6, each logical chip 608 may include a non-addressable physical chip 606 or some portion of a physical chip 606 for convenience The log chip 611 in Fig 6 corresponds to the chip 1 F in Fig 5 The logical chips C( 0,0), C( 0, 1),, C( 0,7) of Fig 6 are organized in a first one of four rows The chips 608 in 5 Fig 6 may correspond to any combination of chips 606 in Fig 5 The log chip 611 in Fig 6 receives as an input the 9-bit scanout address bus 590 and provides one bit on output line 603 of the scanout data bus 591 of Fig 3 and Fig 4 Additionally, the log chip 611 provides eight output column select lines 614-1 through 614-8 and four chip select lines 613 The log chip 611 further receives the 4-bit bus 612 which iscomprised of fourrowscan lines 612-1 through 10 612-4 Each row line 612-1 through 612-4 receives the scanout data from a row of eight logical chip 608 all OR'ed together to form a common line.

The log chip 611 in Fig 6 operates to receive the 9-bit address on bus 590 The three high order bits of that 9-bit bus 590 are decoded to select one of the eight lines 614 The selected one of the lines 614, for example, line 614-1, selects the corresponding column, for example, 15 column C( 0,0), C( 1,0) C( 2,0) and C( 3,0) The four low order bits of the 9-bit address on line 590 are transmitted via bus 613 to each of the chips 608 for selecting one of up to 64 circuits on each chip 608 The state of the selected circuit on each chip is then gated out to the corresponding row line 612-1 through 612-4 The remaining two (middle) address bits on the bus 590 are employed in the log chip 611 to select one of the four row scanout lines 612 for 20 transmission as the output on scanout bus line 603 Further details of the scanout arrangement are now described in connection with a typical example The example described is the 1 H register in the execution unit 10 of the system of Fig 1 as shown in Fig 7.

In Fig 7, the 1 H register 24 is shown between the LUCK unit 20 and the byte adder 32 all of which form part of the execution unit 10 of the system of Fig 1 Further details of the 1 H 25 register and its operation in the execution unit of the system of Fig 1 are described in United States Patents Nos 3840861, 3792362 and 3814925 Those details relating to the 1 H register are hereby incorporated by reference in this specification for the purpose of teaching them in this specification.

In general, the 1 H register 24 is a 32-bit register which receives input data from the LUCK 30 unit 20 and connects its output among other places, to the byte adder 32 Information is latched into register 24 by a clock pulse on line 631 from a clock 102 The details of the clock operation for latching data into the register 24 are described in United States Patent No.

3792362 In that application, a typical bit, identified as bit location 124, is described as including a latch circuit The latch circuit 124 of register 24 in Fig 7 is shown in further detail 35 in connection with Figs 8 and 9.

In Fig 8, bit 124, representing bit position 24 of the 32 bits, 0 through 31, is located on chip 606 1 In addition to bit 24 of register 24 in Fig 7, bits 25 through 31 are also shown as being located on chips 606-2, 606-3,, 606-8 which are designated as BIT 25, BIT 26,, BIT 31, respectively Bit 24, designated 606-1, is one of the chips 606 like that previously 40 described in connection with Fig 5 Similarly, each of the other chips 6062 through 606-8 are also typically identical to the chips 606 in Fig 5 The eight chips 606-1 through 606-8 form a part of the eight chips which form a row, such as row 0 in Fig 6 which have common OR'ed output 612-1.

In addition to the chips 606-1 through 606-8, the logical chips of Fig 6 within a row include 45 further logic not on the same physical chips For example, one logical chip C( 0,0) includes physical chip 606-1 and logic gate 623-1 Similarly, the logical chip of Fig 6 C( 0, 1) includes the physical chip 606-2 of Fig 8 and the column select gate 623-2 The column select gates 623-1 and 623-2, in a preferred embodiment, are on different physical chips In a similar manner, chips 606-3, 606-4 and 606-5 of Fig 8 are three different physical chips and each are 50 associated with the column select gates 623-3, 623-4 and 623-5, repsectively The column select gate 623-3 through 623-5 are, in a preferred embodiment, on a single physical chip.

Similarly, chips 606-6, 606-7 and 606-8 are each three different physical chips while the corresponding select gates 623-6, 623-7 and 623-8 are located on a different physical chip In the manner described, the circuitry 617-1, arrayed on physical chips as indicated, forms one 55 row of C( 00) through C( 0 7) of logical chips 608.

In the same manner that the circuitry 617-1 represents one row of eight logical chips for an MCC of the 601 type, similar additional circuitry 617-2, 617-3 and 617-4 represents rows of logical chips which each provide an output line 612-2, 612-3 and 612-4, repsectively The four lines 612-1 through 612-4 form the 4-bit bus 612 Each of the row circuits 617-1 through 60 617-4 receive the eight column select lines 614 and the four chip address lines 613 derived from the LOG CHIP 611 of Fig 6.

Single Chip Structure Further details of the BIT 24 chip 606 1, which represents bit 24 in the 1 H register 24 of Fig 7, are shown in Fig 9 In Fig 9, chip 606-1 includes latch circuit 1241 which is bit 24 of 65 1,584,004 1,584,004 the bits 0 through 31 of the 1 H register 24 in Fig 7 Ltch 124-1 receives its input from LUCK unit 20 via the lines 652, one of which is a data line and the other of which is a control line.

Similarly, latch 124-1 receives inputs from the shifter via lines 653, one of which is a control line and one of which is a data line and from the adder via lines 654, one of which is a data line and one of which is a control line Also, latch 124-1 has a synchronous reset input via line 651 5 for resetting the latch at appropriate times in the operation of the data processing system.

Additionally, latch 124-1 receives inputs on lines 631 and 632 for controlling the clocking of the latch Line 631 is an input from the clock 102 while line 632 is an inhibit control to prevent clocking of the latch 124-1 Latch 124-1 has an output on line 656 which connects to a phase splitter 637 which is the first level, I, of logic associated with the byte adder as described in 10 United States Patent No 3814925 In addition to connecting to the phase splitter 637 which constitutes the normal data path of the system of Fig 1, latch 124-1 has an output to an additional phase splitter 638 which constitutes the beginning of the scanout data paths of the system of Fig 1.

In addition to latch 124-1, the chip 606-1, in a preferred embodiment of the present '15 invention, includes a latch 124-2 which is associated with BIT 24 in the 2 H register 25 of the Fig 7 circuitry Similarly, the chip 606-1 includes latch circuit 124-3 and 124-4 corresponding to bits 24 of the 1 L register and the 2 L register which are additional registers associated with the execution unit 10 but which are not otherwise specifically shown in the present specification The output from latch 124-2 on line 657 similarly connects to the phase splitter 637 and 20 to the phase splitter 638 as do the outputs from the latches 124-3 and 124-4.

The phase splitter 638 includes a gate 639 which transmits the state of latch 124-1 as indicated on line 656 to the selection gate 641 Selection gate 641 is one of four gates in the selector circuit 640 for appropriately selecting which one of the four latches 124-1 through 124-4 is to be connected with an output on line 643 The selection of which of the gates in the 25 selector 641 is under control of the decoder 642 which includes two bipolar gates 645 and 646 responsive to two bits on lines 613-1 and 613-2 of the 4-bit bus 613 The two bits on lines 613-1 and 613-2 are decoded to uniquely select one of the four gates in the selector circuit 640 When the +LA and +LB lines from gates 645 and 646 are energized, the gate 641 is selected providing the output of line 643 as an input to gate 644 which provides the outputs 30 on line 619 Referring again to Fig 8, the output on line 619 is the selected chip BIT 24 output In the circuitry 606-1 of Fig 9, only two of the four chip address lines of bus 613 are employed, namely lines 613-1, 613-2 The two binary addresses specified by those two lines uniquely define one of the four latches 124-1 through 124-4 Additional lines 613-3 and 613-4 may be employed so that a total of up to 16 latch or other type circuits per chip may be 35 employed in accordance with a preferred embodiment of the present invention The output on line 619, in accordance with Fig 9 represents one or four latches on the chip 606-1 When more latches are employed, up to 16, the line 619 output would represent one out of sixteen latch states as addressed by the address occurring on bus 613.

Log Chip Structure 40 In Fig 10, further details of the log chip 611 of Fig 8 are shown Log chip 611 receives the nine input address bits on input bus 590 The three high order bits on lines 590-1, 590-2 and 590-3 are input to the column select decoding circuitry 626 where, in a conventional manner, they are decoded to sele ct eight output lines 614 The eight lines 614-1 through 614-8 from bus 614 which is connected as the inputs to each of the row select circuits 617-1 through 617-4 45 of Fig 8 In Fig 8, those column select lines are operative to select one at a time, in accordance with the three input address bits, the gates 623-1 through 6238, respectively.

The next two high-ordered bits of address bus 590 appear on lines 590-4 and 590-5 where they serve as inputs to the row decode and select circuitry 627 In circuitry 627, the two bits on lines 590-4 and 590-5 are decoded to select one of the four gates 661-1 through 661-4 which 50 receives the row state lines 612-1 through 612-4, respectively, on the bus 612 from the MCC of Fig 8 The selected one of the four lines 612 in response to the coded information in the input bits 590-4 and 590-5 appears as an output on line 603 which is one of the 16 bits in the bus 634-1 which is one of the 64 bits in the 64-bit bus 591 which is shown in Fig 4.

Similarly, the four low order bits on lines 590-6 through 590-9 are powered in the power 55 drive circuit 628 and retransmitted via bus 613 to each of the chips on the MCC 601 of Fig 6 and particularly to the row chips 617-1 of Fig 8 The signals on the lines 590-6 through 590-9 appear as the identical signals on the lines 613-1 through 613-4, respectively.

OPERATION Principal and Secondary Apparatus 60 The principal apparatus of Fig 1, under control of principal instructions processed by the instruction unit 8, fetches information from the storage control 4 and the main store 2.

Execution unit 10 executes principal instructions under control of information from the instruction unit 8 By way of example, some principal instructions in the principal apparatus employ an adder in execution unit 10 which is shown in more detail in Fig 7 In executing a 65 6 1,584,004 6 7 principal instruction, information is input to the adder 32 of Fig 7 through the LUCK unit 20 where it is stored in the 1 H register 24 and the 2 H register 25 Information latched in the registers 24 and 25 is added by the adder 32 to form results which appear in the register 38.

The operation of the Fig 1 principal apparatus in executing principal instructions is described in United States Patents Nos 3840861, and 3792362 5 The latching of data into the register 24 occurs specifically at a time controlled by the clock signal on line 631 which line operates, as shown in Fig 9, to set each of the bit positions, 0 through 32, of register 24 and specifically bit 24 of the 1 H register designated as 124-1 The setting of the latch 124-1 and the other bit positions in register 24 are generally under control of the principal apparatus in carrying out the instructions of a principal instruction stream 10 The console computer 501 of Fig 2 is operative to access information from address locations in the principal apparatus of Fig 1 in accordance with a program of secondary instructions The operation of the secondary apparatus and the program of secondary instructions in computer 501 is indpendent of the operation of the principal apparatus in executing the principal instructions 15 In a preferred embodiment, address locations within the principal apparatus of Fig 1 are specified in accordance with a 16-bit binary address generated by computer 501 That address has the following significance.

Bits 0 and 1 specify one of four groups of 16 MCC's and particularly their output lines 603.

Bits 0 and 1 are decoded to select one of the four scan gates 561 through 564 in Fig 3 thereby 20 selecting one of four groups of 16 lines.

Bits 2 through 5 specify one out of the 16 information bits appearing on that one group of 16 lines selected by Bits 0 and 1.

Bit 6 specifies whether or not the selected information bit from the 64 MCC's of Fig 4 must be inverted or not in order to have correct polarity Bit 6 is useful in a preferred embodiment 25 of the present invention since a preferred technology employs inverting logic In inverting logic, the existence of an odd number or an even number of logic levels in transmitting information to the scan gates determines whether the information has correct or inverted polarity By using Bit 6 in the present addressing format, addressed information may be arbitrarily returned to the scan gates without the need for requiring that either an odd number 30 or an even number of logic levels be employed By appropriately setting Bit 6 the correct polarity is established for each information bit accessed. Bits 7 through 9 select one of eight columns of chips 608 in Fig 6 Bits 7

through 9 are three of the nine address bits output on scanout address bus 590 of Fig 3.

Bits 10 and 11 select one of four rows of chips 608 in Fig 6 Bits 10 and 11 are two of the 35 nine address bits on scanout address bus 590.

Bits 12 through 15 are four bits which select one of up to 16 circuits on each of the chips 608 in Fig 6 Bits 12 through 15 are the four remaining bits of the nine address bits on bus 590 of Fig 3.

Addressing of IH Register Bit 24 40 While any circuit location within the principal apparatus can be made addressable for accessing by the console computer 501 a particular example selected for explanation is the 1 H register 24 and specifically the bit 24 location therein as shown in Fig 7.

Bit 24 of the 1 H register 24 has the following 16-bit binary address:

45 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 In the binary address of bit 24, Bits 0 and 1 represent a binary 3 which signifies that the SCAN 2 gate 563 will be the gate energized Gate 563 receives the addressed information 50 from the principal apparatus and specifically the 16 lines 603 from the MCC's MCC( 0,4), MCC( 14) MCC( 7 M 4) and MCC( 0,5), MCC( 1,5) MCC( 7,5).

Bits 2 through 5 of the bit 24 address represent a binary 10 which means that the desired information bit will appear on the tenth MCC MCC( 1,5), in the group of MCC's specified by Bits 0 and 1 55 The 0 in Bit 6 of the above binary address indicates that no inversion is required in the information returned for bit 24 of the 1 H register.

The all O's for the column select Bits 7 through 9 and for the row select Bits 10 and 11 signify that bit 24 of the 1 H register is on the chip located in the 0 column and the 0 row of chips Specifically, referring to Fig 6, the 0 column and 0 row is chip C( 00) 60 Referring to Fig 10 Bits 7, 8 and 9 are input on lines 590-1 590-2 and 590-3 to select the O column output line 614-1 of the eight lines 614 That line 614-1 in Fig 8 is operative to select the O gate 623-1 which receives as its other input the output on line 619 from the bit 24 location 606-1 in the O column of the O row 617-1 Simultaneously, the rows 617-2, 617-3 and 617-4 also select a O column output on their lines 612-2, 612-3 and 612-4 65 1,584,004 1,584,004 In Fig 10, Bits 10 and 11 for row select are input on lines 590-4 and 5905 and are decoded to select the gate 661-1 which thereby functions to select from the four row lines 612 the 0 row line 612-1 which is derived from Fig 8.

In Fig 10, Bits 12, 13 and 14 and 15 are input on the lines 590-6 through 590-9 which 5 appear on the output bus 613 which in turn is input to the chips of Fig 6 including chip C( 0,0) which is chip 606-1 in Figs 8 and 9 In Fig 9, two of those four bits are actually employed in a preferred embodiment, specifically the two bits on lines 613-1 and 613-2 Since Bits 12 through 15 are O 's, they enable the gates 645 and 646 with + LA and + LB in the 0 state The 0 state of those two outputs are connected as inputs in the decoder 640 and operate to enable 10 gate 641 with O 's on inputs +LA and +LB With gate 641 thus enabled, the output of gate 641 is controlled by the state of line 656 ' from gate 639 Gate 639 connects from the inverting output of latch 124-1 on line 656 The inverted output on line 656 is, of course, the inverse of the addressed bit 24 of the 1 H register.

The output on line 656 is inverted in gate 639, in gate 641, in gate 644, in gate 623-1 in Fig 15 8, and in gate 661-1 in Fig 10 providing the addressed one of the 64 inputs on line 603 to the 64-bit bus 591 The number of inversions from line 656 to line 603 of Fig 6 is five which when coupled with the inverted output itself on line 656 presents the correct polarity to the scan gate 563 of Fig 3.

Console Computer Program of Instructions 20 The console computer 501 of Fig 2 operates through the interface control 511 and the console control interface 525 to carry out the required addressing and accessing of information in the principal apparatus of Fig 1 in accordance with a secondary program of instructions as given by the following TABLE I:

25 TABLE I

51 XLOGB: STA' 3,2 52 NORM: LDA 1,LGAMK 53 AND 0,1 30 54 SUB 1,0 MOVS 1,1 56 MOVR 1,3 57 MOVR 1,1 35 58 COM 1,1 59 PTY 510 100 511 DOB 1,CCI 1 40 512 LDA 3,SADR 513 DOAP 3,CCI 1 514 MOVZL 0,0 515 MOVL 0,0 45 516 MOVL 0,0 517 LDA 1,RMSK 518 AND 0,1 519 MOVR 0,0 50 520 LDA 3,GRPT 521 ADD 1,3 522 LDA 1,0,3 523 DOA 1,CCI 1 524 DIA 1,CCI 155 525 PTY 526 200 527 BITSL: MOVZL 0,0,SZC 528 MOVS 1,1 60 529 MOVL 0,0,SZC 530 ADDL 1,1,SKP 531 MOV 0,0,SKP 532 ADDL 1,1 65 8 1,584,0048 TABLE I (continued) 533 MOVL 0,0,SZC 534 ADDL 1,1 535 MOVL 0,0,SZC 5 536 MOVL 1,1 537 SUBZR 3,3 538 MOVZL 1,1 539 AND 3,0,SNR 10 540 MOVC 0,0 541 MOVL 0,0 542 i MP 0,2 543 SADR: 120000 15 544 GRPT: + 1 545 000000 546 010000 547 130000 548 040000 20 549 LGAMK: 000777 550 RMSK: 000003 The processing of the above secondary program of instructions is described in connection 25 with bit 24 in the 1 H register 24 In a preferred embodiment, computer 501 is a Nova computer using standard Nova instructions A jump sub-routine (JSR) is employed to enter the program of TABLE I The computer jumps to address XLOGB as indicated in statement

SI of TABLE i In statement S 1, a return address in accumulator 3 is stored in accumulator 2.

Prior to statement 52, the 16-bit address of the 1 H register bit 24 has been stored in 30 accumulator 0.

In 52, accumulator 1 is loaded with the contents of a fixed address, "LGAMK", at 549 As indicated at 549 the value is 000777 in octal code.

In 53, the contents of accumulator 0 are logically AND'ed with the contents of accumulator 1 so that address Bits 7 through 15 are stored in accumulator 1 locations 7 through 15 35 In 54, address Bits 7 through 15 in accumulator I are subtracted from the Bit 0 through 15 contents of accumulator 0 so that Bits 0 through 6 are left in accumulator 0 in locations 0 through 6, Bits 7 through 15 of accumulator 0 are now equal to 0.

In 55, 56 and 57, Bits 7 through 15 in locations 7 through 15 of accumulator I are shifted to locations 0 through 8 of accumulator 1 40 In 58, the contents of accumulator 1 are complemented to put the information in the form needed when gated to the system by output data register (ODR) 575 of Fig 3.

In 59 and S 10, a system call prevents an interruption of the instruction stream until 525 and 526.

In Sll, address Bits 7 through 15 in locations O through 8 of accumulator 1 are transmitted 45 to the output data register (ODA) 575 in the interface controller 5 11.

In 512, accumulator 3 is loaded with the contents of a fixed address, "SADR", at 543 As indicated at 543, the SADR address contents are 1200000 in octal code.

In S 13, the contents of accumulator 3 are transmitted to the interface controller 511 and latched in the SAR 574 Decoder 567 is operative to decode the octal code 1200000 to 50 enable via line 621-6 the input gate 548 to the SADR register 556 Also in S 13, a signal is generated on line 549 which energizes the gates 548 which together with the signal on line 621-6 latches the nine bit address from the ODR register 575 into the SADR register 556 In 513, the secondary apparatus in response to the secondary program of TABLE I addresses the primary apparatus in accordance with the nine bit address in register 556 55 In 514, SI 5, and S 16, the address Bits 0 and 1 are moved in accumulator 0 from locations 0 and 1 to locations 14 and 15 This operation leaves Bits 2 through 6 in locations carry through 4.

In 517, accumulator I is loaded with the contents of a fixed address, "RMSK", at 550 As indicated at 550 the value is 000003 in octal code 60 In 518, the contents of accumulator 0 are logically AND'ed with accumulator I so that accumulator 1 because of the mask has address Bits 0 and 1 in locations 14 and 15.

In S 19, address bits 2 through 6 are moved from locations carry through 4 of accumulator 0 into locations 0 through 5 of accumulator 0.

In 520, accumulator 3 is loaded with the contents at the fixed address GRPT which is the 65 1,584,004 9 1,584,004 9 address of 544 plus one.

In 521, the contents of accumulator 1 Bits 0 and 1, which are binary 2 for bit 24 of the 1 H register, is added to the address in accumulator 3 to specify the addressed one of the four scan gates 561, 562, 563 or 564 in Fig 3.

In 522, accumulator 1 is loaded with the scan gate address from the contents of the location 5 whose address is in accumulator 3.

In 523, the scan gate address of accumulator 1 is input to the SAR register 574 and is -decoded by decoder 567 to select gate 563.

In 524, ingates 572 are enabled to latch the sixteen bits of scanout information from gates 563 into accumulator 1 In 524, the accessing of information from the primary apparatus is 10 completed The information accessed in 524 is the information which was addressed in 513.

In 525 and 526, the inhibit on interruptions established at 59 and 510 is removed.

In 527 through 538, using standard programming techniques, Address Bits 2 through 6 located in accumulator 0 are analyzed to determine which one of 16 bits of scanout information in accumulator 1 is the desired one corresponding to the state of bits 24 of the 1 H 15 register The program determines that it is the tenth bit In 538 that bit is moved into the carry locations.

In 539, Address Bit 6 is interrogated causing a branch to 540 if the scanout tenth bit must be complemented.

In 540, the complement is taken if necessary as determined in 539 20 In 541, the scanout tenth bit in the carry location is placed in location 15 of accumulator 0.

In 542, the program is terminated and the secondary date processing system returns to the return address specified in 51.

FURTHER AND OTHER EMBODIMENTS In Fig 11, an alternate embodiment is shown for decoding and selecting circuits with the 25 four bits utilized for on-chip addressing Specifically, the 9-bit bus 590 has the four on-chip bits 590-6, 590-7, 590-8 and 590-9 connected as an input to a 4-to-7 recoder 586 Recoder 586, in a preferred embodiment, recodes the four input bits 590-6 through 590-9 in accordance with the following TABLE II In TABLE II, the four address lines 5906 through 590-9 are identified in the column LINES 590- The recorded output appears in TABLE II as 30 LINES 597-.

TABLE II

LINES 590LINES 597OCTAL 6 7 8 9 0 O O O O 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 0 1 0 1 6 O 1 1 0 7 0 1 1 1 1 0 0 0 11 1 0 0 1 12 1 0 1 O 13 1 0 1 1 14 1 1 0 0 1 1 0 1 16 1 1 1 0 17 1 1 1 1 A B C D E F G 0 0 1 1 1 1 1 0 1 1 0 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 0 1 1 1 0 1 Still referring to Fig 11, the 7-bit bus 597 from the recorder 586 connects to the decoders 587-1,587-2 587-8 The decoders 587 each includes a plurality of three input gates 598.

Gate 598-0 receives two of the seven outputs on bus 597 and receives one input 473 which connects to some circuit in the data processing system of Fig 1 which is to have information scanned out when gate 598-0 is enabled by zero inputs on two of the lines 597 Gate 598-0 typically receives the inputs 597-A and 597-B from the seven lines 597 Those lines corres1,584,004 1,584,004 10 pond to an octal code of 0 and uniquely select the gate 598-0.

In a similar manner, the gate 598-1 has inputs 597-A and 597-D which represent octal 1 in TABLE II The outputs from the gates 598-0 through 598-7 have their outputs connected in common to the first gate 599-1 of eight column gates 599-1 through 599-8 The outputs from the decoders 587-2 through 587-8 are similarly connected to the column gates 599-2 through 5 599-8, respectively.

The eight column gates 599-1 through 599-8 are in turn connected in common to form the output line 612 '-1 which is analogous to the line 612-1 in Fig 8 Similarly, the four lines 612 '-1 through 612 '-4 are anologous to the four lines in the bus 612 of Fig 10.

Both the decoding schemes in Fig 9 and Fig 11 are used in a preferred embodiment of the 10 present invention Accordingly the present invention may be employed either to read out the state of latches or other storage elements within the data processing system, or may be employed to read out the state of specific lines which may dynamically change independent of the latching of data While the circuits scanned are predominantly latch circuits, it will be apparent to those skilled in the art that any circuit may have its state scanned out 15 The above description forms a part of the specification of United Kingdom Patent Application No 23185/75 (Serial No 1584003).

Claims (1)

1. WHAT WE CLAIM IS:

   1 A data processing system implemented employing integrated circuit chips each having a plurality of circuits in first data paths for storing information in accordance with data 20 manipulations carried out in accordance with first programs of instructions, the improvement comprising, scanout apparatus on each chip for addressing and accessing the states of said circuits independently of said first data paths and in accordance with second programs of instructions, and 25 a digital computer responsive to said second programs for addressing circuits on each of said chips and for receiving the data indicating the state of said addressed circuits.

   2 The data processing system of Claim 1 further including an interface controller responsive to the operation of said digital computer and including a console control interface connecting said interface controller with said chips of said data processing system 30 3 The data processing system of Claim 2 wherein said console control interface includes a scanout address data register for storing the addresses of said circuits to be accessed and providing the address and scanout data bus and includes a scanout data bus connecting to a plurality of said circuits in said data processing system for receiving the state of the circuit specified by said scanout data register 35 4 The data processing system of Claim 3 including a plurality of chip carriers wherein each chip carrier provides one line for said scanout data bus.

   The data processing system of Claim 4 wherein each chip carrier includes means for receiving said address bus for selecting one circuit to be gated to the associated scanout data line 40 6 The data processing system of Claim 5 wherein said address bus includes nine bits and wherein up to 64 scanout data lines.

   7 The data processing system of Claim 6 wherein each of said chip carriers includes up to 32 addressable chips organized in four rows of eight columns and wherein the chips in each row have their scanout outputs OR'ed in common 45 8 The data processing system of Claim 7 wherein said columns are addressed by the three high order bits of said 9-bit address bus and where the rows are addressed by the two next high order address bits.

   9 The data processing system of Claim 8 wherein each chip receives the four low order bits for specifying up to 16 addressable circuits per chip for connection to said scanout lines 50 AMDAHL CORPORATION Per: BOULT WADE & TENNANT 27, Furnival Street, London EC 4 A 1 PQ Chartered Patent Agents 55 Printed for Her Majesty's Stationery Office, by Croydon Printing Company Limited Croydon, Surrey, 1980.

   Published by The Patent Office 25 Southampton Buildings London, WC 2 A LA Yfrom which copies may be obtained.