CA1097820A - Data processing system and information scanout - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

Disclosed is a data processing system having a principal apparatus controlled by a principal program and including a main store, a storage unit, an instruction unit, an execution unit, a console unit and a channel unit. The console unit has a secondary apparatus controlled by a secondary program and including a digital computer for addressing and accessing infor-mation from locations throughout the principal apparatus of the data processing system independent of the principal program and independent of the information paths employed by the principal apparatus.

Description

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1 ¦ BACXGROUND OF THE INVENTION

2 I

3 ¦ The present,invention relates to the field of digital

4 1 computers and specifically to methods and apparatus whereby the

5 1 states of latch or other circuits within the data processing ¦ system are scanned out for the purpose of maintenance and error 7 1 analysis.
8 ¦ In high-speed, large-scale data processing systems, the 9 ¦ ability to detect the state of any latch or other circuit within 10 ¦ the data processing system is desirable particularly for analysis 11 ¦ and detecting of fault conditions. Prior art systems have 12 ¦ frequently direct-wired key pointC within the data processing 13 ¦ system to a control panel or console to illuminate the console 14 1 lamps to thereby give an indication of the status of storage i5 ¦ circuits within the system. The direct-wired approach however ~ ¦ becomes unwieldly for large data processing systems because the 17 ¦ number of illuminating lamps on the system console becomes too 18 ¦ large,for useful or convenient operator analysis.
19 1 Other prior art systems have employed the computing 20 ¦ capability of the data processing system to log out data using 21 ¦ the conventional data paths of the data processing system to 22 store the state of circuits within prescribed locations of 23 system storage. The use of the conventional data paths within 24 the storage system has the problem that if the data path or con-trol circuitry associated with that data path is faulty, the 26 informatiGn ~gged out is in error making fault location and 28 isolation difficult and time consuming.

8047/DEL -,r-1 In view of these problems attendant prior art data pro-2 cessing systems, a need exists for improved accessing of storage 3 circuits within the data processing system in order to facili-4 tate analysis of information for maintenance and other purposes.
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6 ~;UMMARY OF THE INVENTION

8 The present invention is a data processing system in-ciuding primary apparatus for carrying out principal instruction-controlled data manipulations and including secondary apparatus 11 for independently addressing and accessing storage locations 12 within the principal apparatus.
13 In a preferred embodiment of the invention, the secondary 14 apparatus includes an instruction-controlled digital computer which communicates with the remainder or principal apparatus of 16 the data processing system through a console control interface.
17 -The console control interface receives addresses of latch or 18 other circuits within the principal apparatus and addresses 19 those circuits through a scanout address bus connected in parall-el to a plurality of locations throughout the principal appara-21 tus. A group of circuits including the addressed circuit within 22 the system are accessed to transmit their states through the 23 console control interface via a scanout data bus. The informa-24 tion on the scanout data bus is stored back into the digital computer. The digital computer analyzes the returned information 26 to identify faults or to carry out other tasks.
27 In accordance with a further aetailed embodiment of the 229 present invention, the data processing system is constructed A28047/DEL _~

10"78Z0 1 with logic circuits on integrated circuit chips. The integrated 2 circuit chips, each containing a plurality of circuits, are fur-3 ther organized on a carrier called a multi-chip carrier (MCC).
4 Each MCC receives address bits from the scanout address bus and S provides a scanout line for returning information. The scanout 6 lines from all the MCC's together form the scanout data bus.

7 In accordance with the detailed embodiment, each MCC

8 is organized into and constructed from 32 logical chips where

9 the chips are arrayed into four rows of eight columns. The columns are addressed by the three high-order bits of the address 11 bus. Individual circuits on each chip are addressed by the 12 four low-order address bits. Many or all latch circuits and 13 other circuits are individually addressable, independent of 14 the operation of the principal apparatus and the principal pro-gram. In the detailed embodiment, each MCC is addressed in 16 parallel so that when addressed each MCC provides output inor-17 mation to the secondary apparatus. The secondary apparatus includes accessing means in the form of four sixteen bit scan 19 gates which are selected one at a time by two additional address bits. Further, the sixteen bits of information accessed by the 21 selected scan gate are further processed in response to four 22 additional address bits which specify a unique one of those 23 sixteen bits of information accessed.
24 Since the addressing and accessing is under control of a secondary program within the digital computer the sequence in 26 which circuits are addressed and accessed may be changed readily 27 thereby providing great flexibility in the manner in which in-28 formation is accessed for fault location or for any other purpose ~28~47/~EL

Thus, in accordance with a broad aspect of the invention, there is provi.ded a data processing system comprising: a principal apparatus for processing data, said principal apparatus formed by a plurality of principal circuits, interconnected and operable to process data, ea.ch of said pTincipal circuits energized to a logical state as part of the process-ing of data by said principal apparatus, a plurality of integrated circuit chips each containing a plurality of said principal circuits, a secondary apparatus for processing a secondary program of instructions independently from the processing of data by said principal apparatus, said secondary apparatus including addressing means connected in response to an address from said secondary program to address said pr:incipal circuits without disturbing said logical state of said principal circuits, said addressing means including an address bus connected to transmit said address in parallel to each of said chips and including chip address means and a scanout data line on each of sai.d chips, said chip address means on each chip including means responsive to said address on said address bus for addressing an ad-dressed one of said principal circuits on each chip and for gat:ing the logi-cal state of said addressed one of said principal c:ircuits on each chip onto said scanout data line on each chip, and said secondary apparatus including accessing means receiving the scanout data lines for each of said chips, said accessing means including means for selecting predetermined ones of said scanout data lines specified by said secondary program whereby the logi-cal state of principal circuits are accessed by said secondary apparatus.

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~ lQ"7820 1 In accordance with the above summary, the present inven-2 tion provides improved methods and apparatus for addressing and 3 accessing circuits within a data processing system.
4 Additional objects and features of the invention will appear from the following description in which the preferxed 6 embodiments of the invention have been set forth in detail in 7 conjunction with the drawings.
9 BRIEF DESCRIPTION OF T~E DRAWINGS
11 Fig. l depicts a block diagram of the overall data 12 processing system of the present invention.
13 Fig. 2 depicts a schematic representation of the consolc 14 unit of the system of ~ig. l.
Fig. 3 depicts a schematic representation of the inter-16 face controller and the console control interface within the 17 -console unit of Fig. 2.
18 Fig. 4 depicts a schematic representation of the manner 19 in which the data processing system of Fig. l is arrayed with multi-chip carriers (MCC) which are addressed and accessed by 21 the console control interface of Fig. 3.
22 Fig. 5 depicts a schematic representation of the physical 23 array of a typical MCC.
24 Fig. 6 depicts a schematic representation of the manner in which the chips on a typical MCC are logically arrayed.
26 Fig. 7 depicts a schematic representation of several 27 data paths within the execution unit of the Fig. l system.
28 Fig. 8 depicts a schematic representation of the chip 29 arrangement of the lH register which forms part of the data path in the apparatus of Fig. 7.

32 j 6 A28047/DEL -ir-~Q97~3Z~

Eigure 9 depicts a schematic representation of the chip associated with one bit in the Figure 8 circuitry.
Figure 10 depicts a schematic representation of the log chip associated with the MCC containing the circuitry of Figure 8.
Figure 11 depicts a schematic represent~tion of an alternate embodiment of the chip selection circuitry.
DETAILED DESCRIPTION
Overall System In Figure 1, the data processing system of the present invention is shown to include a main store 2l a storage control unit 4, an instruction unit 8, an execution unit 10, a channel unit 6 with associated I/O and a console unit 12. The system of Figure 1 operates under control of principal system instructions where an organized group of those instructions forms a system program. System instructions and the data upon which the instructions operate are introduced from the I/O equipment via the chanrlel unit 6 through the storage control unit 4 into the main store 2. Prom the main store 2, system instructions and data are fetched by the instruction unit 8 through the storage control 4 and are processed so as to control the execution within the execution unit lO. The system of Figure 1 is described in more detail in the above-referenced United States Patent 3,840,861 entitled DATA PROCESSING
SYSTEM which may be referred to for details of the overall general operation of an environmental instruction-controlled data processing system.

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Referring to Figure 4, the logic and other circuits comprising all or a major portion of the system of Figure 1 are implemented on multi-chip carriers (MCC) 602 where each carrier includes a plurality of integrated circuit chips as generally indicated in Figure 5. For example, up to 64 multi-chip carriers 602 indicated as MCC(0,0), ..., MCC~7,7). Each of those carriers typically includes up to 42 chips in a 6X7 rectangular array as indicated in Figure 5.
Console Unit In Figure 2, the console unit 12 of Figure 1 is shown in further detail. Console 1 includes a digital computer 501 which in interconnected with a 32K memory 502 in a conventional manner.
The digital computer 501 is connected to a plurality of controllers such as a disc controller 516, a channel controller 411, a panel controller 513 and an interface controller 511. Additional controllers may be connected to the indicated computer 501 in an analogous manner.
The disc controller 516 interfaces between the computer 501 and a 256 K disc file system 528. The channel controller 411 is one of the channel controllers associated with the channel unit 6 of Figure 1. The panel controller 513 interfaces between the digital computer 501 and the control panel 524. The interface controller 511 interfaces between the console control interface 525 and the digital computer 501.

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.~f 7~20 1 The computer 501 is typically a Nova 1200 computer 2 marketed by Data General Corporation. The details of operation 3 of such a computer and the manner in whieh eontrol units such 4 as the eontrollers 411, 511, 513 and 516 of Fig. 2 interfaee S with the eomputer 501 are described in the publication entitled, 6 "How to use the Nova Computers", DG NM-5, Data General Corpora-7 tion, April, 1971.
8 The interface controller 511, conneeted to the digital 9 eomputer S01 by the 48-bit bus 535 connects to the eonsole control interface by the bus 533. The console control inter-11 faee (CCI)525 is eonneeted via a seanout bus 436 to eireuits 12 throughout the data proeessing system of Fig. 1. The I-unit, 13 C-unit, S-unit intereonneetions from the eonsole eontrol inter-14 faee 525 are further described hereinafter.

16 Console Control Interfaee and Interface Controller 17 In Fig. 3, the eonsole control interfaee 525 and the 18 interfaee eontroller 511 and their intereonneetions are shown 19 in further detail. The eonsole eontrol interfaee (CCI)525 ineludes a 16-bit command register (CR)551 having a 16-bit 21 eommand bus output 540 whieh eonneets as an input to the I-unit 22 and C-unit as hereinafter deseribed. Interfaee 525 further 23 ineludes 16-bit addressing registers 552 and 553 whieh form 24 the 32-bit output address bus 542 whieh interconneets with address paths in the I-unit and S-unit of the data proeessing 26 system.
27 Interface 525 further includes 16-bit data registers 28 554 and 555 having outputs forming the 32-bit eonsole data bus 3~ 9 ~28047/DEL -~k~-~ Q ~ ~ 2~

1 543 which functions as a console data input to th~ data paths 2 ln the C-unit, S-unit and I-unit of the data processing system 3 o~ Fig. 1.
4 The console registers 551 through 556 and the gates 561 through 565 are addressed by the decoded outputs from the 6 decoder 567 which decodes and selects one of those eleven entities in response to the address in the 4-bit storage address 8 register 574 within the interface controller 511.
9 Interface 5~5 additionally includes a 9-bit scanout address register 556 which specifies, via 9-bit scanout address 11 bus 590, circuits within the data processing system which are 12 to be scanned out.
13 Interface 525 further includes the 64-bit scanout data 14 bus 591 which is connected to the 16-bit scanout gates 561 through 564. Also, a 16-bit gated state bus 592 connects to 16 the state yates 572 to the console computer 501 via selection 17 circuit 576 and bus 535. The decoder 567 receives the 4-bit 18 input from the storage address register 574 and decodes that 19 4-bit address to one of the eleven lines 621-1 through 621-11.
The select lines 621-7 through 621-11 are operative to select 21 the scan gates 561 t~rough 564 and the state gate 565, respec-22 tively. The gates 561 through 565 are each 16-bits and receive 23 the buses 634-1 through 634-4 which form the 64-bit scanout ~4 data bus 591. The gated state bus 592 derives state information from the I-unit in the data processing system of Fig. 1.
26 Interface 525 additionally includes the console inter-27 face control (CIC)570 which includes logic circuitry establish-28 ing outputs in response to inputs which are collectively identi-29 fied as lines 541. Specifically, the STA~T line functions to 32 /~
A28047/DEL ~_ lQ"78;:0 1 initiate clock signals in the I-unit for establishing timing2 signals throughout the system of Fig. 1. The S, I and C VALID
3 lines 545, one for each of the S, I and C units, respectively, 4 function to signal~-when one or more of the respective selected units is to be energized to receive commands from the console unit. When the respective S, I and C units have received a 7 VALID signal they signify receipt of that signal via the S, I
8 and C COMP lines 544, one for each of the units S, I and C, respectively. The I-unit acti~e state line 595 signals the STOP, PSW WAIT, CHECK STOP and METERING state conditions as 11 they occur in the system of Fig. 1. The OP END line senses 12 the timing pulses associated Wit-l the system of Fig. 1 and if 13 the delay between pulses exceeds a fixed duration an error 14 condition exists in the system of Fig. 1. The OP END line isinput to a hang detect circuit 581 which senses the time dura-16 tion between timing pulses and produces an output to signal 17 an undu2 delay.
18 The control 570, the hang detect circuit 581, and the 19 STOP line through the active state (AS) gates 582 indicate the state of the Fig. 1 system via the lines 584 connected to the 21 select circuits 576. Gates 583 sense the 8-bit interruption 22 mask register (IMR)579. The gates 582 and the register 579 23 have a one-for-one bit correlation which is for bits 0, 1, 24 7 the commands S COMP, C COMP, STOP, PSW WAIT, CHECK STOP, HANG
DETECTOR and METERING, respectively.
26 The interrupt Mask register 579 controls the settings 27 of the DONE line from gate 583. Since there is a one-for-one28 correspondence between the bits in the IMR 579 and the bits in ~280~7/DEL

lQ~7B2rl 1 the active state gates 582, the activization of a bit in the 2 active state gate sets the DONE line if the corresponding bit 3 in the register 579 is not set. If the bit in register 579 is 4 set, then the DONE line output from gate 583 is not set.
~ The ena~le register 578 stores three bits of information 6 which define which one or ones of the S, I and C VALID lines 7 545 are to be energized. Bit 0 signifies selection of the S-8 unit, bit l the selection of the I-unit and bit 2 the selection of the C-unit. The remaining decoded conditions of the 3 bits in the register 578 are "don't care" conditions.
11 The CIC 570 is responsive to an input START line which 12 also causes energization of the output START line. ~dditionally 13 the START CIC input line initiates operation of the control 1~ ci~cuitry 570. The input line CLEAR CIC functions to clear the CIC logic circuit 570 in anticipation of a new command for the 16 Fig. l system from the computer 50l.

18 M lti-chip Structure Referring now to Fig. 4, the scanout address bus 590 21 from the scanout data register 556 of Fig. 3 connects in parall-22 el to a plurality of MCC's 602 for addressing a particular chip 23 on each MCC and for further addressing a particular latch on 24 the address chip for each MCC. The state of the addressed latch appears as an output on the respec~ive one of the scanout lines 26 603. For example, the addressed latch on MCC(0,0) has its out-27 put on scanout line 603(0,0). In a similar manner, each of the 28 64 MCC's of Fig. 4 has a corresponding output line 603 producing ~¢?97~32/~

1 therefore, the 64-bit bus 591. Bus 591 is the scanout data bus 2 591 which connects as an input to the scan gates 561 through 3 564 in Fig. 3.
4 Referring now to Fig. 5, a typical MCC 602 is shown S comprised of 42 chips 606. The chips are arrayed, for conven-6 ience, in seven rows numbered 1 through 7 and in six columns 7 lettered A through F. Each of the logic chips 606 includes a 8 plurality of circuits for implementing the logical and storage functions carried on in the system of Fig. 1. Further, at least one of the chips, for example, chip lF in Fic3. 5 is a scanout 11 or log ship which receives the 9-bit scanout address bus 590 12 and provides the l-bit scanout line 603 which, together with 13 the other one-line scanouts from the other MCC's, forms the 14 scanout data bus. While the location lF has been selected for the log chip in Fig. 5 any one of the chip locations may in 16 fact contain the log chip since the physical location in the 17 array is not critical. In Fig. 5, each MCC is typically shown i8 including up to 42 chips where each chip has a unique physical 19 location on its chip carriers.
In Fig. 6, the physical MCC of Fig. 5 is redefined in 21 terms of its logical accessibility by the scanout apparatus of 22 the present invention. The logical MCC of Fig. 6 is defined 23 to include 32 addressable logical chips where each logical chip 24 608 in Fig. 6 includes at least one physical chip 606 of Fig. 5.
Because there are only 32 addressable chips in Fig. 6, each 26 logical chip 608 may include a non-addressable physical chip 27 606 or some portion of a physical chip 606 for convenience.
28 The log chip 611 in Fig. 6 corresponds to the chip lF in Fig. 5.

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The logical chips C~0,0), C~0,1), ..., C(0,7) of Figure 6 are organized in a first one of four rows. The chips 608 in Figure 6 may correspond to any combination of chips 606 in Figure 5. The log chip 611 in Figure 6 receives as an input the 9-bit scanout address bus 590 and provides one bit on output line 603 of the scanout data bus 591 of Figure 3 and Figure 4. Additionally, the log chip 611 provides eight output column select lines 614-1 through 614-8 and four chip select lines 613. The log chip 611 further receives the 4-bit bus 612 which is comprised of four row scan lines 6~2-1 through 612-4. Each row line 612-1 through 612-4 receives the scanout data from a row of eight logical chips 608 all OR'ed together to form a common line.
The log chip 611 in Figure 6 operates to receive the 9-bit address on bus 590. The three high order bits of that 9-bit bus 590 are decoded to select one of the eight lines 614.
The selected one of the lines 614, for examplel line 614-1, selects the corresponding column, for example, colwnn C~OJO)~
C(l,0), C(2,0) and C(3,0). The four low order bits of the 9-bit address on line 590 are transmitted via bus 613 to each of the chips 608 for selecting one of up to 64 circuits on each chip 608.
The state of the selected circuit on each chip is then gated out to the corresponding row line 612-1 through 612-4. The remaining two (middle) address bits on the bus 590 are employed in the log chip 611 to select one of the four row scanout lines 612 for transmission as the output on scanout bus line 603. Further details of the scanout arrangement are now described in connection with a typical example. The example described is the 1ll register in the execution unit lO of the system of Figure l as shown in Figure 7.

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In Figure 7, the lH register 24 is shown between the LUCK unit 20 and the byte adder 32 all of which form part of the execution unit 10 of the system of Figure 1. Further details of the lH register and its operation in the execution unit of the system of Figure 1 are described in the above-referenced United States Patents 3,840,861, 3,792,362 and 3,814,925.
In general, the lH register 24 is a 32-bit register which receives input data from the LUCK unit 20 and connects its output, among other places, to the byte adder 32. Information is latched into register 24 by a clock pulse on line 631 from a clock 102. The details of the clock operation Eor latching data into the register 24 are described in the above-referenced United States 3,792,362. In that patent, a typical bit, identified as bit location 124, is described as including a latch circuit. The latch circuit 124 of register 24 in Figure 7 is shown in further detail in connection with Figures 8 and 9.
In Figure 8, bit 124, representing bit position 24 of the 32 bits, 0 through 31, is located on chip 606-1. In addition to bit 24 of register 24 in Figure 7, bits 25 through 31 are also shown as being located on chips 606-2, 606-3, ... , 606-8 which are designated as BIT 25, BIT 26, ..., BIT 31, respectively. Bit 24, designated 606-1, is one of the chips 606 like that previously described in connection with Figure 5. Similarly, each I ( lQ~7~20 ~ ~ I

1 ¦ of the other chips 606-2 through 606-8 are also typically identi-2 ¦ cal to the chips 606 in Fig. 5. The eight chips 606-1 through 3 ¦ 606-8 form a part of the eight chips which form a row, such as 4 ¦ row 0 in Fig. 6 which have a common OR'ed output 612-1.
In addition to the chips 606-1 through 606-8, the 6 logical chips of Fig. 6 within a row include further logic not on the same physical chips. For example, one logical chip C(0,0) 8 includes physical chip 606-1 and logic gate 623-1. Similarly, 9 the logic~l chip of Fig. 6 C(0,1) includes the physical chip

10 606-2 o Fig. 8 and the column select gate 623-2. The column .

11 select gates 623-1 and 623-2, in a preferred embodiment, are on

12 different physical chips. In a similar manner, chips 606-3,

13 606-4 and 606-5 of Fig. 8 are three different physical chips

14 and each are associated with the column select gates 623-3, 623-4 and 623-5, respectively. The column select gate 623-3 16 through 623-~ are, in a preferred embodiment, on a single physi-17 cal chip. Similarly, chips 606-6, 606-7 and 606-8 are each 18 three different physical chips while the corresponding select 19 gates 623-6, 623-7 and 623-8 are located on a different physical chip. In the manner described, the circuitry 617-1, arrayed on 21 physical chips as indicated, forms one row of C(0,0) through 22 C(0,7) of logical chips 608.
23 In the same manner that the circuitry 617-1 represents 24 one row of eight logical chips for an MCC of the 601 type, 25 ¦ similar additional circuitry 617-2, 617-3 and 617-4 represents 26 I rows of logical chips which each p~ovide an output line 612-2, 27 ¦ 612-3 and 612-4, respectively. The four lines 612-1 through 28 l 612-4 form the 4-bi~ bus 612. Each of the row circuits 617-1 29 ¦ through 617-4 receive the eight column select lines 614 and the 30 ~ four chip address lines 613 derived from the LOG CHIP 611 of Fig.
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Single Chip Structure Further details of the BIT 24 chip 606-1, which represents bit 24 in the lH register 24 of Figure 7, are shown in Figure 9.
In Figure 9, chip 606-1 includes latch circuit 124-1 which is bit 24 of the bits 0 through 31 of the lH register 24 in Figure7.
I,atch 124-1 receives its input from LUCK unit 20 via the lines 652, one of which is a data line and the other of which is a control line. Similarly, latch 124-1 receives inputs from the shifter via lines 653, one of which is a control line and one of which is a data line and from the adder via lines 654, one of which is a data line and one of which is a control line. Also, latch 124-1 has a synchronous reset input via line 651 for resetting the latch at appropriate times in the operation of the data processing system.
Additionally, latch 124-1 receives inputs on lines 631 and 632 for controlling the clocking of the latch. I.ine 631 is an input from the clock 102 while line 632 is an inhibit control to prevent clocking of the latch 124-1. Latch 124-1 has an output on line 656 which connects to a phase splitter 637 which is the first level, I, of logic associated with the byte addcr as described in the above-identified lJnited States Patent 3,814,925. In addition to connecting to the phase splitter 637 which constitutes the normal data path of the system of Figure 1, latch 124-1 has an output to an additional phase splitter 638 which constitutes the beginning of the scanout data paths of the system of Figure 1.
In addition to latch 124-1, the chip 606-1, in a pre-ferred embodiment of the present invention, includes a latch l~Q78Z~) 1 124-2 which is associated with BIT 24 in the 2H register 25 of 2 the Fig. 7 circuitry. Similarly, the chip 606-1 includes latch 3 circuit 12~-3 and 124-4 corresponding to ~its 24 of the lL
4 register and the 2L register which are additional registers associated with the execution unit 10 but which are not otherwise 6 specifically shown in the present specification. The output from 7 latch 124-2 on line 657 similarly connects to the phase splitter 637 and to the phase splitter 638 as do the outputs from the 9 latches 124-3 and 124-4.
The phase splitter 638 includes a gate 639 which trans-11 mits the state of latch 124-1 as indicated on line 656 to the 12 selection gate 641. Selection gate 641 is one of four ga~es 13 in the selector circuit 640 for appropriately selecting which 14 ¦ one of the four latches 124-1 through 124-4 is to be connected with an output on line 643. The selection of which of the gates 16 in the selector 641 is under control of the ~ecoder 642 which 17 includes two bi-polar gates 645 and 646 responsive to two bits i8 on lines 613-1 and 613-2 of the 4-bit bus 613. The two bits on 19 lines 613-1 and 613-2 are decoded to uniquely select one of the four gates in the selector circuit 640. When the +LA and ~LB
21 lines from gates 645 and 646 are energized, the gate 641 is 22 selected providing the output of line 643 as an input to gate 23 644 which provides the outputs on line 619. Referring again to 24 Fig. 8, the output on line 619 is the selected chip BIT 24 out-put. In the circuitry 606-1 of Fig. 9, only two of the four 26 chip address iines of bus 613 are employed, namely lines 613-1, 27 613-2. The two binary addresses specified by those two lines 28 uniquely define one of the four latches 124-1 through 12~-4.
29 Additional lines 613-3 and 613~4 may be employed so that a total ~280~7/DEL ¦ /~
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1 of up to 16 latch or other type circuits per chip may be employed 2 in accordance with a preferred embodiment of the present inven-3 tion. The output on line 619, in accordance with Fig. 9 repre-4 sents one or four latches on the chip 606-1. When more latches S are employed, up to 16, the line 619 output would represent one 6 out of sixteen latch states as addressed by the address occurring 7 on bus 613.

Log Chip Structure 11 In Fig. 10, further details of the log chip 611 of Fig.
12 8 are shown. Log chip 611 receives the nine input address bits 13 on input bus 590. The three high order bits on lines 590-1, 14 590-2 and 590-3 are input to the column select decoding circuitry lS 626 where, in a conventional manner, they are decoded to select 16 eight output lines 614. The eight lines 614-1 through 614-8 from bus 614 which is connected as the inputs to each of the row l8 select circuits 617-1 through 617-4 of Fig. 8. In Fig. 8, those 19 column select lines are operative to select one at a time, in accordance with the three input address bits, the gates 623-1 21 through 623-8, respectively.
22 The next two high-ordered bits of address bus 590 appear 23 on lines 590-4 and 590-5 where they serve as inputs to the row 24 decode and select circuitry 627. In circuitry 627, the two bits 25 on lines 590-4 and 590-5 are decoded to select one of the four 26 gates 661-1 through 661-4 which receives the row state lines 27 612-1 through 612-4, respectivelyj on the bus 612 from the MCC
28 of Fig. 8. The selected one of the four lines 612 in response 29 to the coded information in the input bits 590-4 and 590-5 appears as an output on line 603 which is one of the 16 bits in 31 the bus 634-1 which is one of the 64 bits in the 64-bit bus 591 32 which is shown in Fig. 4.
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Similarly, the four low order bits on lines 590-6 through 590-9 are powered in the power drive circuit 628 and retransmitted via bus 613 to each of the chi.ps on the MCC 601 of Figure 6 and particularly to the row chips 617-1 of Figure 8. The signals on the lines 590-6 through 590-9 appear as the identical signals on the lines 613-1 through 613-4, respectively.
OPERATION
Principal and Secondary Apparatus The principal apparatus of Figure 1, under control of principal instructions processed by the instruction unit 8, fetches informati.on from the storage control 4 and the main store 2. Execution unit 10 executes principal instructions under control of information from the instruction unit 8. By way of example, some principal instructions in the principal apparatus employ an adder in execution unit 10 which is shown in more detail in Figure 7. In executing a principal instruction, information is input to the adder 32 of Figure 7 through the LUCK unit 20 where it is stored in the 1ll register 24 and the 211 register 25. Information latched in the registers 24 and 25 is added by the adder 32 to form results which appear in the register 38. The operation of the Figure 1 principal apparatus in executing principal instructions is described in the above-referenced United States Patents 3,840,861 and 3,792,362.

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1 ¦ The latching of data into the register 24 occurs 2 il specifically at a time controlled by the clock signal on line 631 3 1I which line operates, as shown in Fig. 9, to set each of the bit 4 jl positions, 0 through 32, of register 24 and specifically bit 24 5 i of the lH register designated as 124-1. The setting of the latch 6 124-1 and the other bit positions in register 24 are generally 7 under control of the principal apparatus in carrying out the 8 instructions of a princip21 instruction stream.

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1 The console computer 501 o~ Fig. 2 is operative 2 to access information from address locations in the principal 3 apparatus of Fig. 1 in accordance with a program of secondary 4 ¦ instructions. The operation of the secondary apparatus and S ¦ the program of secondary instructions in computer 501 is 6 ¦ independent of the operation of the principal apparatus in ¦ executing the principal instructions.
8 ¦ In a preferred embodiment, address locations within 9 ¦ the principal apparatus of Fig. 1 are specified in accordance 10 ¦ with a 16-bit binary address generated by computer 501. That 11 ¦ address has the follo-~ing significance.
12 ¦ Bits 0 and 1 specify one of four groups of 16 MCC's 13 ¦ and particularly their output lines 603. Bits 0 and 1 are 14 ¦ decoded to select one of the four scan gates 561 through 564 l5 ¦ in Fig. 3 thereby selecting one of four groups of 16 lines.
16 Bits 2 through 5 specify one out of the 16 in-17 formation bits appearing on that one group o 16 lines selec-ted l8 by Bits 0 and 1.
l9 Bit 6 specifies ~hether or not the selected infor-mation bit from the 64 MCC's of Fig. 4 must be inverted or 21 not in order to have correct polarity. Bit 6 is useful in 22 a preferred embodiment of the present invention since a 23 preferred technology employs inverting logic. In inverting 24 logic, the existence of an odd number or an even number of logic levels in transmitting information to the scan gates 26 determines ~hether the information has correct or inverted 27 ¦¦ polarity. By using Bit 6 in the present addressing format, 28 1l addressed information may be arbitrarily returned to the 29~j scan gates without the need for requiring that either an odd 30 ~
~ 31 A-28047/DE~

~-- , . _ . .

1~7!~1Z~) l number or an even number of logic levels be employed. By 2 appropriately setting sit 6 the correct polarity is established 3 for each information bit accessed.
4 Bits 7 through 9 select one of eight columns of chips 608 in Fig. 6. Bits 7 through 9 are three of the nine 6 address bits output on scanout address bus 590 of Fig. 3.
7 Bits 10 and 11 select one of four rows of chips 608 8 in Fig, 6. Bits 10 and 11 are two of the nine address bits 9 on scanout address bus 590.
IO Bits 12 through 15 are four bits which select one .
l of up to 16 circuits on each of the chips 608 in Fig. 6.
12 Bits 12 through 15 are the four remaining bits of the nine 13 address bits on bus 590 of Fig. 3.
14 Addressing of lH Register Bit 24 While any circuit location within the principal 16 apparatus can be made addressable or accessing by the 17 console computer 501, a particular example selected for 18 explanation is the lH register 24 and specifically the l9 bit 24 location therein as shown in Fig. 7.
Bit 24 of the lH register 24 has the following 21 16-bit binary address:

~3 0 1 2 3 4 5 6 7 8 9 10 11 12~,.13 14 15 24 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 o 26¦ In the binary address of bit 24, Bits 0 and 1 re-271 present a binary 3 which signifies that the SC~N 2 gate 563 28~ will be the gate energized. Gate 563 receives the addressed 29¦ information from the principal apparatus and specifically the 32 ~
~-28047/DEL ,l ~3 11~7~32~

1 16 lines 603 from the MCC's MCC(0,4), MCC(1,4),..., MCC(7,4 2 and MCC(0,5), MCC(1,5),..., MCC(7,5).
3 Bits 2 through 5 of the bit 24 address represent 4 a binary 10 which means that the desired information bit will appear on the tenth MCC, MCC(1,5), in the group of MCC's 6 specified by Bits ~ and 1.
7 The 0 in Bit 6 of the above binary address indicates 8 that no inversion is required in the information returned for 9 bit 24 of the lH register.
The all O's for the colun~ select Bits 7 through 9 11 and for the row select Bits 10 and 11 signify that bit 24 12 of the lH register is on the chip located in the 0 column 13 and the 0 row of chips. Specifically, referring to Fig. 6, 14 the 0 column and 0 row is chip C(0,0).
Referring to Fig. 10 Bits 7, 8 and 9 are input on 16 lines 590-1, 590-2 and 590-3 to select the 0 column output 17 line 614-1 of the eight lines 614. That line 614-1 in 18 Fig. 8 is operative to select the 0 gate 623~1 which receives l9 as its other input, the output on line 619 from the bit 24 location 606-1 in the 0 column of the 0 row 617-1. Simultan-21 eously, the rows 617-2, 617-3 and 617-4 also select a 0 22 column output on their lines 612-2, 612-3 and 612-4.
23 In Fig. 10, Bits 10 and 11 for row select are input 24 on lines 590-4 and 590-5 and are decoded to select the gate 661-1 which thereby functions to select from the four row 26 lines 612 the 0 row line 612-1 which is derived from Fig. 8.
27 In Fig. 10, Bits 12, 13 and 14 and 15 are input on 28 I the lines 590-6 through 590-9 which appear on the output bus 613 29 I which in turn is input to the chips of Fig. 6 including 30 1l ~-2~047/DEL ! ~ ~

-~ 7~X~

Ichip C(0,0) which is chip 606-1 in Figs. 8 and 9. In Fig. 9, 2 two of those four bits are actually employed in a preferred 3 ¦ embodiment, specifically the two bits on lines 613-1 and 613-2.
41 Since Bits 12 through 15 are O's, they enable the gates 645 5 ¦ and 646 with +LA and +LB in the 0 state. The 0 state of those 6 ¦ two outputs are connected as inputs in the decoder 640 and 7 ¦ operate to enable gate 641 with O's on inputs +LA and +LB.
8 ¦ With gate 641 thus enabled, the output of gate 641 is controlled 9 ¦ by the state of line 656' from gate 639. Gate 639 connects lO ¦ from the inverting output of latch 124-1 on line 656. The 11 ¦ inverted output on line 656 is, of course, the inverse of the 12 ¦ addressed bit 24 of the lH regi~er.
13 ¦The output on line 65~ is inverted in gate 639, in 1~ ¦ gate 641, in gate 644, in gate 623-1 in Fig. 8, and in gate I 661-1 in Fig. 10 providing the addressed one of the 64 inputs 16 ¦ on line 603 to the 64-bit bus 591. The number of inversions 17 ¦ from line 656 to line 603 of Fig. 6 is five which when coupled 18 ¦ with the inverted output itself on line 656 presents the 19 ¦ correct polarity to the scan gate 563 of Fig. 3.
20 I Console Computer Program of Instructions I _ , 21 ¦ The console computer 501 of Fig. 2 operates through 22 ¦ the interface control 511 and the console control interface 525 23 ¦ to carry out the required addressing and accessing of informa-24 ¦ tion in the principal apparatus of Fig. 1 in accordance with 25 I a secondary program of instructions as given by the following 26 j TABLE I:

29~'1 30 i -280~47/DEL 'i~-~s Ii ~- ,, ' ~ 1~7~32~

I TABLE
2 Sl XLOGB: STA 3,2 3 S2 NORM: LDA l,LGAMK
4~ S3 AND 0,1 5 ¦ S4 SUB 1,0 6 ¦ S5 MOVS 1,1 7 ¦ S6 MOVR 1,3 8 ¦ S7 MOVR 1,1 9 ¦ S8 COM 1,1 IO ¦ S9 .PTY
11 I SlO 100 12 ¦ Sll DOB l,CCIl 13 ¦ S12 LDA 3,SADR
14 ¦ S13 DOAP 3,CCIl

15 ¦ S14 ~ MOVZL 0,0

16 ¦ S15 MOVL 010

17 ¦ S16 MOVL 0~0

18 ¦ S17 LDA l,RMiSK
l9 ¦ S18 AND 0,1 Sl9 MOVR 0~0 21 S20 LDA 3,GRPT
22 S21 ADD 1,3 23 S22 LDA 1,0,3 24 S23 DOA l,CCIl S24 DIA l,CCIl 226 ~ 525 .PTY

28 , h 30 j 31.
32 i ~`'' `l ~-28047/DEL 1 æG

1~7~Z~ I

2 S27 BITSL: MOVZL 0~0,SZC
3 S28 MOVS 1,1 4 ¦ S29 MOVL 0,0,SZC
S ¦ S30 ADDL l,l,SKP
6 ¦ S31 MOV 0,0,SKP
¦ S32 ADDL 1,1 8 ¦ S33 MOVL 0~0,SZC
9 ¦ S.34 ADDL 1,1 10 ¦ S35 MOVL 0,0,SZC , 11 ¦ S36 MOVL 1,1 12 ¦ S37 SUBZR 3,3 13 ¦ S38 MOVZL 1,1 14 ¦ S39 AND 3,0,SNR
15 ¦ S40 MOVC 0,0 16 ¦ S41 MOVL 0,0 17 ¦ S42 JMP 0,2 18 ¦ S43 SADR: 120000

19 S44 GRPT: .+1 ~3 S48 040000 24 S49 LGAMK: 000777 S50 RMSK: 000003 ,226 -21~47/DEL

1(;~7~

1 The processing of the above secondary program of 2 instructions is described in connection with bit 24 in the 3 lH register 24. In a preferred e~bodiment, computer 501 is 4¦ a Nova computer using standard ~ova instructions. A jump sub-routine (JSR) is employed to enter the program of T~BLE I.
6 The computer jumps to address XLOGB as indicated in statement 7 Sl of TABLE i. In statement Sl, a return address in accumu-8 lator 3 is stored in accumulator 2.
9 Prior to statement S2, the 16-bit address of the 10 ¦ lH register bit 24 has been stored in accumulator 0. , 11 ¦ In S2, accumulator 1 is loaded with the contents 12 ¦ of a fi~ed address, "LGAMK", at S49. As indicated at S49 13 the value is 000777 in octal code.
~ In S3, the contents of accumulator 0 are logically AND~ed with the contents of accumulator 1 so that address 16 Bits 7 through 15 are stored in accumulator 1 locations 7 17 through 15.
18 In S4, address Bits 7 through 15 in accumulator 1 19 are subtracted from the Bit 0 through 15 contents of accumulator 0 so that Bits 0 through 6 are left in accumulator 0 in loca-21 tions 0 through 6, Bits 7 through 15 of accumulator 0 are 22 now equal to 0.
23 In S5, S6 and S7, Bits 7 through 15 in locations 7 24 through 15 of accumulator 1 are shifted to locations 0 through 8 of accumulator 1.
26 In S8, the contents of accumulator 1 are complemented 27 to put the information in the form needed when gated to the 28 system by output data register(ODR) 575 of Fig. 3.
29 In S9 and S10, a system call pxevents an interruption ~-2 ~ 7/DEL

lQ'17t~ZO

I of the instruction stream until S25 and S26.
2 In Sll, address sits 7 through 15 in locations 0 3 through 8 of accumulator 1 are transmitted to the output data ¦ register (ODA) 575 in the interface controller 511.
. 5 In S12, accumulator 3 is loaded with the contents 6 of a fixed address, "SADR", at S43. As indicated at S43, 7 the SADR address contents are 1200000 in octal code.
8 In S13, the contents of accumulator 3 are transmitted 9 to the interface controller 511 and latched in the SAR 574. , Decoder 567 is operative to decode the octal code 1200000 to Il enable via line 621-6 the input gate 548 to the SADR register 12 556, Also in S13, a signal is generated on line 549 which 13 energizes the gates 548 which together with the signal on 14 . line 621-6 latches the nine bit address from the ODR register 575 into the SADR register 556. In S13, the secondary apparatus 16 in response to the secondary program o TABLE I addresses the 17 primary apparatus in accordance with the nine bit address in 18 register 556.
19 In S14, S15, and S16, the address Bits 0 and 1 are moved in accumulator 0 from locations 0 and 1 to locations 14 21 and 15. This operation leaves Bits 2 through 6 in locations 22 carry through 4.
23 In S17, accumulator 1 is ioaded with the contents 24 of a fixed address, "RMSK", at S50. As indicated at S50 the value is 000003 in octal code.
j 26 In S18, the contents of accumulator 0 are logically 27 ANDIed ~,lith accumulator 1 so that accumulator 1 because of 28 the mask has address Bits 0 and 1 in locations 14 and 15.
291 In Sl9, address bits 2 through 6 are moved from 30 ~ .

~ ., 32 -280~7/DEL
., l ( ~
-~ :

:10978;~0 1 locations carry through 4 af accumulator 0 into locations 0 2 through 5 of accumulator 0.
3 In S20, accumulator 3 is loaded with the contents ¦ at the fixed address G~PT which is the address of S44 plus one.
5 ¦ In S21, the contents of accumulator l Bits 0 and l, 6 ¦ which are binary 2 for bit 24 of the lH register, is added 7 ¦ to the address in accumulator 3 to specify the addressed 8 ¦ one of the four scan gates 561, 562, 563 or 564 in Fig. 3.
¦ In S22, accumulator l is loaded with the scan 10 j gate address from the contents of the location whose address , 11 ¦ is in accumulator 3.
12 ¦ In S23, the scan gate ~ddress of accumulator l is 13 ¦ input to the SAR register 574 and is decoded by decoder 567 4 ¦ to select gate 563.
15 ¦ In S24, ingates 572 are enabled to latch the sixteen ¦ bits of scanout information from gates 563 into accumulator l.
17 In S24, the accessing of information from the primary apparatus 18 is completed. The information accessed in S24 is the informa-tion which was addressed in Sl3.
In S25 and S26, the inhibit on interruptions estab-21 lished at S9 and SlO is removed.
22 In S27 through S38, using standard programming 23 techniques, Address Bits 2 through 6 located in accumulator 0 24 are analyzed to determine which one of 16 bits of scanout information in accumulator l is the desired one corresponding 26 to the state of bits 24 of the lH register. The program 27 ~ determines that it is the tenth bit. In S38 that bit is moved 28 j into the carry locations.
! In S39, Address Bit 6 is interrogated causing a 30jl 31 1j , ~ 32 11 ~-28047/DEL jl ~3~

~Oq78ZO

1 branch to S40 if the scanout tenth bit must be complemented.
2 In S40, the complement is taken if necessary as 3 determined in S39.
4 In S41, the scanout tenth bit in the carry location is placed in location 15 of accumulator 0.
6 In S42, the program is terminated and the secondary date processing system returns to the return address specified in Sl.

21 ~

- 29 1 .

301 .

~-28047/DEL _~z_ 109782~

1 FURTHER AND OTI~ER EMBODIMENTS
2 In Fig. 11, an alternate embodiment is shown for 3 decoding and selecting circuits with the four bits utilized 4 for on-chip addressing. Specifically, the 9-bit bus 590 has the four on-chip bits 590-6, 590-7, 590-8 and 590~9 connected 6 as an input to a 4-to-7 recoder 586. Recoder 586, in a preferrec .
7 embodiment, recodes the four input bits 590-6 through 590-9 8 in accordance with the follo~7ing TABLE II. In TABLE II, the 9 four address lines 590-6 through 590-9 are identified in the column LINES 590-. The recoded output appears in TABLE II
4 as LINES 597-, ' ' 2811 ~-28047/DEL I 3.

~ _ ., .

~ '7~32`~) TABLE I I

4 OCTAL 6_ 7 8 9 A B C D E F G
0 0 0 0 0 0 0 l 1 l l l 6 l . 0 0 0 1 0 l l 0 l 1 l 7 2 0 0 l 0 l 0 0 l l l 1 8 3 0 0 l 1 l 1 0 0 l l l 9 1 4 0 l 0 0 0 l 0 1 l l 0 l 0 1 0 l l 1 1 0 l 11 16 0 l l 0 1 l 0 l 0 l2 7 0 l l l l l 0 l l 0 l 13 10 l 0 0 0 l 0 l l 0 l l 14 11 1 0 0 1 1 l l 0 0 1 l lS 12 l 0 l 0 ' l 0 l 0 16 13 l 0 l l l l l 0 l 0 14 l 1 0 0 0 l 1 l 0 1 1 l8 15 l l 0 l 1 l l l 0 0 1 19 16 1 l 1 0 1 0 l l l l 0 22o 17 l 1 l l l 0 1 l l 0 l 30 ii ,. ;

lQ~7~12~

Still referring to Figure 11, the 7-bit bus 597 from the recoder 586 connects to the decoders 587-1, 587-2, ..., 587-8.
The decoders 587 each includes a plurality of three input gates 598. Gate 598-0 receives two of the seven outputs on bus 597 and receives one input 473 which connects to some circuit in the data processing system of Figure 1 which is to have information scanned out when gate 598-0 is enabled by zero inputs on two of the lines 597. Gate 598-0 typically receives the inputs 597-A
and 597-B from the seven lines 597. Those lines correspond to an octal code of 0 and uniquely select the gate 598-0.
In a similar manner, the gate 598-1 has inputs 597-A
and 597-D which represent octal 1 in TABLE II. The outputs from the gates 598-0 through 598-7 have their outputs connected in common to the first gate 599-1 of eight column gates 599-1 through 599-8. The outputs from the decoders 587-2 through 587-8 are ; similarly connected to the column gates 599-2 through 599-8, respectively.
; The eight column gates 599-1 through 599-8 are in turn connected in common to form the output line 612'-1 which is analogous to the line 612-1 in Figure 8. Similarly, the four lines 612'-1 through 612'-4 are analogous to the four lines in the bus 612 of Figure 10.
Both the decoding schemes in Figure 9 and Figure 11 are used in a preferred embodiment of the present invention. In a preferred embodiment, the typical circuit connec~ed to line 473 is derived from the console unit.

:~`
~ - 34 -~ , .

~Q~7~

The line 473 detects the active state of the circuit in the above-referenced application, where that circuit is not a latch circuit.
The bit 24 of the 111 register as discussed in Figure 9 is, by way of comparison a la~ch circuit. Accordingly, the present invention may be employed either to read out the state of latches or other storage elements within the data processing system, or may be employed to read out the state of specific lines which may dynamically change independent of the latching of data. While the circuits scanned are predominantly latch circuits, it will be apparent to those skilled in the art that any circuit may have its state scanned out.

~'~

.

Claims (4)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A data processing system comprising: a principal apparatus for processing data, said principal apparatus formed by a plurality of principal circuits, interconnected and operable to process data, each of said principal circuits energized to a logical state as part of the processing of data by said principal apparatus, a plurality of integrated circuit chips each contain-ing a plurality of said principal circuits, a secondary apparatus for processing a secondary program of instructions independently from the processing of data by said principal apparatus, said secondary apparatus including addressing means connected in re-sponse to an address from said secondary program to address said principal circuits without disturbing said logical state of said principal circuits, said addressing means including an address bus connected to transmit said address in parallel to each of said chips and including chip address means and a scanout data line on each of said chips, said chip address means on each chip including means responsive to said address on said address bus for addressing an addressed one of said principal circuits on each chip and for gating the logical state of said addressed one of said principal circuits on each chip onto said scanout data line on each chip, and said secondary apparatus including access-ing means receiving the scanout data lines for each of said chips, said accessing means including means for selecting pre-determined ones of said scanout data lines specified by said secondary program whereby the logical state of principal circuits are accessed by said secondary apparatus.

2. The system of Claim I wherein said secondary apparatus includes, a programmable digital computer for communicating with devices through a plurality of controllers in response to said secondary program, an interface controller for communicating with said digital com-puter, said interface controller including an output data register for gating out said address from said secondary program and including a scanout address register for receiving said address, and control interface means connected between said interface controller and said principal apparatus, said control interface means including said addressing means and said accessing means each connected to be enabled by the address from said scanout address register in response to said secondary program for addressing and accessing said principal circuits.

3. The system of Claim 2 wherein said scanout address register has an output forming a scanout address bus connected in parallel to a plurality of said principal circuits, and said system further including scan gates connected serially to said scanout data lines including means responsive to said address generated by said secondary program for enabling said scanout address register and said scan gates whereby information is addressed and accessed in said principal apparatus.

4. The data processing system of Claim 1 further including, a plurality of chip carriers each containing a plurality of said chips and each connected to receive said address bus and to provide an input to a scanout data bus from selected predetermined ones of said scanout data lines, means associated with each chip carrier for addressing one of the plurality of said chips contained on said chip carrier in response to said address on said address bus.