DE2725504C2 - - Google Patents

Description

The invention relates to a data processing system the described in the preamble of claim 1, from the US-PS 38 06 887 known type.

With fast-working, extensive data processing systems it is particularly useful for analyzing and recording Disturbance conditions desirable to be able to the state of locking and other circuits in the data processing system capture. In known systems often directly wired key points in the data processing system provided and on a control panel or a console led to light up the console lamps to let and so an indication of the state of the memory circuits to give in the system. The direct wiring is however unwieldy with large data processing systems and extensive because the number of indicator lights on the System console for a convenient analysis by the operator gets too big.

In other known systems, the ability of Data processing system used for calculation to data to spend, using more common Data paths of the data processing system for storage the state of the circuits within predetermined storage locations of system memory. The use of more common Data paths in the storage system offer the difficulty that if the data path is faulty or the control circuit is faulty, that is connected to the data path, the output Information is incorrect, so the localization of errors and their isolation difficult and time consuming is.  

From US-PS 38 76 987 is also a data processing system known in which a variety of processors can perform a mutual diagnosis. Here is each processor for the detection of its own fault responsible. If an error occurs, the interrupts Processor its own data processing operations. Then a second processor, which is also interrupts its data processing operations to which Access circuit paths of the main processor and run a diagnostic program. This diagnostic program intervenes in the operation of the main processor.

From the above-mentioned US-PS 38 06 887 is a data processing system known, where two identical, programmable central processors in a redundant way work to provide reliable operation. Maintenance access circuits are also provided with whose help is the primary central processor in place of the access redundant, second central processor can to initialize certain circuits and thus maintain parallel operation. For execution troubleshooting and maintenance programs the main command program are interrupted.

It is therefore an object of the invention to provide a data processing system propose where the main command program and the auxiliary or diagnostic command program simultaneously can run without the operation and that of the execution of the main command program Logic states of the main processor circuitry to be influenced.

The solution to this problem is based on the characteristic Features of the new patent claim 1.

Advantageous embodiments of the invention are the subject of subclaims 2 to 4.  

The invention relates to a data processing system with a main processing device for executing the main or first-rate data processing operations and a secondary processing device for independent Addressing and independent access to storage spaces in the main processing facility.

In a preferred embodiment of the invention contains the secondary processing device a command-controlled Digital computer that works with the rest or the main processing facility of the data processing system via a console control interface communicates. The console control interface receives addresses from blocking or other Circuits in the main processing facility and addressed or controls such circuits via a query address rail to parallel across the entire main processing facility multiple positions is switched. A group of circuits including the addressed circuit within of the system is controlled to determine their states by the Console control interface via a query data rail transferred to. The information on the query data rail is saved back to the digital computer. The digital computer analyzes the returned information and identifies errors or performs other operations.

According to a further embodiment of the invention, this is Data processing system with logic circuits on integrated Circuit chips executed. The integrated Circuit chips, each containing several circuits, are formed on a carrier that serves as a carrier for inclusion multiple chips (MCC) is called. Any MCC receives address bits and from the query data rail provides for a query line to return the information. The query lines from all MCCs form together the query data rail.  

Because the addressing and access under control by the auxiliary command program can take place in the digital computer the sequence in which the circuits are addressed and selected be easily changed, making yourself a big one Flexibility in the way the Information on fault localization or on any is made available for other purposes.

An embodiment of the invention is described below with reference to the drawing explained in more detail. It shows  

Fig. 1 is a block diagram of a data processing system;

Fig. 2 is a schematic representation of the console unit of Fig. 1;

Fig. 3 is a schematic representation of the interface controller and the console control interface in the console unit of Fig. 2;

FIG. 4 shows the schematic representation of the design of the data processing system of FIG. 1 with carriers for multiple chips (MCC), which are addressed and queried by the console control interface of FIG. 3;

Fig. 5 is a schematic representation of the physical training of a typical MCC;

Fig. 6 shows the schematic representation of the logical arrangement of the chips on a typical MCC;

FIG. 7 shows the schematic representation of various data paths in the execution unit in the system of FIG. 1;

Fig. 8 is a schematic representation of the chip arrangement of the 1H register which forms part of the data path of the arrangement of Fig. 7;

FIG. 9 shows the schematic representation of a chip assigned to a bit in the circuit of FIG. 8; FIG.

Fig. 10 is a schematic view of the recording chip of the circuit of Fig. 8 containing MCC and

Fig. 11 is a schematic representation of an alternative embodiment of the chip select circuit.

The data processing system shown in FIG. 1 contains a main memory 2 , a memory control unit 4 , a command unit 8 , an execution unit 10 , a channel unit 6 with associated input / output and a console unit 12 . The system of FIG. 1 is controlled by commands from the main processing device, an organized group of these commands forming a system program. The system commands and the data which are processed by the commands are fed into the main memory 2 by the input / output unit via the channel unit 6 and the memory control unit 4 . From the main memory 2 , the system commands and data are passed through the command unit 8 via the memory controller 4 and processed in such a way that they control the execution in the execution unit 10 . The system of Fig. 1 is described in more detail in US-PS 38 40 861.

According to Fig. 4, the logic circuits and other circuits which all or a major portion of the system of FIG. 1 include running on a MCC 602, each carrier more running on chips, integrated circuits includes (Fig. 5), for example. B. up to 64 MCCS 602 with MCC (0, 0),. . ., MCC (7, 7). Each of these carriers typically contains up to 42 chips, which are arranged in a (6 × 7) rectangular arrangement according to FIG. 5. Further details of the structure of chips which are suitable for arrangement on chip carriers are described in US Pat. No. 3,8 08,475.

FIG. 2 shows further details of the console unit 12 of FIG. 1. The console 12 contains a digital computer 501 , which is connected to a 32K memory 502 in a conventional manner. The digital computer 501 is connected to several control devices, for example a plate control unit 516 , a channel control unit 411 , a console control unit 513 and an interface control unit 511 . In an analogous manner, additional control units can be connected to the digital computer 501 shown.

The disk control unit 516 forms an interface between the digital computer 501 and a 256K disk input system 528 . The channel control unit 411 is one of the channel control units assigned to the channel unit 6 of the figure . The console control unit 513 forms an interface between the digital computer 501 and the control console 524 . The interface control unit 511 forms an interface between the console control interface 525 and the digital computer 501 .

The digital computer 501 is typically a computer called Nova 1200 from Data General Corporation. The details of the operation of such a computer and the manner in which the control units, such as the control units 411, 511, 513 and 516 of FIG. 2, are connected to the computer or form interfaces for the same are described in the document DG NM- 5 "How to use the Nova Computers", April 1971, Data General Corporation.

The interface control unit 511 , which is connected to the digital computer 501 by the 48-bit rail 535 , is connected via the rail 533 to the console control interface (CCI) 525 , which in turn is connected via a query rail 436 to circuits in the data processing system of FIG. 1 connected is. The connections from the console control interface 525 designated I-unit, C-unit and S-unit are described in more detail below.

Fig. 3 shows further details of the console control interface 525 and the interface control unit 511. The console control interface (CCI) 525 includes a 16-bit command register (CR) 551 with a 16-bit control command rail 540 which is the input to the I and C units, which will be described below. The control interface 525 also includes 16-bit address registers 552 and 553 that feed the 32-bit output address rail 542 that is connected to the address paths in the I and S units of the data processing system.

Control interface 525 also includes 16-bit data registers 554 and 555 , the outputs of which feed 32-bit console data rail 543 , which acts as console data input to the data paths in the C, S, and I units of the data processing system of FIG . 1 is used.

The registers 551 to 556 and the sampling gates 561 to 565 are addressed by the decoded output signals of a decoder 567 , which decodes and selects one of these eleven units according to the address in the 4-bit query address register 574 in the interface control unit 511 .

The control interface 525 additionally contains a 9-bit query address data register 556 which, via a 9-bit query address rail 590, determines the circuits in the data processing system which are to be queried.

The control interface 525 also includes a 64-bit scan data rail 591, which is connected to 16-bit output gates 561-564. A controlled 16-bit-bar 592 connects via the selector circuit 476 and the rail 535, the state of gate 572 via the select circuit 576 and the rail 535 with the digital computer five hundred and first Decoder 567 receives the 4-bit input signal from polling address register 574 and decodes the 4-bit address on one of the eleven lines 621-1 through 621-11 . Dial lines 621-7 through 621-11 select scan gates 561 through 564 and status gate 565, respectively. The gates 561 through 565 , which are 16-bit gates, are supplied with the rails 634-1 through 634-4 , which form the 64-bit query data rail 591 . The controlled rail 592 receives the status information from the I unit in the data processing system of FIG. 1.

Control interface 525 also includes console interface controller (CIC) 570 , which includes logic circuitry that generates output signals in accordance with the overall input signals designated as lines 541 . In detail, the clock signals of the I-unit are triggered by the START line, whereby the control signals for the entire system of FIG. 1 are formed. The S, I and C VALID lines 545 , one of which is provided for each unit S, I and C , give a signal when one or more of the selected units is to be energized in order to receive control commands from the console unit .

If the S, I or C unit has received a VALID signal, they indicate the receipt of this signal via the S, I and C COMP lines 544 , with S, I and C per unit a COMP line 544 is provided. Line 595 , which indicates the active state of the I-unit, signals the states STOP, PSW WAIT, CHECK STOP and METERING when these occur in the system of FIG. 1. The OP END line detects the control pulses in the system of FIG. 1. If the delay between pulses exceeds a fixed duration, there is an error state in the system of FIG. 1. The OP END line serves as an input to a STOP detection circuit 581 which detects the time between control pulses and generates an output signal indicating an illegal delay.

The interface controller 570 , the STOP or interrupt detection circuit 581 and the STOP line indicate the state of the system of FIG. 1 via the active state gates (AS gates) 582 via the lines 584 connected to the selector circuits 576 . Gates 583 poll 8-bit interrupt mask register (IMR) 579 . Gate 582 and register 579 have a bit-bit relationship, that is, bits 0, 1,. . ., 7 correspond to the control commands S COMP, C COMP, STOP, PSW WAIT, CHECK STOP, HANG DETECTOR or METERING.

Interrupt mask register 579 determines the signals on output line DONE from gate 583 . Because of the bitwise correspondence between the bits in the IMR 579 and the bits in the active state gates 582 , the activation of a bit in the active state gates sets the DONE line when the corresponding bit in the register 579 is not set. If the bit in register 579 is set, the output line DONE of gate 583 is not set.

The turn-on register 578 stores three information bits that determine which of the S, I and C VALID lines 545 should be energized. Bit 0 denotes the selection of the S unit, bit 1 the selection of the I unit and bit 2 the selection of the C unit. The remaining decoded states of the three bits in the switch-on register 578 are ignored.

The interface controller (CIC) 570 is responsive to an input START line which also energizes the output START line. In addition, the START-CIC input line initiates the operation of the interface controller 570 . The input line CLEAR-CIC clears the CIC interface controller 570 from the digital computer 501 before the arrival of a new command for the system of FIG. 1.

According to FIG. 4, the polling address rail 3 is connected in parallel to a plurality of MCCs 602, so that a certain chip on each MCC, and further a certain blocking circuit may be driven on the address chip for each MCC 590 of Abfrageadressen- data register 556 of FIG.. The state of the addressed blocking circuit appears as an output signal on the corresponding query line 603 . For example, an output signal is provided by the addressed inhibit circuit on the MCC (0, 0) on query line 603 (0, 0). Similarly, each of the 64 MCCs of Figure 4 has a corresponding query line 603 ; this creates the 64-bit query data rail 591 . The data rail 591 is connected as an input to the scan gates 561 to 564 ( FIG. 3).

Fig. 5 shows a typical chip carrier MCC 602, which consists of 42 chips 606th The chips are expediently arranged in seven rows 1 to 7 and in six columns A to F. Each of the logic chips 606 contains multiple circuitry for implementing the logic functions and memory functions that are performed in the system of FIG. 1. Furthermore, at least one of the chips, for example chip 1F in FIG. 5, is a query or registration chip to which the 9-bit query address rail 590 is connected and which feeds the 1-bit query line 603 , which together with the others 1-bit query lines from the other MCCs form the query data rail. Instead of at location 1F in the exemplary embodiment in FIG. 5, any chip location can contain the registration chip, since the actual location in the arrangement is unimportant. In Fig. 5, each MCC is shown in typical embodiment as containing up to 42 chips, each chip being disposed on its chip carriers on a certain place.

FIG. 6 shows the MCC shown physically in FIG. 5 in such a way that its logical accessibility is made clear by the query arrangement. The logic MCC of FIG. 6 contains 32 addressable logic chips, with each logic chip 608 in FIG. 6 including at least one chip 606 of FIG. 5. Since only 32 addressable chips are provided in FIG. 6, each logic chip 608 can expediently contain a non-addressable chip 606 or part of a chip 606 . The registration chip 611 in FIG. 6 corresponds to the chip 1F in FIG. 5. The logic chips C (0, 0), C (0, 1),. . ., C (0, 7) of FIG. 6 are arranged in a first of four lines. The chips 608 in FIG. 6 may correspond to any combination of the chips 606 . The 9-bit query address rail 590 is fed to the registration chip 611 in FIG. 6; it feeds a 1-bit query line 603 to the query data rail 591 of FIGS. 3 and 4. In addition, the registration chip 611 feeds eight output column select lines 614-1 through 614-8 and four chip select lines 613 . Next the 4-bit rail is connected 612 to the registration chip 611, which consists of four lines of scanning lines 612-1 to 612-4. Each line 612-1 through 612-4 receives the query data from a row of eight logic chips 608 that feed a common line via an OR operation.

The registration chip 611 of FIG. 6 receives the 9-bit address on the query address bar 590 . The three higher order bits of this 9-bit rail 590 are decoded to choose one of the eight lines 614 . The selected line 614 , for example the line 614-1 , selects the corresponding column, for example the column C (0, 0), C (1, 0), C (2, 0) and C (3, 0). The four low order bits of the 9-bit address on poll address rail 590 are transmitted over dial line 613 to select 1 to 64 circuits on each chip 608 . The state of the selected circuit on each chip is then output to the corresponding line scan line 612-1 through 612-4 . The remaining two (middle) address bits on the rail 560 are used in the registration chip 611 to select one of the four line query lines 612 for transmission as an output signal on the query line 603 . The query arrangement is described in more detail below in connection with a typical exemplary embodiment. The described embodiment is the 1H register shown in FIG. 7 in the execution unit 10 of the system of FIG. 1.

FIG. 7 shows the 1H register 24 between the LUCK unit 20 and the byte adder 32 , all of which are part of the execution unit 10 of the system of FIG. 1. Further details of the 1H register and its operation in the execution unit of the system of FIG. 1 are described, inter alia, in US Pat. No. 3,792,362.

In general, the 1H register 24 is a 32-bit register to which input data from the LUCK unit 20 are supplied and whose output is connected to the byte adder 32 , among other things. The information is fed into the register 24 by a clock pulse on a line 631 from a clock generator 102 . The details of the clock operation for entering data into register 24 are described in said U.S. Patent No. 3,792,362. In this document, a typical bit, designated as bit position 124 , is described as containing a disable or input circuit. The latch or input circuit 124 of register 24 of FIG. 7 is further shown in FIGS. 8 and 9.

In Fig. 8, bit 124, which is bit space 24, which represents 32 bits 0 through 31, is on chip 606-1 . In addition to bit 24 of register 24 in FIG. 7, bits 25 to 31 are arranged on chips 606-2, 606-3, 111, 606-8 , which are designated as BIT 25, BIT 26 ,. . . or BIT 31 are designated. Bit 24, designated 606-1 , is one of chips 606 like that previously described with reference to FIG. 5. Similarly, each of the other chips 606-2 through 606-8 is also identical to chips 606 in FIG. 5. The eight chips 606-1 through 606-8 form part of the eight forming a row, for example forming row 0 in FIG. 6 Chips that have a common output 612-1 designed as an OR link.

In addition to chips 606-1 through 606-8 , the logic chips of FIG. 6 contain further logic circuits in one row, which are not formed on the same chip. For example, a logic chip C (0, 0) includes the physical chip 606-1 and the logic gate 623-1 . Similarly, logic chip C (0, 1) of FIG. 6 includes chip 606-2 of FIG. 8 and column selection gate 623-2 . Column selection gates 623-1 and 623-2 are formed on different physical chips in a preferred embodiment. Similarly, chips 606-3, 606-4 and 606-5 of FIG. 8 are three different physical chips and are each connected to a column select gate 623-3, 623-4 and 623-5 , respectively. In a preferred embodiment, column select gates 623-3 through 623-5 are formed on a single physical chip. Similarly, chips 606-6, 606-7 and 606-8 are each three different physical chips, while the corresponding selector gates 623-6, 623-7 and 623-8 are arranged on a different physical chip. In the manner described, the circuit 617-1 arranged on physical chips in the manner described forms a line from C (0, 0) to C (0, 7) of logic chips 608 .

In the same way that circuit 617-1 represents a row of eight logic chips for a 601- type MCC, similar additional circuits 617-2, 617-3, and 617-4 form rows of logic chips, each of which is one sense line 612- Feed 2, 612-3 or 612-4 . The four lines 612-1 through 612-4 form the 4-bit rail 612 . Each of the row circuits 617-1 to 617-4 are supplied with the eight column select lines 614 and the four chip address lines 613 , which originate from the registration chip 611 in FIG. 6.

Further details of bit 24 chip 606-1 , which represents bit 24 in 1H register 24 of FIG. 7, are shown in FIG . According to FIG. 9, the chip 606-1 includes the locking or latch circuit 124-1, the bits 0 to 31, the bit 24 of the 1H-register 24 in FIG. 7. The latch circuit 124-1 receives its input signal from the LUCK unit 20 via lines 652 , one of which is a data line and the other a control line. Similarly, circuit 124-1 receives input signals from the shifter via lines 653 , one of which is a control line and the other a data line, and of the adder via lines 654 , one line of which is also a data line and the other of which is a control line. Circuit 124-1 further includes a synchronous reset input connected to line 651 for resetting the circuit at appropriate times during the operation of the data processing system. In addition, circuit 124-1 receives inputs on lines 631 and 632 to control the clock of the circuit. Line 631 is an input line from clock 102 , while line 632 is a disable control to prevent clock control of circuit 124-1 . The output 656 of the circuit 124-1 is connected to a phase splitter 637 , which is the first level I of the logic assigned to the byte adder (US Pat. No. 3,814,925 ). In addition to being connected to phase splitter 637 , which is the normal data path of the system of FIG. 1, latch circuit 124-1 has an output to an additional phase splitter or splitter 638 , which is the beginning of the query data paths of the system of FIG. 1 .

In addition to the circuit 124-1 , the chip 606-1 in a preferred embodiment contains a hold circuit 124-2 which is assigned to the BIT 24 in the 2H register 25 of the circuit of FIG. 7. Similarly, chip 606-1 includes latches 124-3 and 124-4 corresponding to bits 24 of the 1L and 2L registers, which are additional registers connected to execution unit 10 , but which are not otherwise specifically described in the present description. The output of latch 124-2 on line 657 is connected to phase splitter 637 and phase splitter 638 in a manner similar to the outputs of circuits 124-3 and 124-4 .

Phase splitter 638 includes a gate 639 that supplies the state of circuit 124-1 , as indicated on line 656 , to select gate 641 . The select gate 641 is one of four gates in the select circuit 640 for appropriate selection of which of the four circuits 124-1 through 124-4 is to be connected to an output line 643 . The choice of gate in selector 641 is controlled by a decoder 642 , which includes two bipolar gates 645 and 646 , which are responsive to two bits on lines 613-1 and 613-2 of 4-bit rail 613 . The two bits on lines 613-1 and 613-2 are decoded so that one of the four gates in the selector circuit 640 is uniquely selected. When lines + LA and + LB are energized by gates 645 and 646 , respectively, gate 641 is selected and provides an output on line 643 which is input to gate 644 which provides the outputs on line 619 . According to FIG. 8, the output signal on line 619, the output signal for the chosen chip-BIT 24. In the circuit 606-1 of FIG. 9, only two of the four chip address lines of the rail 613 are used, namely the lines 613-1 and 613-2 . The two binary addresses uniquely determined by these two lines determine one of the four latch circuits 124-1 to 124-4 . Additional lines 613-3 and 613-4 can be used so that, according to a preferred embodiment, up to 16 holding or other circuits per chip can be used. The output signal on line 619 ( FIG. 9) represents one or four latches on chip 606-1 . If more, up to 16 latches, are used, the output signal on line 619 represents one of 16 latches represented by Address can be addressed on rail 613 .

Fig. 10 shows further details of the recording or registration chip 611 of Fig. 8. The registration chip 611 receives the nine input address bits on the query address bar 590 . The three higher order bits on lines 590-1, 590-2, and 590-3 are input signals to column select decode circuit 626 , where they are decoded in the usual manner to select eight output lines 614 . The eight output lines 614-1 through 614-8 from the rail 614 are connected as inputs to each of the row selection circuits 617-1 through 617-4 of FIG. 8. In the circuit of Fig. 8, the column select lines operate so that one of the gates 623-1 to 623-8 is selected in accordance with the three input address bits .

The next two higher order bits of query address bar 590 appear on lines 590-4 and 590-5 where they serve as input signals to row decoder and selector circuit 627 . In circuit 627 , the two bits on lines 590-4 and 590-5 are selected to select one of the four gates 661-1 through 661-4 that is on rail 612 by the MCC of FIG. 8 line state lines 612 -1 to 612-4 receives. The line of the four lines 612 selected according to the information coded in the input bits 590-4 and 590-5 or the signal present there appears as the output signal on line 603 , which is one of the 16 bits of the rail 634-1 , the one of 64 bits in the 64-bit query data rail 591 of FIG. 4.

Similarly, the four lower order bits on lines 590-6 through 590-9 are energized in power driver circuit 628 and via rail 613 to each of the chips on MCC 601 of FIG. 6, and particularly row chips 617-1 of FIG Fig. 8 retransmitted. The signals on lines 590-6 to 590-9 appear as identical signals on each of lines 613-1 to 613-4 .

In the following the operation of the device is closer described.

The main processing device of FIG. 1 receives information from the memory controller 4 and the main memory 2 , controlled by the main instructions processed by the instruction unit 8 . The execution unit 10 processes the main instructions, controlled by the information from the instruction unit 8 . For example, some main instructions in the main processor use an adder in execution unit 10 ( FIG. 7). When a main instruction is being processed, the information is supplied to adder 32 of FIG. 7 via LUCK unit 20 , where it is stored in 1H register 24 and 2H register 25 . The information held in registers 24 and 25 is added by adder 32 ; the results appear in register 38 . The operation of the main processing device of FIG. 1 in the execution of main instructions is described in US Pat. Nos. 38 40 861 and 37 92 362.

The data are entered into register 24 at a time controlled or predetermined by the clock signal on line 631 . Line 631 sets each of bit locations 0 through 32 of register 24 and the highlighted bit 24 of the 1H register, designated 124-1 . The setting of latch 124-1 and the other bit positions in register 24 are generally controlled by the main processor when executing the instructions of a main instruction stream.

The digital computer 501 of FIG. 2 takes the information from address locations in the main processing device of FIG. 1 in accordance with a program of secondary instructions. The operation of the auxiliary processing device and the program of the auxiliary commands in the digital computer 501 is independent of the operation of the main processing device when executing the main commands.

In a preferred embodiment, the address locations in the main processing device of FIG. 1 are determined in accordance with a 16-bit binary address that is generated or specified by the digital computer 501 . This address has the following meaning.

Bits 0 and 1 designate one of four groups of 16 MCCs and especially their output lines 603 . Bits 0 and 1 are decoded to select one of the four key gates 561 through 564 in FIG. 3, and thus one of four groups of the 16 lines.

Bits 2 to 5 designate one of the 16 information bits, that appear on one group of 16 lines that selected by bits 0 and 1.

Bit 6 determines whether the selected information bit 5 of the 64 MCCs of FIG. 4 has to be inverted in order to obtain the correct polarity. Bit 6 is useful in a preferred embodiment because inverting logic is used in a preferred technology. In the case of inverting logic, the presence of an odd or even number of logic levels in the transmission of the information to the sampling gates determines whether the information has correct or inverted polarity. By using bit 6 in the present address format, the addressed information can be arbitrarily returned to the scan gates without having to apply an odd or even number of logic levels. The correct polarity for each tapped information bit is formed by suitable setting of bit 6.

Bits 7 through 9 select one of eight columns of chips 608 in FIG. 6. Bits 7 through 9 represent three of the nine address bit outputs on the query address rail 590 of FIG. 3.

Bits 10 and 11 select one of four rows of chips 608 in FIG. 6. Bits 10 and 11 are two of the nine address bits on the query address bar 590 .

The four bits 12 through 15 select one through 16 circuits on each chip 608 of FIG. 6. Bits 12 through 15 are the four remaining bits of the nine address bits on the query address rail 590 of FIG. 3.

While any circuit location for access by the digital computer 501 can be made addressable in the main processing device, the 1H register 24 and in particular the bit 24 location ( FIG. 7) is selected as a special example.

Bit 24 of 1H register 24 has the following 16-bit binary address:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0

In the binary address of bit 24, bits 0 and 1 represent a binary 3 indicating that the SCAN-2 scan gate 563 is the energized gate. The scan gate 563 receives the addressed information from the main assembly, and in particular the 16 lines 603 from the MCCs MCC (0, 4), MCC (1, 4),. . ., MCC (7, 4) and MCC (0, 5), MCC (1, 5),. . ., MCC (7, 5).

Bits 2 to 5 of the 24-bit address represent a binary 10 represents what the desired information bit is on the tenth MCC, the MCC (1, 5) appears in the group of MCCs, which are determined by bits 0 and 1.

The 0 in bit 6 of the above binary address indicates that none Inversion in the return to bit 24 of the 1H register Information is required.

All 0 for column select bits 7 through 9 and row select bits 10 and 11 indicate that bit 24 is in the 1H register on the chip located in column 0 and row 0 of the chips. Referring to FIG. 6 is located in the column or row 0 is the chip C (0, 0).

Referring to FIG. 10, the bit 7 input on lines 590-1, 590-2 and 590-3 8 and 9 to select the output line 614-1 column 0 of the eight lines 614th Line 614-1 in FIG. 8 selects 0-gate 623-1 , the other input of which provides the output on line 619 from place 606-1 of bit 24 in the 0 column of 0-row 617-1 . At the same time, rows 617-2, 617-3, and 617-4 select a 0-column output on their lines 612-2, 612-3, and 612-4 .

In FIG. 10, bits 10 and 11 for line selection are input signals on lines 590-4 and 590-5 and are selected for selection of gate 661-1 , which thereby makes 0-line line 612-1 from four line lines 612 selects that starts from the circuit of FIG. 8.

In FIG. 10, bits 12, 13, and 14 and 15 are input signals on lines 590-6 through 590-9 that appear on output rail 613 , which in turn is input to the chips of FIG. 6, including chip C (0 , 0), which is the chip 606-1 in FIGS . 8 and 9. In Fig. 9, two of these four bits are actually used in a preferred embodiment, particularly the two bits on lines 613-1 and 613-2 . Since bits 12 are to 15 to 0 level, turn on the gate 645 and 646 with + LA and + LB in the state of 0. The 0 state of these two output signals is fed as input signal to the decoder 640, so that the gate 641 turns on and level 0 is present at inputs + LA and + LB. With gate 641 thus switched through, the output of gate 641 is controlled by the state of line 656 ' from gate 639 . Gate 639 provides a connection from the inverting output of latch 124-1 on line 656. The inverted output signal on line 656 has the inverted value of addressed bit 24 of the 1H register.

The output signal on line 656 is inverted in gate 639 , gate 641 , gate 644 , gate 623-1 ( FIG. 8) and gate 661-1 ( FIG. 10) and provides one of the 64 addressed input signals on the Line 603 to 64-bit query data rail 591 . The number of reversals from line 656 to line 603 of FIG. 6 is five, so that when connected to the inverted output signal itself on line 656 , the correct polarity is presented in key gate 563 of FIG. 3.

The digital computer 501 of FIG. 2 acts via the interface controller 511 and the console control interface 525 to carry out the required addressing and the required access to information in the main processing device of FIG. 1 in accordance with a sub-instruction program according to the following Table I:

Table I

The execution of the above secondary instruction program is described in connection with bit 24 in the 1H register 24. In a preferred embodiment, digital computer 501 is a nova computer using the standard nova commands. A jump subroutine (JSR) is used to enter the Table I program. The computer jumps to the address XLOGB (S1). According to instruction S1, a return address is stored in the accumulator 3 in the accumulator 2.

Before the instruction S2, the 16-bit address of the 1H register Bits 24 stored in accumulator 0.

According to instruction S2, the accumulator 1 with the content a fixed address LGAMK loaded at S49. As with S49 shown, the value 000777 is given in octal value.

In instruction S3, the contents of the accumulator become 0 and the accumulator 1 is subjected to a logical AND operation, so that the address bits 7 to 15 at the places 7 to 15 of the accumulator 1 are stored.

In instruction S4, bits 7 to 15 in accumulator 1 subtracted from the contents of bits 0 to 15 of accumulator 0, so that bits 0 to 6 in the accumulator 0 to the Places 0 to 6 remain and bits 7 to 15 of the accumulator 0 are now equal to 0.

In instructions S5, S6 and S7, bits 7 to 15 on the places 7 to 15 of the accumulator 1 on the places 0 to 8 of the accumulator 1 shifted.

In instruction S8, the contents of the accumulator 1 are complemented to bring the information into the required form when it is transferred to the system through the output data register (ODR) 575 of FIG. 3.

A system call prevents instructions S9 and S10 an interruption of the command stream pending instructions  S25 and S26.

In instruction S11, address bits 7 to 15 in positions 0 to 8 of accumulator 1 are transferred to output data register (ODA) 575 in interface controller 511 .

In instruction S12, the accumulator 3 with the content a fixed address SADR loaded at S43. As stated in S43, is the SADR address content 1200000 in octal code.

In instruction S13, the content of the accumulator 3 is transferred to the interface control unit 511 and entered in SAR 574 . Decoder 567 decodes octal code 1200000 and switches input gate 548 to SADR register 556 via line 621-6 . In instruction S13, a signal is also generated on line 549 which turns on gate 548 which, together with the signal on line 621-6, inputs the 9-bit address from ODR register 575 into SADR register 556 . At instruction S13, the slave processor addresses the master processor in response to the slave instruction program of Table I according to the 9-bit address in register 556 .

In instructions S14, S15 and S16, the address bits 0 and 1 in accumulator 0 from positions 0 and 1 places 14 and 15 shifted. This operation leaves the Transfer bits 2 through 6 in places through 4.

In instruction S17, the accumulator 1 with the content a fixed address RMSK loaded at S50. As in S50 mentioned, the value in octal code is 000003.

In instruction S18 the content of the accumulator 0 ANDed with that of the accumulator 1, so that the accumulator 1 because of the mask address bits 0 and 1 in places 14 and 15.

In instruction S19, address bits 2 through 6 are over  four transfer points of the accumulator 0 into positions 0 to 5 of the accumulator 0 transmitted.

In instruction S20, the accumulator 3 with the content a fixed address GRPT loaded which is the address of S44 plus one is.

In instruction S21, the contents of bits 0 and 1 of accumulator 1, which are a binary 2 for bit 24 of the 1H register, are added to the address in accumulator 3 in order to identify the addressed gate of the four key gates 561, 562, 563 or To designate 564 in FIG. 3.

In instruction S22, the accumulator 1 with the scanning gate address loaded from the content of the place, its address in the accumulator 3.

At instruction S23, the scan gate address of the accumulator 1 is input to the SAR register 574 and decoded by the decoder 567 to select the gate 563 .

In instruction S24, input gates 572 are switched through and the 16 bits of the query information are thus input into the accumulator 1 by the gates 563 . At instruction S24, access to the information from the main processing device is completed. The information acquired in S24 is the information addressed in S13.

In the case of instructions S25 and S26, the locking effect is set to the interruptions formed in instructions S9 and S10 away.

Instructions S27 through S38 are applied using more conventional ones Programming procedure the address bits 2 to 6 analyzed in accumulator 0 and determined which of the 16th Bits of the query information in the accumulator 1 the desired Bit is the state of bits 24 in the 1H register corresponds. The program determines that this is the tenth Bit is. With instruction S38, this bit is inserted into the Transfer places.  

With instruction S39, address bit 6 is queried. This leads to a jump or branch to S40 if the tenth bit output must be complemented.

In instruction S40, the complement is formed if this proves to be necessary, given by S39.

At S41, the tenth bit output is in the carry place entered in place 15 of the accumulator 0.

With instruction S43, the program is ended, and that secondary data processing system returns to that specified in S1 Return address back.

Fig. 11 shows an alternative embodiment for the decoding and selection circuits, in which the four bits are used for addressing by a chip. Specifically, the 9-bit query address rail 590 connects the four 1-chip bits 590-6, 590-7, 590-8 and 590-9 as inputs to a 4/7 converter 586 . In a preferred embodiment, converter 587 encodes the four input bits 590-6 to 590-9 according to Table II below. In Table II, the four address lines 590-6 through 590-9 are shown in column lines 590- . The converted output signals appear in Table II as lines 597- .

Table II

Referring to FIG. 11, the converter 586, a 7-bit-bar 597 with decoders 587-1, 587-2. . ., 587-8 . Decoders 587 each contain multiple input gates 598 with three inputs. Gate 598-0 receives two of seven output signals on rail 597 and an input signal via line 473 which is connected to certain circuits of the data processing system of Fig. 1 to which the information must be communicated when gate 598-0 is through Input signals with the level 0 on the two lines 597 is switched through. Gate 598-0 typically receives input signals 597 -A and 597 -B from seven lines 597 . The signals on these lines correspond to octal code 0 and clearly select gate 598-0 .

Similarly, gate 598-1 is connected to input lines 597 -A and 597 -D, which are octal 1 in Table II. The outputs of the gates 598-0 to 598-7 are commonly supplied to the first gate 599-1 from eight column gates 599-1 to 599-8 . The outputs of the decoders 587-2 to 587-8 are each connected in a similar manner to one of the column gates 599-2 to 599-8 .

The eight column gates 599-1 to 599-8 are in turn connected to one another and feed the output line 612'-1 , which is analogous to line 612-1 in FIG. 8. Lines 612'-1 to 612'-4 are similar to the four lines in rail 612 of FIG. 10.

In a preferred embodiment, both decoding systems of FIGS. 9 and Fig. 11 are applied. In a preferred embodiment, the typical circuit connected to line 473 is taken from the console unit. Line 473 detects the active state of the circuit. As explained with reference to FIG. 9, bit 24 of the 1H register is a blocking or holding circuit for comparison.

Accordingly, the invention  either on the output or reading the status of holding or other storage elements in the data processing system or on the output of the state certain lines are used that are independent of Keeping data dynamically changeable. While the sampled circuits predominantly hold circuits it can be seen that the state of any Circuit can be queried.

Claims (5)

1. Data processing system with

• a main processing device which has a multiplicity of main circuits which are connected to one another by main circuit paths and process data under the control of a main instruction program, each main circuit being set to a specific logic state as a result of the execution of the main instruction program,
• - A polling device responsive to polling addresses for addressing selected main circuits and
• a secondary processing device operated under a secondary instruction program for generating the query addresses,

characterized,

• - That the operation of the secondary processing device ( 501, 511, 525 ) takes place under the secondary command program independently of the operation of the main processing device under the main command program and
• - That the interrogator interrogation circuit means ( 590, 591 ), which are arranged separately from the main circuit paths, so that the logical states of the selected main circuits can be accessed independently of the main circuit paths under control of the auxiliary instruction program.

2. Data processing system according to claim 1, characterized in that the secondary processing device has the following components:

• a programmable digital computer ( 501 ) for exchanging information with devices via a plurality of control devices ( 516, 411 ) in accordance with the auxiliary command program,
• an interface control unit ( 511 ) which serves to exchange information with the digital computer ( 501 ) and which contains an output data register ( 575 ) for outputting addresses of the main circuits and a query address register ( 574 ), and
• - A control interface ( 525 ) connected between the interface control unit ( 511 ) and the main processing device and containing a polling device that is switched so that it is turned on by the polling address register ( 574 ) according to the sub-instruction program for addressing and accessing the main circuits becomes.

3. Data processing system according to claim 2, characterized in that the control interface ( 525 ) contains a query address data register ( 556 ) which, when switched on, is connected to the output data register ( 575 ) and has an output which forms a query address rail ( 590 ), which is connected in parallel to several of the main circuits and that the interrogator includes sampling gates ( 561 to 565 ) connected in series with several of the main circuits by an interrogation data rail ( 591 ) and means ( 548 ) responsive to the by the sub-instruction program Turning on the polling address data register ( 556 ) and the scanning gates ( 561 to 565 ) address addresses generated, whereby the information is addressed and queried in the main processing device. 4. Data processing system according to claim 3, characterized by

• several integrated circuit chips ( 606 ), each containing several of the main circuits,
• a plurality of chip carriers ( 602 ), each containing an associated quantity of the chips and each connected to the query address rail ( 590 ) and supplying an input signal to the query data rail ( 591 ),
• - Devices ( 611 ) connected to each chip carrier ( 602 ) for addressing one of the associated number of chips in accordance with the information on the query address rail ( 590 ) and
• - means ( 640, 642 ) on each of the chips responsive to the query address rail ( 590 ) for addressing a particular master circuit on the chip and for connecting each addressed master circuit to the query data rail ( 591 ).