JPH07288282A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a symmetric configuration of external terminals with two arrays of bonding pads placed by including a pad switchover circuit for selectively switching function of first paired pads according to a predetermined switching control signal. CONSTITUTION:A pad switchover circuit PS supplies a switching control signal PSS via a bonding pad PPS. The switching control signal PSS replaces functions of pairs of bonding pads P2, P4 to P20, P23, that is, logic signals input or output via these bonding pads, selectively according to a high or low level with the bonding pad PPS coupled to a power voltage supply or ground potential supply bus bar leads and transmits them to respective parts of a dynamic RAM. Therefore, a symmetric configuration of external terminals with two arrays of bonding pads placed can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, for example, a dynamic RAM (Random Access Memory) in the form of a LOC (Lead On Chip) package.
The present invention relates to a technology that is particularly effective when used for random access memory).

[0002]

2. Description of the Related Art A so-called LOC in which bonding pads are linearly arranged along a center line of a semiconductor substrate surface, and a bus bar lead for supplying a power supply voltage and a bus bar lead for supplying a ground potential are arranged close to both sides of these pads. There is a package form, and there is a semiconductor device such as a dynamic RAM that takes such a LOC package form.

A dynamic RAM adopting the LOC package form is disclosed in, for example, Japanese Patent Laid-Open No. 3-214669.
It is described in Japanese Patent Publication No.

[0004]

In a dynamic RAM or the like in the LOC package form, the bonding pads including the power supply voltage supply pads and the ground potential supply pads are arranged linearly along the center line of the semiconductor substrate surface. ,
On both sides of these pads, bus bar leads for supplying a power supply voltage and for supplying a ground potential, which are made of a metal wiring layer such as aluminum, are arranged. Each bus bar lead is bonded to a plurality of power supply voltage supply or ground potential supply bonding pads with the shortest distance, and power is supplied to each circuit of the dynamic RAM via these bonding pads. As a result, the power supply impedance of the dynamic RAM can be reduced, its power supply noise can be suppressed, the flexibility of the pad arrangement can be increased, and the capability as a package, that is, the storage capacity can be improved.

However, as the capacity of the dynamic RAM and the like increases and the number of bits increases, the above L
The inventors of the present application have found that the dynamic RAM or the like having the OC package form has the following problems. That is, the increase in the capacity and the increase in the number of bits of the dynamic RAM result in an increase in the number of external terminals (pins), that is, the number of bonding pads, but the dynamic RAM adopting the LOC package form.
In such a case, since the arrangement position of the bonding pads is limited to the central portion of the semiconductor substrate surface, in order to accommodate a large number of bonding pads, a method of arranging at least two rows in a zigzag pattern is unavoidable.

On the other hand, in a digital system such as a computer having a memory device including a dynamic RAM, the capacity of the memory device is increasing, and a large number of packages of the dynamic RAM are provided on both sides of the mounting board, that is, the front surface and the back surface. A method of increasing the capacity of the board by mounting is adopted. At this time, the package of the dynamic RAM is TSOP (Thin Sma).
It is effective to improve the mounting efficiency by using a small package structure (such as a Small Outline Package: Small Outline Package). Furthermore, the external terminals are symmetrical in the package mounted on the front and back surfaces of the mounting board. Can be placed
It is effective in improving the wiring efficiency of the board.

As is well known, in order to symmetrically arrange the external terminals of the package mounted on the back surface of the mounting board with respect to the package mounted on the surface, the so-called reverse bending package in which leads serving as the external terminals are bent to the opposite side However, when the dynamic RAM adopts a small package structure such as TSOP, the reverse bending of the leads causes a decrease in structural reliability. To deal with this,
In the package assembly process, the bonding pad and the corresponding lead, that is, the bonding between the external terminal and the bonding terminal may be exchanged with each other to realize a substantially symmetrical arrangement of the external terminals. When arranged in two rows along the line, the swapping causes the bonding wires to cross, increasing the chance of short circuit failure. As a result, the bonding pad 2
The row arrangement becomes difficult, which limits the number of bonding pads that can be placed.

An object of the present invention is to provide a semiconductor device such as a dynamic RAM which can realize a symmetrical arrangement of external terminals without changing the bonding, that is, with the bonding pads arranged in two rows. It is another object of the present invention to increase the capacity of a dynamic RAM or the like in the form of a LOC package and ensure the reliability thereof while improving the mounting efficiency of a storage device or the like.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like that adopts the LOC package form, the first pads including the data input / output pads are arranged in two rows in a staggered manner along the center line of the semiconductor substrate surface to supply the power supply voltage and the ground potential. Pad switching circuit for arranging a second pad including a pad for a row along the center line of the semiconductor substrate surface and selectively switching the substantial function of the pair of first pads in accordance with a predetermined switching control signal To provide.

[0011]

According to the above-mentioned means, the second pads, which include the pads for supplying the power supply voltage and the pads for supplying the ground potential and are arranged in one row, are replaced with the bonding to secure the symmetry of the external terminals and to input the data. Including output pad and 2
With respect to the first pads arranged in rows, the pad switching circuit can replace the substantial functions of the pads without changing the bonding, and the symmetry of the external terminals can be secured. As a result, the symmetrical arrangement of the external terminals can be realized without changing the bonding, that is, without restricting the number of bonding pads.
It is possible to increase the capacity of a dynamic RAM or the like in the OC package form and ensure its reliability, while improving the mounting efficiency of a storage device or the like.

[0012]

1 is a block diagram of an embodiment of a dynamic RAM to which the present invention is applied. First, the outline of the configuration and operation of the dynamic RAM of this embodiment will be described with reference to FIG. The dynamic RAM of this embodiment is mounted on a predetermined mounting board together with a large number of other similar dynamic RAMs, but is not particularly limited, and constitutes a storage device of a computer system. Further, the circuit elements forming each block of FIG. 1 are known MOSFETs (Metal Oxides).
Semiconductor Field Effct
Transistor: A metal oxide semiconductor field effect transistor. In this specification, a MOSFET is a generic term for an insulated gate field effect transistor) and is formed on one semiconductor substrate surface such as single crystal silicon by a manufacturing technique of an integrated circuit. Further, in FIG. 1, the input or output node of the dynamic RAM is shown by the bonding pad shown in the parentheses, and the relationship between the input or output signal and the bonding pad shown outside the parentheses is shown in the dynamic RAM. The package is mounted on the surface of the mounting board as an example.

In FIG. 1, the dynamic RAM of this embodiment has a memory array MARY, which occupies most of the surface of a semiconductor substrate, as its basic constituent element. The memory array MARY is not particularly limited, but includes substantially 2048 word lines arranged in parallel in the vertical direction of FIG.
Substantially 9216 sets of complementary bit lines arranged parallel to the horizontal direction. An information storage capacitor and an address selection MOS are provided at the intersections of these word lines and complementary bit lines.
A substantial number of 18874368 dynamic memory cells made of FETs are arranged in a grid. As a result, the dynamic RAM of this embodiment is substantially 1887436.
It has a storage capacity of 8 bits, that is, a so-called 18 megabit.

2048 constituting the memory array MARY
The word lines of the book are coupled to the word line drive circuit WD and are selectively put in the selected state. The word line drive circuit WD is supplied with the same number of 2048-bit word line selection signals from the X address decoder XD. Further, the X address decoder XD includes X address buffers XB to 11
The bit internal address signals X0 to X10 are supplied, and the timing generation circuit TG supplies the internal control signal XDG. Further, in the X address buffer XB, 11 address input terminals A0 to A10, that is, bonding pads P15 to P20 and P23 to P27, are supplied to the X address signal AX via a pad switching circuit PS described later.
0 to AX10 are time-divisionally supplied, and an internal control signal XL (not shown) is supplied from the timing generation circuit TG.

The X address buffer XB fetches and holds the X address signals AX0 to AX10 supplied from the address input terminals A0 to A10 via the pad switching circuit PS in accordance with the internal control signal XL and holds these X address signals. Based on the internal address signals X0 to X1
0 is formed and supplied to the X address decoder XD. On the other hand, the X address decoder XD is selectively operated in response to the high level of the internal control signal XDG. In this operation state, the X address decoder XD decodes the internal address signals X0 to X10 and selectively sets the corresponding word line selection signal to the high level. The word line drive circuit WD receives the high level of the word line selection signal supplied from the X address decoder XD, and receives the memory array M.
The word line corresponding to ARY is alternatively set to the high level selected state.

Next, the memory array MARY is constructed 9
The 216 sets of complementary bit lines are coupled to the corresponding unit circuits of the sense amplifier SA. A bit line selection signal of substantially 512 bits is supplied from the Y address decoder YD to the sense amplifier SA, and an internal control signal PA is supplied from the timing generation circuit TG.

The sense amplifier SA is a memory array MAR.
Substantially 9216 provided corresponding to each complementary bit line of Y
Unit circuits, each of these unit circuits
It includes a unit amplifier circuit formed by cross-connecting a pair of CMOS inverters and a pair of switch MOSFETs. Of these, the internal control signal PA is applied to the unit amplifier circuit of each unit circuit.
A pair of drive MOSFs that are selectively turned on according to
The power supply voltage and ground potential of the circuit are selectively supplied via ET. In addition, the switch MOSFET of each unit circuit
The gates of are substantially connected in pairs of 18 pairs,
Corresponding bit line selection signals are commonly supplied from the Y address decoder YD.

The unit amplifier circuits constituting each unit circuit of the sense amplifier SA are selectively and simultaneously operated by the internal control signal PA being at a high level, and the selected word line of the memory array MARY is activated. Bound to 921
The minute read signal output from the six memory cells via the corresponding complementary bit lines is amplified to be a high level or low level binary read signal. On the other hand, a switch MOSFET that constitutes each unit circuit of the sense amplifier SA
Are selectively turned on by 18 pairs by setting the corresponding bit line selection signal to the high level, and the corresponding 18 pairs of complementary bit lines and complementary common data lines CD0 * to CD17 * ( Here, for example, the non-inverted common data line CD0 and the inverted common data line CD0B are collectively indicated by an asterisk such as a complementary bit line CD0 *, and when it is enabled, it is selectively set to the low level. For so-called inverted signals, etc., B is added at the end of the name.
It is indicated by adding. The same applies to the following).

The Y address decoder YD includes 9-bit internal address signals Y0 to Y from the Y address buffer YB.
8 is supplied, and the internal control signal YDG is supplied from the timing generation circuit TG. Further, the Y address buffer YB is supplied with the Y address signal AY from the nine address input terminals A0 to A8 via the pad switching circuit PS.
0 to AY8 are supplied in a time division manner, and an internal control signal YL (not shown) is supplied from the timing generation circuit TG.

The Y address buffer YB fetches and holds the Y address signals AY0 to AY8 supplied from the address input terminals A0 to A8 via the pad switching circuit PS in accordance with the internal control signal YL and holds these Y signals.
Internal address signals Y0 to Y8 are formed based on the address signal and supplied to the Y address decoder YD. On the other hand, the Y address decoder YD is selectively operated in response to the high level of the internal control signal YDG, decodes the internal address signals Y0 to Y8 supplied from the Y address buffer YB, and selects the corresponding bit line. The signal is alternatively set to the high level. As described above, these bit selection signals correspond to the 18 pairs of switches MO corresponding to the sense amplifier SA.
It is commonly supplied to the gates of the SFETs.

In this embodiment, the sense amplifier SA
Are eight sense amplifiers SA0 to SA, as will be described later.
The memory array MARY is divided into seven, and the memory array MARY includes eight pairs of memory arrays MARY to sandwich these sense amplifiers.
00 and MARY01 to MARY70 and MARY
71 are divided and arranged. The word line drive circuit WD and the X address decoder XD are arranged in the memory array MARY00.
And MARY01 to MARY70 and MARY71
Corresponding to 8 pairs of word line drive circuits WD00 and WD0
1 to WD70 and WD71 and X address decoders XD00 and XD01 to XD70 and XD71
The Y address decoder YD is divided into two parts, the Y address decoder YD0 corresponding to the even-numbered sense amplifiers SA0, SA2, SA4 and SA6, and the Y address decoder YD corresponding to the odd-numbered sense amplifiers SA1, SA3, SA5 and SA7.
It is divided into an address decoder YD1.

Complementary common data lines CD0 * to CD17 * to which 18 designated complementary bit lines of memory array MARY are selectively connected are coupled to data input / output circuit IO. The data input / output circuit IO includes a complementary common data line C
18 for each D0 * to CD17 *
It includes a write amplifier and a main amplifier, and a data input buffer and a data output buffer. Of these, the output terminal of each write amplifier and the input terminal of the main amplifier are commonly coupled to the corresponding complementary common data lines CD0 * to CD17 *. Further, the input terminals of the respective write amplifiers are respectively coupled to the output terminals of the corresponding data input buffers, and the input terminals of the respective data input buffers correspond to the corresponding data input / output terminals D0 to D17, that is, the bonding via the pad switching circuit PS. Pads P2 to P5
P7 to P11, P32 to P36 and P38 to P41
Respectively combined with. Further, the output terminals of the respective main amplifiers are respectively coupled to the input terminals of the corresponding data output buffers, and the output terminals of the respective data output buffers are respectively connected to the corresponding data input / output terminals D0 to D17 via the pad switching circuit PS. Be combined.

Each data input buffer of the data input / output circuit IO corresponds to the corresponding data input / output terminals D0 to D when the dynamic RAM is selected in the write mode.
1 supplied from 17 through the pad switching circuit PS
The 8-bit write data is fetched and transmitted to the corresponding write amplifier. These write data are converted into predetermined complementary write signals by the corresponding write amplifiers, and then the corresponding complementary common data lines CD0 * to
The data is simultaneously written to the selected 18 memory cells of the memory array MARY via the CD 17 *. On the other hand, each main amplifier of the data input / output circuit IO has corresponding complementary common data lines CD0 * to CD17 from the selected 18 memory cells of the memory array MARY when the dynamic RAM is selected in the read mode. The 18-bit binary read signal output via * is further amplified and transmitted to the corresponding data output buffer. These read data are transferred from the corresponding data output buffer to the pad switching circuit PS and the data input / output terminals D0 to D0.
It is sent to the outside via D17.

As a result, the dynamic RAM of this embodiment has a so-called x18-bit dynamic RA for simultaneously inputting or outputting 18-bit storage data.
It is assumed to be M and has a word structure of 1048576 words, that is, so-called 1 megaword × 18 bits.
The bit configuration of the dynamic RAM of this embodiment corresponds to the storage data of 2 bytes including the parity bit. Further, the dynamic RAM of this embodiment is
The column address strobe signal U is not particularly limited.
It has a so-called byte control function of selectively inputting or outputting one byte, that is, 9 bits of 18-bit storage data according to CASB and LCASB, that is, internal control signals UIO and LIO.

The timing generation circuit TG has an external terminal RA.
SB, that is, pad P14, external terminals UCASB and LC
ASB, that is, pads P30 and P31, external terminal WEB
That is, based on the row address strobe signal RASB, the column address strobe signals UCASB and LCASB, the write enable signal WEB and the output enable signal OE which are supplied from the pad P13 and the external terminal OEB, that is, the pad P29 via the pad switching circuit PS. Internal control signals are selectively formed and supplied to each part of the dynamic RAM.

The pad switching circuit PS has a switching control signal PS supplied via the bonding pad PPS.
According to C, the substantial functions of the total 18 pairs of bonding pads P2 and P41 to P20 and P23, that is, the logic signals input or output through these bonding pads are exchanged with each other, and are connected to each part of the dynamic RAM. introduce. The switching control signal PS
C is selectively set to a high level or a low level by coupling the bonding pad PPS to a bus bar lead for supplying a power supply voltage or a ground potential. Regarding the specific configuration and operation of the pad switching circuit PS,
It will be described in detail later.

By the way, the dynamic type R of this embodiment
AM is a power supply voltage VCC of 0V and a positive potential such as + 5V
That is, the ground potential VSS is used as the operating power supply. Of these, the power supply voltage VCC is three power supply voltage supply terminals VC
Dynamic type RA via bonding pads PVC1 to PVC4 for supplying four power supply voltages from C1 to VCC3
The ground potential VSS is supplied to each circuit of M and is supplied to each circuit of the dynamic RAM from three ground potential supply terminals VSS1 to VSS3 through four ground potential supply bonding pads PVS1 to PVS4.

On the other hand, the dynamic RAM of this embodiment
Is a LOC package, and is provided between the three power supply voltage supply terminals VCC1 to VCC3 and the four power supply voltage supply bonding pads PVC1 to PVC4 and 3
The coupling between the ground potential supply terminals VSS1 to VSS3 and the four ground potential supply bonding pads PVS1 to PVS4 is performed by a power supply voltage supply bus bar lead BBC or a ground potential supply bus bar lead BB made of a metal wiring layer.
Via S. Further, a power supply voltage VCCA obtained through the power supply voltage supply bonding pad PVC1, a ground potential VSSA obtained through the ground potential supply bonding pad PVS1, and a power supply voltage VCCB obtained through the power supply voltage supply bonding pad PVC2. Ground potential VSSB obtained through the ground potential supply bonding pad PVS2, power supply voltage VCCC obtained through the power supply voltage supply bonding pad PVC3, and ground potential VSSC and power supply voltage obtained through the ground potential supply bonding pad PVS3 The power supply voltage VCCD obtained through the supply bonding pad PVC4 and the ground potential VSSD obtained through the ground potential supply bonding pad PVS4 are dynamic R respectively.
It is supplied as a dedicated power source to the circuit corresponding to the AM. As a result, the supply paths of the power supply voltage VCC and the ground potential VSS are separated for each application, that is, for each circuit, and
The impedance of the power supply voltage or the ground potential supply path is reduced, the power supply noise is suppressed, and the operation of the dynamic RAM is stabilized. The specific pad arrangement of the dynamic RAM and its connection form will be described later in detail.

FIG. 2 is a board layout diagram of one embodiment of the dynamic RAM shown in FIG. Based on the figure,
An outline of the substrate layout of the dynamic RAM of this embodiment will be described. In the description below, the positional relationship shown in FIG.

In FIG. 2, the sense amplifier SA that constitutes the dynamic RAM is eight sense amplifiers SA0.
To SA7, and the memory array MARY also has eight pairs of memory array MARY corresponding to these sense amplifiers.
00 and MARY01 to MARY70 and MARY
It is divided into 71. Of these, four pairs of memory arrays MA
RY00 and MARY01, MARY20 and MARY
21, MARY40 and MARY41 and MARY
60 and MARY 61 are so-called laterally stacked on the left side of the vertical center line of the semiconductor substrate surface with their word lines oriented in the horizontal direction in the figure, and a corresponding sense amplifier SA0, SA2, SA4 and SA6 are arranged respectively. Similarly, the remaining four pairs of memory arrays MARY10 and MARY11, MARY30 and MA
RY31, MARY50 and MARY51 and MA
RY70 and MARY71 are also arranged side by side on the right side of the semiconductor substrate surface, and corresponding sense amplifiers SA1, SA3, SA5 and SA7 are arranged between the memory arrays of each pair. As a result, the dynamic RA
M will adopt the so-called shared sense method,
The sense amplifiers SA0 to SA7 correspond to a pair of corresponding memory arrays MARY00 and MARY01 to MARY7.
0 and MARY 71 respectively.

Memory arrays MARY21 and MARY4
Between 0 and MARY31 and MARY50,
A Y address decoder YD is formed by dividing the Y address decoder YD into two along the center line on the side of the semiconductor substrate.
0 and YD1 are arranged respectively. Among them, the Y address decoder YD0 is composed of four sense amplifiers SA0, SA2, SA4 and SA arranged on the left side of the semiconductor substrate surface.
6, the Y address decoder YD1 includes four sense amplifiers SA arranged on the right side of the semiconductor substrate surface.
1, SA3, SA5 and SA7.

On the other hand, inside the two memory arrays MARY00 and MARY10 to MARY61 and MARY71 sandwiching the vertical center line of the semiconductor substrate surface, X address decoders XD00 and XD10 are formed by dividing the X address decoder XD into 16 parts. To XD61 and XD7
1 is arranged in each of which the word line drive circuit WD is divided into 16 word line drive circuits WD.
00 and WD10 to WD61 and WD71, respectively.

In this embodiment, the dynamic RA
M is a LOC package, and word line drive circuit W
Further inside D00 and WD10 to WD61 and WD71, along the vertical center line of the semiconductor substrate SUB,
A large number of bonding pads are arranged. Among them, the pad PPS to which the switching control signal PSC is input, the power supply voltage supply pads PVC1 to PVC4, and the ground potential supply pads PVS1 to PVS4, that is, the second pads are arranged in a line on the center line of the semiconductor substrate SUB. , The other pads P2 to P41, that is, the first pads are arranged in two staggered patterns with the center line of the semiconductor substrate SUB in between. As will be described later, on both sides of these pads, a predetermined insulating adhesive film is sandwiched, and a power supply voltage supply bus bar lead BBC and a ground potential supply bus bar lead B are provided.
The BS and the signal leads are extended, and the bonding process is performed in a predetermined combination.

FIG. 3 is a partial sectional structural view of an embodiment of the package and mounting board of the dynamic RAM shown in FIG. Further, FIG. 4 shows a terminal layout diagram of one embodiment of the surface mount package of the dynamic RAM of FIG. 1, and FIG. 5 shows a terminal layout diagram of one embodiment of the back mount package of the dynamic RAM. Has been done. Based on these figures, the package structure, the terminal arrangement, and the features of the dynamic RAM of this embodiment will be described.
In addition, in the following description, the upper and lower sides and the left and right sides of the package and the mounting board are represented with the positional relationship of FIGS.

In FIG. 3, the dynamic RAM of this embodiment adopts the LOC package form as described above, and its package structure is so-called TSOP package structure, which is mounted on both sides of the mounting board BD. . Therefore, in the surface mounting package PKGF mounted on the surface side of the mounting board BD, the chip CHP
The lead frame LFF extended to the front surface of F is bent downward to the outside of the package, that is, bent to the mounting board BD side to serve as an external terminal. However, in the back surface mounting package PKGB mounted on the back surface side of the mounting board BD, the chip CH
The lead frame LFB extended to the surface of the PB is bent upward on the outside of the package, that is, on the mounting board BD side to serve as an external terminal. Printed wirings PWF and PWB having a predetermined film are formed on the front surface and the back surface of the mounting board BD, and through wirings for connecting the corresponding external terminals of the surface mounting package PKGF and the back surface mounting package PKGB inside thereof. TW1 and TW2 are formed.

By the way, the surface mount package PKGF
As shown in FIG. 4, a total of 42 external terminals are provided, 21 on each of the left side and the right side of the package. Of these, the three external terminals T1 and T6 and T21 provided on the left side are the external terminals VCC1 and VCC for power supply voltage supply for supplying the power supply voltage VCC.
2 and VCC3, and the three right external terminals T4
2 and T37 and T22 are ground potential supply external terminals VSS1 and VSS for supplying the ground potential VSS.
2 and VSS3. In addition, a total of 18 left and right external terminals T2 to T5, T7 to T11, T32
To T36 and T38 to T41 are external terminals D0 to D17 for data input / output and a total of 11 external terminals T.
15 to T20 and T23 to T27 are external terminals A0 to A10 for address input. The left external terminals T13 and T14 are used as activation control signal input external terminals WEB and RASB for inputting the write enable signal WEB and the row address strobe signal RAS, respectively, and the left external terminals T29 and T30.
And T31 are output enable signal OEB and column address strobe signals UCASB and LC, respectively.
External terminal O for starting control signal input for inputting ASB
EB and UCASB and LCASB. The external terminals T12 and T28 are unconnected terminals NC that are not used together.

On the other hand, the backside mounting package PKGB is
As shown in FIG. 5, 21 pieces are provided on each of the left side and the right side of the package, and the surface mounting package P is provided.
The KGF has a total of 42 external terminals which are allotted symmetrically with respect to the center line of the package. Of these, three external terminals T42, T37 and T22 provided on the right side are external terminals VCC1 and VCC2 for supplying power supply voltage and VCC3 for supplying power supply voltage VCC.
And three external terminals T1 and T6 on the left side and T
Reference numeral 21 is used as ground potential supply external terminals VSS1 and VSS2 and VSS3 for supplying the ground potential VSS. In addition, the right and left 18 external terminals T41 to
T38, T36 to T32, T11 to T7 and T5
T2 is used as external terminals for data input / output D0 to D17,
Eleven external terminals T28 to T23 and T20 to T1
Reference numeral 6 designates address input external terminals A0 to A10.
The right external terminals T30 and T29 are used as activation control signal input external terminals WEB and RASB for inputting the write enable signal WEB and the row address strobe signal RAS, respectively, and the right external terminal T1.
4 and T13 and T12 are the output enable signal OEB and the column address strobe signal U, respectively.
External terminal OEB for starting control signal and UCASB and LCAS for inputting CASB and LCASB
B. The external terminals T15 and T31 are non-connection terminals NC that are not used.

From these facts, the backside mounting package PKGB has a pin arrangement symmetrical to that of the frontside mounting package PKGF without reverse bending of its lead frame, that is, the external terminals. As shown, by arranging these packages at the corresponding positions on the front surface and the back surface of the mounting board BD, each external terminal can be associated with each function. As a result, the mounting density of the dynamic RAM on the mounting board BD can be increased, and the mounting efficiency of the storage device including the dynamic RAM can be increased.

FIG. 6 shows a pad connection diagram of one embodiment of the surface mounting package PKGF of the dynamic RAM of FIG. 1, and FIG. 7 shows its back mounting package PKGF.
A pad connection diagram for one embodiment of GB is shown. Also,
FIG. 8 shows a partial circuit diagram of an embodiment of the pad switching circuit PS included in the dynamic RAM of FIG. 1, and FIG. 9 shows an embodiment of the surface mounting package and the back mounting package. The signal path diagram of is shown. Based on these figures, the pad connection form, the pad switching method, the signal path and the features of the surface mounting package and the back surface mounting package of the dynamic RAM of this embodiment will be described.

In FIG. 6, the dynamic RAM of this embodiment adopts the LOC package form as described above, and in the central portion of the chip CHPF of the surface mounting package PKGF, the vertical center line of the semiconductor substrate surface is formed. 4 along
Five bonding pads are arranged. Of these, 9
Individual pads PPS, PVC1 to PVC4 and PVS
1 to PVS4 are arranged on the vertical center line of the semiconductor substrate surface, and the remaining 36 pads P2 to P41 are arranged in two rows in a zigzag pattern across the vertical center line of the semiconductor substrate surface. A power supply voltage supply busbar lead BBC made of a metal wiring layer such as aluminum is arranged on the left side of these pad rows, and a ground potential supply busbar lead BBS also made of a metal wiring layer is arranged on the right side thereof. .

The bus bar lead BBC for power supply voltage supply is
External terminals T1 and T6 and T21 on the left side
That is, the power supply voltage supply external terminals VCC1 and VCC2
And the power supply voltage supply pads PVC1 to PVC4 which are coupled to VCC3 and have the shortest distances.
Bonded to. Similarly, the ground potential supply bus bar lead BBS is coupled to the external terminals T42 and T37 and T22 on the right side thereof, that is, the ground potential supply external terminals VSS1 and VSS2 and VSS3, and has the shortest distance to the ground potential supply pads. Bonded to PVS1 to PVS4. As a result, impedance in the power supply voltage and ground potential supply paths is reduced, power supply noise is suppressed, the operation of the dynamic RAM is stabilized, and the pad layout for power supply voltage supply and ground potential supply pads is free. This will increase the package's capability and capacity. The power supply voltage supply bus bar lead BBC and the ground potential supply bus bar lead BBS are bonded to the chip CHPF via an insulating adhesive film (not shown).

Eighteen leads corresponding to the external terminals T2 to T20 are extended to the left of the power supply voltage supply bus bar lead BBC, and corresponding bonding pads P2 to P2.
Bonded to 0 respectively. Similarly, the external terminal T23 is provided on the right side of the ground potential supply bus bar lead BBS.
18 leads corresponding to ~ T41 are extended and bonded to corresponding bonding P23 to P41, respectively. In this surface mounting package PKGF,
Pad PPS for inputting the switching control signal PSC
Is coupled to the ground potential supplying bus bar lead BBS.

On the other hand, the chip CHPB of the back surface mounting package PKGB has the same structure as the front surface mounting package PKGF as shown in FIG. 7, and is arranged in a row or two along the vertical center line of the semiconductor substrate surface. 45 in total
Although the bonding pad is provided, the power supply voltage supply bus bar lead BBC is arranged on the right side of these pad rows, and the ground potential supply bus bar lead BBS is arranged on the left side of the pad row. Busbar lead B for power supply voltage supply
BC has external terminals T42 and T37 and T22 on the right side thereof, that is, an external terminal VCC1 for supplying a power supply voltage.
And coupled to VCC2 and VCC3,
Each power supply voltage supply pad PVC with the shortest distance
1 to PVC4 are bonded. The ground potential supply bus bar lead BBS is coupled to the external terminals T1 and T6 and T21 on the left side thereof, that is, the ground potential supply external terminals VSS1 and VSS2 and VSS3, and has the shortest distance to the ground potential supply pad PVS1. ~ Bonded to PVS4.

Eighteen leads corresponding to the external terminals T23 to T41 are extended to the right of the power supply voltage supply bus bar lead BBC, and the corresponding bonding P23 to P41 is performed.
Respectively bonded to. Similarly, the external terminals T2 to T are provided on the left side of the ground potential supply bus bar lead BBS.
Eighteen leads corresponding to 20 are extended and bonded to corresponding bondings P2 to P20, respectively. In this back side mounting package PKGB, the pad PPS for inputting the switching control signal PSC is coupled to the power supply voltage supply bus bar lead BBC.

By the way, the dynamic type R of this embodiment
As described above, the AM includes the pad switching circuit PS, and the pad switching circuit PS has a switching control signal P.
The pad PPS for inputting SC is coupled to the ground potential supply bus bar lead BBS in the surface mounting package PKGF, and is coupled to the power supply voltage supply bus bar lead BBC in the back surface mounting package PKGB.

In this embodiment, the pad switching circuit PS is not particularly limited, but as shown in FIG.
18 pairs of external terminals T2 and T41, T3 and T40, T4 and T3 symmetrically arranged on the left and right sides of the package
9 to T20 and T23, that is, 18 pairs of pads P2 and P41, P3 and P40, P4 and P39 and P symmetrically arranged with respect to the vertical center line of the semiconductor substrate surface.
20 and P23, each of which includes 18 unit pad switching circuits SC1 to SC18. Each of these unit pad switching circuits is, as represented by the unit pad switching circuit SC1 in FIG. 4 consisting of P-channel and N-channel MOSFETs
The number of complementary gates G1 to G4 is included.

Of these, one of the complementary gates G1 and G4 forming each unit pad switching circuit is coupled to the corresponding left external terminal T2, T3, T4 to T20, that is, the bonding pad P2, P3, P4 to P20, respectively. , One of the complementary gates G2 and G3 is coupled to the corresponding right external terminal T41, T40, T39 to T23, that is, the bonding pad P41, P40, P39 to P23, respectively. The other of the complementary gates G1 and G2 has the other internal signal lines D0, D1, D2.
Through A5 and complementary gates G3 and G, respectively.
The other of 4 corresponds to the corresponding internal signal lines D17, D16, D1.
5 to A6, respectively. The switching control signal PSC is commonly supplied to the gates of the P-channel MOSFETs forming the complementary gates G1 and G3 and the N-channel MOSFETs forming the complementary gates G2 and G4 of each unit pad switching circuit, and the complementary gates G1 and G3 are connected to each other. Comprising N-channel MOSFET and P-channel MOSF composing complementary gates G2 and G4
An inverted signal by the inverter V1, that is, an inverted switching control signal PSCB is commonly supplied to the gate of ET.

As described above, the surface mounting package PK
The pad PPS of GF is bonded to the ground potential supply bus bar lead BBS. Therefore, the switching control signal PSC is at a low level like the ground potential VSS, and the inverted switching control signal PSCB is the power supply voltage VCC.
It is a high level like. Therefore, in the pad switching circuit PS of the surface mounting package PKGF, the complementary gate G of the unit pad switching circuits SC1 to SC18 is used.
1 and G3 are in a transmission state all at once, and complementary gates G2 and G4 are in a non-transmission state. As a result, as shown in FIG. 9, the input / output data D for the dynamic RAM
0 to D17 are corresponding external terminals T2 to T5 and T7 to T
11, T32 to T36 and T38 to T41 respectively transmitted via pads P2 to P5, P7 to P11, P32 to P36 and P38 to P41, and corresponding unit pad switching circuits SC1 to SC9 of the pad switching circuit PS. Becomes Further, the address signal A0
To A10 are corresponding external terminals T15 to T20 and T23 to T27 to pads P15 to P20 and P2.
3 to P27, and further transmitted via the corresponding unit pad switching circuits SC13 to SC18 of the pad switching circuit PS, respectively, and the row address strobe signal RAS is transmitted.
B, column address strobe signal UCASB and LC
ASB, write enable signal WEB, and output enable signal OEB correspond to corresponding external terminals T14, T30.
And T31, T13 and T29 to pads P14,
It is transmitted via P30 and P31, P13 and P29, respectively.

On the other hand, the pad PPS of the back surface mounting package PKGB is bonded to the power supply voltage supply bus bar lead BBC as described above. Therefore, the switching control signal PSC is at a high level like the power supply voltage VCC, and the inverted switching control signal PSCB is at a low level like the ground potential VSS. Therefore, in the pad switching circuit PS of the backside mounting package PKGB, the complementary gates G1 and G3 of the unit pad switching circuits SC1 to SC18 are in the non-transmission state, and instead, the complementary gates G2 and G4 are in the transmission state at the same time. As a result,
As shown in FIG. 9, the input / output data D0 to D17 are
Corresponding external terminals T41 to T38, T36 to T32, T
11-T7 and T5-T2 to pads P41-P3
8, P36 to P32, P11 to P7 and P5 to P2
Further, the data is transmitted via the corresponding unit pad switching circuits SC1 to SC9 of the pad switching circuit PS. Further, the address signals A0 to A10 correspond to the corresponding external terminals T28 to T23 and T20 to T16.
From the pads P28 to P23 and P20 to P16 and the corresponding unit pad switching circuits SC13 to SC18 of the pad switching circuit PS, respectively, and are transmitted to the row address strobe signals RASB, the column address strobe signals UCASB and LCASB, and the write enable signal WEB. And output enable signal OE
B is the corresponding external terminal T29, T13 and T12, T
30 and T14 to pads P29, P13 and P1
2, P30 and P14 respectively.

That is, the dynamic RA of this embodiment
In M, by selectively bonding the pad PPS to the ground potential supply bus bar lead BBS or the power supply voltage supply bus bar lead BBC, data input / output, address input, and start control signal input provided on the left side of the package. External terminals T2 to T21, that is, the pad P
2 to P21 and the substantial functions of the external terminals T41 to T23 for data input / output, address input and start control signal input, that is, the pads P41 to P23 provided on the right side of the package. It is possible to realize the surface mounting package PKGF and the back surface mounting package PKGB having symmetrical pin arrangements without reverse bending of the lead frame, that is, the external terminals.

As is apparent from FIG. 9, the external terminals T2 to T21 and T41 to T23 and the pads P2 to P are provided.
21 and the bonding between P41 and P23,
The same combination is applied to the surface mounting package PKGF and the back surface mounting package PKGB. Therefore, the bonding wires connecting these external terminals and pads do not cross each other, and the problem that the pads P2 to P21 and P41 to P23 are arranged in two rows does not occur. On the other hand, the power supply voltage supply busbar lead BBC and the ground potential supply busbar lead BBS have their arrangement positions interchanged in the surface mounting package PKGF and the back surface mounting package PKGB, but the power supply voltage supply pads PVC1 to PVC4 and the ground potential. Since the supply pads PVS1 to PVS4 are arranged in one row along the vertical center line of the semiconductor substrate surface, the bonding wires do not intersect with each other. As a result, in the dynamic RAM of this embodiment, it is possible to realize a symmetrical pin arrangement with most pads arranged in two rows, which solves the constraint imposed by the symmetrical pin arrangement on the number of external terminals. Therefore, the capacity of the dynamic RAM can be promoted.

As shown in the above embodiment, the present invention adopts the LOC package form dynamic RAM.
The following operational effects can be obtained by applying the present invention to a semiconductor device such as. That is, (1) Dynamic RA that takes the form of LOC package
In M or the like, the first pads including the data input / output pads are arranged in two rows in a staggered manner along the center line of the semiconductor substrate surface, and the second pads including the power supply voltage supply pads and the ground potential supply pads are arranged. By arranging one row along the center line and providing a pad switching circuit that selectively exchanges the substantial functions of the pair of first pads according to a predetermined switching control signal, a power supply voltage supply and a ground potential supply are provided. For the second pad including the data pad and arranged in one row, the symmetry of the external terminal is ensured by replacing the bonding, and for the first pad including the data input / output pad and arranged in two rows, The effect that the substantial functions of the pads can be exchanged without changing the bonding and the symmetry of the external terminals can be ensured is obtained.

(2) According to the above item (1), the symmetrical arrangement of the external terminals of the dynamic RAM or the like can be realized without changing the bonding, that is, without restricting the number of bonding pads. To be (3) According to the above items (1) and (2), it is possible to increase the mounting capacity of a storage device or the like while increasing the capacity of a dynamic RAM having a LOC package form and ensuring its reliability. The effect is obtained.

Although the invention made by the present inventor has been concretely described based on the embodiments, the invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the dynamic RAM can have an arbitrary bit configuration and word configuration such as so-called x1 bit or x8 bit configuration. Further, the data input / output terminals D0 to D17 can be dedicated as the data input terminal and the data output terminal, and the address input terminal does not need to be a so-called address multiplex system. Switching control signal PS to the pad switching circuit PS
The pad PPS for inputting C may be coupled to a predetermined external terminal. Further, the number of external terminals and bonding pads for supplying the power supply voltage or for supplying the ground potential is not restricted by this embodiment. Further, in this example,
Pad PPS for inputting the switching control signal PSC
All the signal input or output pads except the power supply voltage supply pad and the ground potential supply pad are arranged in two columns, but for example, only the data input / output pads are arranged in two columns and other signal input or output pads are arranged. May be arranged in one row. The memory array MARY may include redundant word lines and redundant complementary bit lines. The dynamic RAM can have an arbitrary block configuration, and its storage capacity, combination of activation control signals, and the like can adopt various embodiments.

In FIG. 2, the memory array and its peripheral circuits can be divided into any number, and it is not essential to adopt the shared sense method. Further, the dynamic RAM can adopt a so-called vertical stacking arrangement in which the word lines of each memory array are extended in the vertical direction of the semiconductor substrate surface, and it is not essential to adopt the LOC package form. The first pads, including the data input / output pads, may not be in a staggered pattern, but may be arranged in two complete rows. 3 to 7 and 9, the dynamic RAM can include an arbitrary number of external terminals and pads, and its package structure can be a package structure other than TSOP. In FIG. 8, the unit pad switching circuit SC1 of the pad switching circuit PS
A part of each of SC18 to SC18 can be configured by a clocked inverter, or can be configured by an element other than MOSFET. Furthermore, dynamic RA
Various embodiments can be adopted for the specific layout of M, the shapes of the semiconductor substrate, the pads and the lead frame, the circuit configuration of the pad switching circuit PS, and the like.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM which is the field of application which is the background of the invention has been described.
The present invention is not limited to this, and can be applied to various memory integrated circuit devices such as static RAMs and logic integrated circuit devices such as single-chip microcomputers. The present invention can be widely applied to a semiconductor device including at least a plurality of bonding pads and requiring symmetrical arrangement of external terminals.

[0057]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like that adopts the LOC package form, the first pads including the data input / output pads are arranged in two rows in a staggered manner along the center line of the semiconductor substrate surface to supply the power supply voltage and the ground potential. Pad switching circuit for arranging a second pad including a pad for a row along the center line of the semiconductor substrate surface and selectively switching the substantial function of the pair of first pads in accordance with a predetermined switching control signal By providing a pad for power supply voltage supply and a pad for ground potential supply and arranged in one row, the symmetry of the external terminals is secured by replacing the bonding, and the pad for data input / output is provided. For the first pad which is included and arranged in two rows, the substantial function of the pad is replaced without replacing the bonding, and It is possible to ensure the symmetry of the child. As a result, the external terminals can be symmetrically arranged without changing the bonding, that is, without restricting the number of bonding pads. Therefore, it is possible to increase the capacity of a dynamic RAM in the LOC package form and ensure its reliability. At the same time, the mounting efficiency of the storage device and the like can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a substrate layout view showing an embodiment of the dynamic RAM of FIG.

FIG. 3 is a partial cross-sectional structural view showing an embodiment of the package and mounting board of the dynamic RAM of FIG.

FIG. 4 is a terminal layout diagram showing an embodiment of a surface mounting package of the dynamic RAM of FIG.

5 is a terminal layout diagram showing one embodiment of a backside mounting package of the dynamic RAM of FIG.

6 is a pad connection diagram showing an embodiment of a surface mounting package of the dynamic RAM of FIG.

FIG. 7 is a pad connection diagram showing an example of a backside mounting package of the dynamic RAM of FIG.

8 is a partial circuit diagram showing an embodiment of a pad switching circuit included in the dynamic RAM of FIG.

FIG. 9 is a signal path diagram showing an embodiment of the surface mounting package and the back mounting package of the dynamic RAM of FIG.

[Explanation of symbols]

MARY, MARY00 to MARY71 ... Memory array, WD, WD00 to WD71 ... Word line drive circuit, XD, XD00 to XD71 ... X address decoder, XB ... X address buffer, SA, SA0-S
A7 ... Sense amplifier, YD, YD0 to YD1 ...
Y address decoder, YB ... Y address buffer,
IO ... Data input / output circuit, TG ... Timing generation circuit, PS ... Pad switching circuit. SUB ...
Semiconductor substrate, P2-P41, PPS, PVC1-PVC
4, PVS1 to PVS4 ... Bonding pads. B
D ... Mounting board, PKGF ... Surface mounting package, PKGB ... Back mounting package, CHP
F, CHPB ... Chip, LFF, LFB ... Lead frame, PWF, PWB ... Printed wiring, TW
1-TW2 ... Penetration wiring. T1 to T42 ... External terminals. BBC: Busbar lead for power supply voltage supply, BB
S ... Busbar lead for supplying ground potential. SC1-SC
18 ... Unit pad switching circuit, G1 to G4 ...
Complementary gate, V1 ... Inverter.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 21/822 21/8242 27/108 H01L 27/10 325 T (72) Inventor Yasuhiro Kasama Tokyo, Kodaira City 5-20-1 Mizumotocho, Ltd. Semiconductor Company, Hitachi, Ltd. (72) Inventor Hiroshi Yoshida 5-2-1, Kamisuihoncho, Kodaira-shi, Tokyo Hirate Super LSI Engineering Co., Ltd.

Claims (4)

[Claims] 1. A plurality of first pads arranged substantially in two columns, and a pad switching circuit for selectively exchanging substantial functions of the first pads forming a pair according to a predetermined switching control signal. A semiconductor device comprising. 2. The semiconductor device is in the form of an LOC package, and the plurality of first pads are arranged in a zigzag pattern along a center line of a semiconductor substrate surface. The semiconductor device according to claim 1. 3. The semiconductor device is a dynamic RAM having a plurality of data input / output terminals.
Pad includes a plurality of data input / output pads provided corresponding to the data input / output terminals, and the semiconductor device includes a power supply voltage supply pad and a ground potential supply pad. 3. The semiconductor device according to claim 1 or 2, further comprising a plurality of second pads arranged in a line along the center line of. 4. The package of the semiconductor device is mounted on a front surface and a back surface of a mounting board, and external terminals of the package arranged at the same positions on the front surface and the back surface of the mounting board have their center lines separated from each other. And the switching control signal is selectively set to a high level when the package of the semiconductor device is mounted on the back surface of the mounting board. The semiconductor device according to claim 1, claim 2, or claim 3.