JPH03176892A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To accelerate an operation by arranging a latch circuit, an X/Y decoder circuit in an area between a logic circuit and a memory cell array part from a logic circuit side. CONSTITUTION:An input/output circuit 2 is arranged in the peripheral part of a semiconductor substrate 1, and the logic circuit 3 is arranged in the center part in the upward/downward direction of the semiconductor substrate 1. And the latch circuit 7, the X/Y decoder circuit 8 are arranged in the area between the logic circuit 3 and the memory cell array part 5 from the logic circuit 3 side, respectively. Therefore, since distance between the latch circuit 7 and the X decoder 8 can be reduced, wiring length between them can be reduced, which reduces the transmission delay of a signal on the wiring of the address signal of an X system. In such a way, the operation can be accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device including a logic circuit and a memory.

[Conventional technology]

Large and ultra-large supercomputers are CPUs (Cen
A cache memory (buffer memory) is interposed between the main memory device and the main memory device. Since the main memory device requires a large amount of storage capacity, it is composed of, for example, a DRAM.

The cache memory reads predetermined information from among the information in the main memory device, and inputs and outputs the read information to and from the CPU. Further, this cache memory outputs information that has been input/output to/from the previous HHc PU to the main memory device. In other words, each of the cache memory and main memory device is
Seen from the CPU, it functions as one storage device, and constitutes a storage device with a hierarchical structure.

The cache memory is composed of, for example, an SRAM whose operation speed is faster than that of the DRAM constituting the main memory device, and a logic circuit (gate array section). S
Compared to DRAM, RAM has a faster operating speed corresponding to the refresh cycle of DRAM. The logic circuit receives a logical address (for example, 32
[bitl] into a physical address (for example, 24 [bit]) used in the SRAM.

In this way, by providing a cache memory between the CPU and the main memory device, a supercomputer can secure a large storage capacity with the main memory, and also increase the operating speed with the cache memory. Therefore, as a whole, large-capacity and high-speed arithmetic processing is possible.

Next, the configuration of the cache memory will be specifically explained.

The cache memory is composed of a rectangular semiconductor substrate made of single crystal silicon. At the periphery of this semiconductor substrate,
Input/output circuits are arranged. Further, a bonding pad is arranged near the area where this input/output circuit is arranged.

The logic circuit is arranged at the center of the semiconductor substrate within a region defined by the input/output circuit.

The SRAM is divided into a plurality of blocks (RAM macrocells). This divided block includes an input/output circuit arranged along one side of the rectangular semiconductor substrate, an input/output circuit arranged along the other opposing side, and the logic circuit. It is located in the area between.

Each of the divided blocks of the SRAM is mainly composed of an input latch circuit, a decoder circuit, a memory cell array section, and a sense amplifier.

The SRAM is divided into, for example, four blocks, and arranged along the logic circuit on one side and the other side opposite to the logic circuit. Each of these four divided blocks is an input latch circuit from the logic circuit side.

It is configured by arranging a Y decoder circuit, a sense amplifier, and a memory cell array section.

The memory cell array portion of the block divided into four is divided into two within this block. In other words,
The memory cell array section of the SRAM mounted on the cache memory is divided into eight parts. Between the two divided memory cell array parts in the block,
An X decoder circuit and a driver circuit are respectively arranged.

Each of the eight divided memory cell array sections includes:
A plurality of memory cells storing 1 [bit] of information are arranged in a matrix. This memory cell is arranged at the intersection of a complementary data line and a word line extending through the memory cell array section.

Regarding this type of technology, for example, I.E.
E., International Solid State Circuits Conference (1,989), pp. 26-27 and 278 (IEEE, International
onal 5 solid-state C1rcuj,t
s Conference.

(1989), pp26-27. ρρ278).

C Problems to be Solved by the Invention] However, as a result of studying the above-mentioned prior art, the inventor found the following problems.

In the cache memory described above, the X-system address signal input to the input latch circuit is transmitted from the input latch circuit along the memory cell array section toward the - side or another side opposite thereto. Since it is transmitted to the X decoder circuit, from the input latch circuit,
There is a problem in that a signal transmission delay occurs corresponding to the transmission of the X-system address signal to the X decoder circuit, and the operation speed decreases.

An object of the present invention is to provide a technique that can increase the operating speed of a semiconductor integrated circuit device equipped with a memory and a logic circuit.

6- Another object of the present invention is to provide a technique that enables high integration in a semiconductor integrated circuit device equipped with the memory and logic circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) In a semiconductor integrated circuit device in which an address signal is input from a logic circuit to a decoder circuit via a latch circuit, and a predetermined memory cell in a memory cell array section is selected based on the address signal, the logic circuit and the memory cell array A latch circuit and an X/Y decoder circuit are respectively arranged from the logic circuit side in the area between the logic circuit and the logic circuit.

(2) In a semiconductor integrated circuit device in which an address signal is inputted from a logic circuit to a decoder circuit via a latch circuit, and a memory cell in a predetermined memory cell array section from among a plurality of memory cells is selected based on the address signal, the logic arranging the plurality of memory cell array sections along the outer periphery of the circuit;
A dedicated logic circuit for calculating information read from the memory cell array is arranged in a region between each of the memory cell array sections, and a logic circuit on the logic circuit side is arranged in a region between the memory cell array and the logic circuit. From the latch circuit.

Each of the X/Y decoder circuits is arranged.

C effect] According to the above-mentioned means (1), the distance between the latch circuit and the Delay is reduced. Thereby, the operating speed of the semiconductor integrated circuit device can be increased.

According to the above-mentioned means (2), the dedicated logic circuit that calculates the output from the memory cell array section can be arranged independently in a region different from the logic circuit, and the dedicated logic circuit can be optimized. It is possible to reduce the area occupied by the circuit and achieve a high density ratio of the semiconductor integrated circuit device.

At the same time, the length of the wiring between the memory cell array section and the dedicated logic circuit is shortened, so the signal transmission delay of the wiring is reduced, and the operating speed of the semiconductor integrated circuit device can be increased.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

In all the figures for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

A semiconductor integrated circuit device (cache memory) including an SRAM and a logic circuit, which is an embodiment of the present invention, is shown in FIG.
This will be explained using a circuit block diagram showing an outline of the overall configuration. This semiconductor integrated circuit device is a computer CPU.
and the main memory device, and is used as a cache memory.

As shown in FIG. 1, the semiconductor integrated circuit device is composed of a rectangular semiconductor substrate 1. As shown in FIG. This semiconductor substrate 1
is made of, for example, single crystal silicon.

An input/output circuit 2 is arranged around the semiconductor substrate 1 . Further, a plurality of bonding pads (not shown) are arranged near the area where the input/output circuit 2 is arranged. The semiconductor integrated circuit device inputs and outputs information to and from the main memory device or CPU via the input/output circuit 2 and the bonding pads.

In the case of this embodiment, the input/output circuit 2 is connected to an ECL external to the semiconductor integrated circuit device (CPU and main memory device).
Since we are assuming a case of (multiple logic) configuration, the external ECL circuit and the CMO8 (which constitutes the internal SRAM and logic circuit (3)) are assumed.
Performs level conversion with the complementary MISFET) circuit.

Within the area defined around the input/output circuit 2,
A logic circuit (
A gate array section) 3 is arranged. This logic circuit 3
The logical address (for example, 32 [bit]) input from the CPU via the input/output circuit 2 is sent to the SRA.
The address signal in M is converted into a physical address (for example, 24 [bitl)].

In the area defined around the logic circuit 3 and the input/output circuit 2, a RAM block (R
AM macrocell) 4 is arranged. This RAM block 4 has 2 bits that can be read simultaneously.
kW] X 24 [bitl] Two-sided configuration. This RAM block 4 mainly includes an input latch circuit 7,
It is composed of a decoder circuit 8, a memory cell array section 5, a sense amplifier (13), and a level conversion circuit (!4). Further, this RAM block 4 is provided with a dedicated logic circuit (15, 16) for calculating information read out from the memory cell array section 5. Each of the RAM blocks 4 is configured with mirror symmetry with the logic circuit 5lt3 as an axis of symmetry.

The RAM block 4 is divided above and below the logic circuit 3, and is further divided horizontally in each of the two lower regions. In other words, the RAM block 4 has 4
It is divided. One of the four divided RAM blocks 4 is shown surrounded by a two-dot chain line in FIG.

Each of the four divided RAM blocks 4 is constructed by arranging an input latch circuit 7, a decoder circuit 8, and a memory cell array section 5 from the logic circuit 3 side. Each of the input latch circuit 7 and the decoder circuit 8
Each of the divided R and AM blocks 4 is divided into two from the center in the left and right direction. This manual latch circuit 7 has a RAM block 4 of 2 [kW]
X 24 [1 converted into a physical address by the logic circuit 3 due to the two-sided configuration of the bit],
[bit] address signal is input manually. The input latch circuit 7 temporarily holds this input address signal, holds all of ]1-[bj tl, and then outputs the address signal of all 11 [bitl to the decoder circuit 8 based on the clock signal. do.

In the RAM block 4, the input latch circuit 7
, the area where the decoder circuit 8 is provided and this RAM
The memory 1-2-recell array section 5 is arranged along the logic circuit 3 in an area other than the center portion in the left and right direction of the block 4. In other words, this memory cell array section 5 has two memory cells in each RAM block 4.
In the entire SRAM, the memory cell array section 5 is divided into eight parts and arranged.

In the central part of the RAM block 4, that is, in the area between the memory cell array parts 5, the sense amplifier (
), level conversion circuit (14), dedicated logic circuit (15,1
6) are provided. Each of the memory cell array sections 5 adjacent to each other with this region 6 in between is
It is configured with mirror symmetry with the region 6 as the axis of symmetry.

Next, the detailed configuration of the RAM block 4 is shown in FIG.
The explanation will be made using FIG. 1 (a diagram showing an enlarged view of the area surrounded by the dashed line in FIG. 1). In FIG. 2, the dashed line A-A is RA
It shows the center of the M block 4 in the left and right direction.

As shown in FIG. 2, in each RAM block 4, each of the two divided memory cell array sections 5 has a word line WL extending in the vertical direction, and a complementary data line DL extending in the horizontal direction. and DL extend. In this memory cell array section 5, memory cells 9 are arranged in rows and columns. The configuration of this memory cell 9 is shown in FIG. 3 (equivalent circuit diagram).

As shown in FIG. 3, the memory cell 9 is arranged at the intersection of the complementary data lines DL, DL and the word line WL. The memory cell 9 is composed of a flip-flop circuit used as an information storage section (having a charge node) and two transfer MISFETs Qs and QS2. The flip-flop circuit consists of two driving M,
It consists of 15FETs Qd□ and Qd2, and two resistance elements R and R2. In other words, the memory cell 9 has M
, and TSFETs, as a result, the memory cell array section 5 is mainly composed of MISFETs.

A power supply voltage VCC is connected to the train regions of each of the driving MISFETs Qd1 and Qd2 through resistive elements R and R2, respectively. Drive MISFETQ
A 14- reference voltage Vss is connected to each source region of d1 and Qd2.

As shown in FIG. 2, a sequence control (aligner) circuit 16 extending in the vertical direction is arranged in the center of the area 6 in the left-right direction. In the region between this sequential jlt control circuit 16 and the memory cell array section 5, the Y switch circuit 12, the sense amplifier circuit 13, the level conversion circuit 14, and the parity check circuit 15 are arranged from the memory cell array section 5 side, respectively. has been done.

The decoder circuit 8 includes an X decoder circuit 10. Each of the Y decoder circuits 11 is comprised of Y decoder circuits 11. Each of these X decoder circuits 1O1Y decoder circuits 11 has a word line W
In order to increase the rising speed of each of the L and Y direction selection signal lines ys, it is constructed mainly of bipolar transistors. The X decoder circuit 10 is arranged along the memory cell array section 5 in a region between the memory cell array section 6 and the input latch circuit 7.

The Y decoder circuit 11 is arranged along the Y switch circuit 12 in a region between the Y switch circuit 12 and the logic circuit 3. This X decoder times 8
10 and Y decoder circuit engineer! each decodes the address signal of 1 1 [bitl input from the input latch circuit 7 into a signal of 211, that is, 2048. Based on this decoded address signal of 2048, the X decoder circuit 10 raises the word line WL, the front By decoder circuit 11 raises the Y switch circuit $12,
A predetermined memory cell 9 in the memory cell array section 5 is selected. Here, by arranging the input latch circuit 7 and the Since the distance between the latch circuit 7 and the X/Y decoder circuit 10.11 is shorter than that of a conventional cache memory, the wiring between the input latch circuit 7 and the X/Y decoder circuit 10.11 is The length is shortened, and signal transmission delay in address signal wiring is reduced. Thereby, the operating speed of the semiconductor integrated circuit device can be increased.

5 6- Next, the operation of reading information from the memory cell array section 5 will be briefly explained.

Information stored in the memory cells 9 of the memory cell array section 5 is first amplified by the sense amplifier circuit 13 from each of the data lines DL and DL via the Y switch circuit 12. The information amplified by this sense amplifier circuit 13 is input to the level conversion circuit 14, and when the read information is 1, the power supply voltage Vcc (for example, 5[V
1).

Next, the information output from the level conversion circuit 14 is
It is output to the outside of the RAM block 4 and is also input to the parity check circuit 15. Further, the information output from the level conversion circuit 14 is transmitted to the order control circuit 16.
is output to. The parity check circuit 15 checks input information for errors.

The order control circuit 16 receives two signals from each of two adjacent memory cell array sections 5 with the order control circuit 16 in between.
4 [bjtl] of information, controls the order of the imported 48 [bit] of information, and
bit] information. The information on which this order control has been performed is output to the logic circuit 3 or 2 in FIG.
The signal is output to the input/output circuit 2 via either the path indicated by 0a or 20b.

The semiconductor integrated circuit device employs a gate array method, and circuits such as the logic device g3, the RAM block 4, and the input/output circuit 2 are basically arranged as macro cells (functional blocks).

In this way, semiconductor integrated circuit devices (cache memory)
In order to speed up the processing, an input latch circuit 7 and an When the transmission path is defined, the readout path of information from the memory cell array section 5 is defined in a direction perpendicular to the transmission path of the X-system address signal. Therefore, this readout path includes the level conversion circuit 14, parity check circuit 15, and order control circuit 16.
Each of them is arranged. According to this arrangement, it is possible to optimize (minimize) each of the X-system address signal transmission path and the information readout path.
The operating speed of a semiconductor integrated circuit device can be increased.

As explained above, according to this embodiment, an address signal is inputted from the logic circuit 3 to the decoder circuit 8 via the input latch circuit 7, and a predetermined memory cell 9 of the memory cell array section 5 is selected based on this address signal. In the semiconductor integrated circuit device, a human latch circuit 7 and an X, /Y decoder circuit 8 are arranged in a region between the logic circuit 3 and the memory cell array section 5 from the logic circuit 3 side. According to this configuration, the input latch circuit 7 and the X decoder circuit 8
Since the distance between them becomes smaller, the wiring length between them becomes shorter, and the signal transmission delay in the X-system address signal wiring is reduced. Thereby, the operating speed of the semiconductor integrated circuit device can be increased.

Further, a plurality of memory cell array sections 5 are arranged along the outer periphery of the logic circuit 3, and between each memory cell array section 5 (two memory cell array sections 5 of the RAM block 4)
A dedicated logic circuit for calculating information read from each memory cell array section 5, that is, a parity check circuit 15 and a sequence control circuit 16, are arranged in the area 6 between the memory cells 1 and 5. According to this configuration, a dedicated logic circuit can be arranged independently of the logic circuit 3 in an area different from the logic circuit 3, and this dedicated logic circuit can be optimized and the area occupied by this dedicated logic circuit can be reduced. High integration of semiconductor integrated circuit devices can be achieved.

At the same time, the length of the wiring required to connect the memory cell array section 5 and the dedicated logic circuit is shortened, so the signal transmission delay of the wiring is reduced, and the operating speed of the semiconductor integrated circuit device is increased. can be achieved.

Further, the RAM blocks 4 arranged in the upper and lower regions of the logic circuit 3 are mirror-symmetrical with the logic circuit 3 as an axis of symmetry. Furthermore, the two memory cell array sections 5 in each of the four divided RAM blocks 4 are as follows:
It is configured with mirror symmetry with the area 6 where the dedicated logic circuit is placed as an axis of symmetry. In this manner, by providing symmetry within the single conductor integrated circuit device, the wiring lengths of the signal paths are averaged, so that signal transmission delays are reduced.

Thereby, the operating speed of the semiconductor integrated circuit device can be increased.

Furthermore, in an electronic device on which the semiconductor integrated circuit device of this embodiment is mounted, that is, a computer equipped with each of a CPU, a cache memory, and a main memory device, it is possible to increase the operating speed and improve the packaging density on the mounting wiring board. can.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, in this embodiment, an example is shown in which the order control circuit 16 is arranged in the center of the area 6, but in the present invention, a comparator circuit may be arranged in place of the order control circuit 16.

Further, in the present invention, both or either of the RAM block 4 and the logic circuit 3 can be configured with bipolar transistors.

Further, the present invention can also be applied to an address translation memory used in a computer.

〔Effect of the invention〕

To briefly explain the effects obtained by the representative inventions disclosed in this application, it is possible to increase the operating speed of a semiconductor integrated circuit device equipped with a memory and a logic circuit as described below. can.

In a semiconductor integrated circuit device including the memory and logic circuit described above, high integration can be achieved.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram schematically showing the overall configuration of a semiconductor integrated circuit device that is an embodiment of the present invention, and FIG. 2 is an enlarged view of the area surrounded by the dotted chain line in FIG. 1. FIG. 3 is an equivalent circuit diagram of a memory cell. In the figure, 1... semiconductor substrate, 2... input/output circuit, 3...
・Logic circuit, 4... RAM block, 5... Memory cell array section, 6... Dedicated logic circuit placement area, 7...
input? 1-2 latch circuit, 8... decoder circuit.

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit device in which an address signal is input from a logic circuit to a decoder circuit via a latch circuit, and a predetermined memory cell in a memory cell array section is selected based on the address signal, the logic a latch circuit from the logic circuit side in a region between the circuit and the memory cell array section;
A semiconductor integrated circuit device characterized in that each of X/Y decoder circuits is arranged. 2. In a semiconductor integrated circuit device in which an address signal is input from a logic circuit to a decoder circuit via a latch circuit, and a memory cell in a predetermined memory cell array section is selected from among a plurality of memory cells based on the address signal, the logic circuit A plurality of memory cell array sections are arranged along the outer periphery of the memory cell array section, and a dedicated logic circuit for calculating information read from the memory cell array section is arranged in a region between the respective memory cell array sections. 1. A semiconductor integrated circuit device, wherein a latch circuit and an X/Y decoder circuit are arranged from the logic circuit side in a region between the logic circuit and the logic circuit.