CN102270490A - Large-capacity DRAM chip memory array structure - Google Patents
Large-capacity DRAM chip memory array structure Download PDFInfo
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- CN102270490A CN102270490A CN2011100761742A CN201110076174A CN102270490A CN 102270490 A CN102270490 A CN 102270490A CN 2011100761742 A CN2011100761742 A CN 2011100761742A CN 201110076174 A CN201110076174 A CN 201110076174A CN 102270490 A CN102270490 A CN 102270490A
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Abstract
A purpose of the present invention is to provide a large-capacity DRAM chip memory array structure to realize reducing package size as much as possible during the chip expansion. The DRAM chip memory array structure comprises a plurality of memory cell arrays, corresponding row decoder circuits, corresponding column decoder circuits and a main control circuit. Each memory cell array is divided into two sets memory cell array modules along the bit line direction, wherein two sets memory cell array modules comprise a set upper memory cell array modules and a set lower memory cell array modules, the number of the row modules in the lower memory cell array modules is half of the number of the row modules in the upper memory cell array modules. The column decoder circuits are mainly arranged between the upper memory cell array modules and the lower memory cell array modules. With the present invention, according to improvements of the composition and the placement of the memory cell arrays in the DRAM chips, and improvements of the main control circuit, the row decoder circuits, and the column decoder circuits, the problem of the limited packaging of the large-capacity DRAM chip area is simply and effectively solved.
Description
Technical field
The present invention relates to a kind of dram chip memory array structure, especially be applied to the encapsulation of high capacity dram chip.
Background technology
Along with the dram chip capacity is increasing, based on client's specific demand, encapsulation (package) size is also increasing to the restriction of chip area.In order to be encapsulated in chip among the less package, we can and put and make certain improvement the formation of memory cell array module in the memory circuitry, and certainly, the control circuit of memory cell array also needs to make corresponding improvement.
Package is a rectangular structure as shown in Figure 1, and dram chip shown in Figure 2 also is a rectangular structure.Increase along with the dram chip capacity, the area of dram chip also can correspondingly increase, but because some specific demands of user, the area of package does not always scale up, so jumbo dram chip area often is subjected to the restriction of package size in x or y direction, all can be restricted at both direction sometimes.
As shown in Figure 2, dram chip can be divided into four parts substantially: memory cell array, row decoder circuits, column decoder circuit, total control circuit.Wherein the area of memory cell array has accounted for the overwhelming majority of total chip area.Suppose that we will design the dram chip that a capacity is 2 times of dram chip capacity shown in Figure 2, general have two kinds of methods:
1, directly memory cell array is doubled in the x direction, bit line (bit line) can double like this, so column decoder also can double and do corresponding improvement (because column address increases by) in the x direction simultaneously, total control circuit also can double and make corresponding improvement (column address increases by) in the x direction.
2, directly memory cell array is doubled in the y direction, word line (word line) can double like this, so line decoder also can double and do corresponding improvement (because row address increases by) in the y direction simultaneously, total control circuit does not need to increase in the y direction but will make corresponding improvement (row address increases by).
For jumbo dram chip, increase the restriction that memory cell array might be subjected to package at x or y direction separately, obviously, the structure of arranging in this way can't satisfy the requirement of small size encapsulation as far as possible.
Summary of the invention
The present invention aims to provide a kind of high capacity dram chip memory array structure, during with the dilatation of realization chip, reduces encapsulation volume as far as possible.
Want at x or y direction dram chip to be made improvement, the formation of memory cell array and the improvement of putting are the most effective.The present invention considers to increase memory cell array in x direction and y direction simultaneously, and dram chip just may satisfy the demand of package like this.
Technical scheme of the present invention is as follows:
A kind of high capacity dram chip memory array structure comprises a plurality of memory cell arrays and corresponding row decoder circuits, column decoder circuit and total control circuit; Each memory cell array is divided into upper and lower two groups of memory cell array modules along bit line direction, and wherein, the capable module number of following memory cell array module is half of capable module number of last memory cell array module; Described column decoder circuit mainly is arranged between upper and lower two groups of memory cell array modules.
Above-mentioned down memory cell array module is to be divided into identical two parts and these two parts are arranged side by side by standard module.
The above-mentioned row module number of going up the memory cell array module is A, and the row module number of following memory cell array module before cutting apart is B, satisfies A-2B 〉=1; Usually can consider 1≤A-2B≤3, the best is A-2B=1.
Above-mentioned memory cell array module down is in abutting connection with total control circuit.
Above-mentioned memory cell array module down is provided with the electric capacity of part rows decoder circuit or power supply along the remaining space that word-line direction forms, and can share the cabling of segment signal line.
The part rows decoder circuit of above-mentioned remaining space setting is redundant repair control circuit.
The present invention has the following advantages:
1, by to the formation of memory cell array in the dram chip and the improvement of putting, and is aided with improvement, simply and effectively solved the problem that high capacity dram chip area is subjected to packages limits total control circuit and row, column decoder circuit.
2, the formation of the memory cell array described in the advantage 1 and putting has been followed certain principle, makes that its implementation is simple, and makes the performance of dram chip can not be lowered.
3, the lower left remainder that memory cell array constitutes and the improvement of putting imports has been placed the partial circuit of column decoder circuit, can share the cabling of segment signal line, and this makes the wiring of whole dram chip be more prone to.
Description of drawings
Fig. 1 is the packaging appearance synoptic diagram;
Fig. 2 is the partition structure synoptic diagram of traditional dram chip storage array;
The conventional art means adopted the x direction to double the synoptic diagram of (is example with 1 memory cell array) when Fig. 3 was the chip dilatation;
The conventional art means adopted the y direction to double the synoptic diagram of (is example with 1 memory cell array) when Fig. 4 was the chip dilatation;
Fig. 5 is the structural representation of embodiment of the invention process object 2G DDR3 dram chip;
Fig. 6 realizes the preliminary figure (is example with 1 memory cell array) of 4G DDR3 memory cell array for the embodiment of the invention;
Fig. 7 realizes that for the embodiment of the invention (with 1 memory cell array is example for the final figure of 4G DDR3 memory cell array, the column decoder circuit is meant the decoder circuit of 8 original row module correspondences among the figure, and column decoder circuit 1 and 2 is meant the new decoder circuit of the row module correspondence that dilatation increases);
Fig. 8 realizes 4G DDR3 chip one-piece construction synoptic diagram for the embodiment of the invention.
Embodiment
With 4G DDR3 dram chip is that example describes.
Suppose that we are basic engineering 4G DDR3 dram chip with 2G DDR3 dram chip.
The structure of 2G DDR3 dram chip as shown in Figure 2, each memory cell array is 128M, line direction has 512*32 word line, column direction has 1024*8 bit line.Concrete structure as shown in Figure 5, at column direction, this 128M memory cell array is made up of the row module of 8 16M (1024*512*32), is made up of the capable module of 32 4M (512*1024*8) in the line direction memory cell array, the width of row module, the just number of bit line (1024); The width of row module, just the number of word line (512) all by the technology decision, generally can not done change.That is to say that the change of memory cell array and putting will be prerequisite with the width that does not destroy capable module and row module.In addition, the control and the wiring of column decoder for convenience, memory cell array preferably places the both sides of column decoder.
Because the restriction of package, the memory cell array of 4G DDR3 dram chip can not be simple double at x or y direction, so at first consider after the x direction doubles, 5 row modules to be moved to below the column decoder circuit, just can satisfy the requirement of package like this in the x direction, as shown in Figure 6, there are 11 row modules the column decoder top, there are 5 row modules the below, 3 row modules that 5 row modules that increase that column decoder circuit 1 and column decoder circuit 2 be respectively applied for that the column decoder below increases and column decoder top increase, for convenience to the control and the convenient wiring of memory cell array, we place as shown in the figure position with these two column decoder circuit; Increase row decoder circuits 1 simultaneously and be used for the capable module that the column decoder below increases.
Though said method has solved the problem that the x direction is limited by package, make the y direction be subjected to the restriction of package again, and the vacant part in lower left is too big, has wasted area of chip.In order to solve the restricted problem of y direction, we become the row module of 2 16M with the row module segmentation of each 32M, are partitioned into the row module of 10 16M so altogether, and we get up it side by side, have just satisfied the requirement of package like this in the y direction, as shown in Figure 7
Memory cell array has been divided into two, the column decoder top is the memory cell array module of a 176M, line direction has 512*32 word line, column direction has 1024*11 bit line, comprise the row module of 11 16M (1024*512*32) at column direction, comprise the capable module of 32 5.5M (512*1024*11), increase column decoder circuit 2 and be used for 8 at line direction, the decoding of 9,10 row modules; The column decoder below is the memory cell array module of a 80M, and line direction has 512*16 word line, and column direction has 1024*10 bit line.The row module that comprises 10 8M (1024*512*16) at column direction, the capable module that comprises 16 5M (512*1024*10) at line direction, increase the decoding that column decoder circuit 1 is used for these 10 8M row modules, increase the decoding that row decoder circuits 1 is used for these 16 capable modules of 5M.
Row decoder circuits and row decoder circuits 1 cooperate total control circuit to make certain change to satisfy the demand of client pagesize, the column decoder circuit, column decoder circuit 1, column decoder circuit 2 cooperate total control circuit to make certain change to satisfy the demand of look ahead (prefetch).
Vacant space, lower left can be used to place the electric capacity of power supply or places 3 partial circuits in the column decoder circuit.In this vacant space present embodiment is the width of a row module, but says at large, also can be to stay several width more, so also can correspondingly reduce the width of column decoder circuit, makes more compact structure.This clearance spaces can also be shared the cabling of segment signal line, so just makes the wiring of entire chip be more prone to.
Figure 7 shows that the 4G DDR3 chip of designing by said method, split bank wherein is exactly our memory cell array discussed above.We have placed the redundant repair control circuit in the column decoder space of each memory cell array lower left, by the redundant repair control circuit in the column decoder is moved to the lower left, and can be so that entire chip further reduces in the length of y direction.
As seen, for jumbo dram chip, when x or y direction were subjected to the restriction of package size, we can pass through said method, promptly improve the structure of memory cell array and put satisfying the needs of package, when improving structure, followed two principles:
1, do not change the width of row module and row module;
2, wiring for convenience reaches the control to memory cell array, two memory cell array modules that split is placed the both sides of column decoder circuit.
Claims (6)
1. a high capacity dram chip memory array structure comprises a plurality of memory cell arrays and corresponding row decoder circuits, column decoder circuit and total control circuit; It is characterized in that: each memory cell array is divided into upper and lower two groups of memory cell array modules along bit line direction, and wherein, the capable module number of following memory cell array module is half of capable module number of last memory cell array module; Described column decoder circuit mainly is arranged between upper and lower two groups of memory cell array modules.
2. high capacity dram chip memory array structure according to claim 1 is characterized in that: described down memory cell array module is to be divided into identical two parts and these two parts are arranged side by side by standard module.
3. high capacity dram chip memory array structure according to claim 2 is characterized in that: the described row module number of going up the memory cell array module is A, and the row module number of following memory cell array module before cutting apart is B, satisfies A-2B 〉=1.
4. high capacity dram chip memory array structure according to claim 3 is characterized in that: described memory cell array module down is in abutting connection with total control circuit.
5. high capacity dram chip memory array structure according to claim 4 is characterized in that: the remaining space that described memory cell array module down forms along word-line direction is provided with the electric capacity of part rows decoder circuit or power supply.
6. high capacity dram chip memory array structure according to claim 5 is characterized in that: the part rows decoder circuit of described remaining space setting is redundant repair control circuit.
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| CN2011100761742A CN102270490A (en) | 2011-03-29 | 2011-03-29 | Large-capacity DRAM chip memory array structure |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1052965A (en) * | 1989-12-29 | 1991-07-10 | 三星电子株式会社 | Semicondctor storage array |
| US5694352A (en) * | 1995-11-17 | 1997-12-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having layout area of periphery of output pad reduced |
| US6233196B1 (en) * | 1998-01-09 | 2001-05-15 | Samsung Electronics Co., Ltd. | Multi-bank integrated circuit memory devices with diagonal pairs of sub-banks |
| CN202042191U (en) * | 2011-03-29 | 2011-11-16 | 山东华芯半导体有限公司 | Large-volume dynamic random access memory (DRAM) chip storage array structure |
-
2011
- 2011-03-29 CN CN2011100761742A patent/CN102270490A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1052965A (en) * | 1989-12-29 | 1991-07-10 | 三星电子株式会社 | Semicondctor storage array |
| US5694352A (en) * | 1995-11-17 | 1997-12-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having layout area of periphery of output pad reduced |
| US6233196B1 (en) * | 1998-01-09 | 2001-05-15 | Samsung Electronics Co., Ltd. | Multi-bank integrated circuit memory devices with diagonal pairs of sub-banks |
| CN202042191U (en) * | 2011-03-29 | 2011-11-16 | 山东华芯半导体有限公司 | Large-volume dynamic random access memory (DRAM) chip storage array structure |
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Application publication date: 20111207 |