CN105826274A - Semiconductor package method, semiconductor package piece, and method for manufacturing dynamic random access memory - Google Patents
Semiconductor package method, semiconductor package piece, and method for manufacturing dynamic random access memory Download PDFInfo
- Publication number
- CN105826274A CN105826274A CN201510012706.4A CN201510012706A CN105826274A CN 105826274 A CN105826274 A CN 105826274A CN 201510012706 A CN201510012706 A CN 201510012706A CN 105826274 A CN105826274 A CN 105826274A
- Authority
- CN
- China
- Prior art keywords
- wafer
- pad
- silicon perforation
- logic
- memorizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Dram (AREA)
- Semiconductor Memories (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The present invention provides a semiconductor package method which comprises a step of providing a memory wafer with the formation of a dynamic random access memory and a plurality of first silicon through hole connection pads, a step of providing a logic wafer with the formation of a logic chip and a plurality of second silicon through hole connection pads, and a step of electrically connecting the first silicon through hole connection pads and the second silicon through hole connection pads through a silicon through hole mode, and realizing the wafer level package of the memory wafer and the logic wafer. A super wide bus is directly connected to the silicon through hole connection pads on the metal layer of a surface, the electrical connection with an external logic wafer is realized through the silicon through hole technology, and the reading and writing bit width and reading and writing speed of the dynamic random access memory are extended.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to the manufacture method of a kind of method for packaging semiconductor, semiconductor package part and dynamic random access memory.
Background technology
Dynamic RAM (DRAM, DynamicRandomAccessMemory) has the features such as capacity is big, speed is fast, unit cost is low, and therefore purposes is extremely wide.Through long-term development, current DRAM has been developed that multiple multi-generation products, such as: evolved to the DDR5 in the 5th generation from first generation DDR in high-performance field, evolves to LPDDR2 from LPDDR in the application scenario of low-power consumption.
As it is shown in figure 1, the DRAM of main flow generally comprises at present: storage array 10, control logic circuit 20 and interface conversion logic circuit 30. storage array 10 include substantial amounts of memory element, are used for storing data, DRAM occupies the area of maximum.Storage array is divided into the bank that multiple size is identical with mechanism, Fig. 1 showing, storage array is 8 bank, each bank is exclusive or shares data/address bus and controls bus between several bank, these data/address bus and control between bus and the bus of bank separate.Control logic circuit 20 includes: storage array control, row address latch, column address latch and position select the circuit such as logic, is used for controlling DRAM work, processes DRAM agreement, the read-write requests on DRAM interface is converted to the access to each bank.The data/address bus being connected with bank, data width is wider, for data serioparallel exchange, is converted to the data/address bus that data width on DRAM interface is narrower by interface conversion logic circuit 30.At this moment because the narrower data bus interface of DRAM layout is to reduce the difficulty at PCB upward wiring, the stability of storage system, reliability are improved.But interface logic can bring higher power consumption, and the narrower width of DRAM data bus, also limit the further lifting of DRAM reading speed.
In order to obtain broader DRAM data bus, on the one hand those skilled in the art of the present technique seek to improve the method for packing of DRAM, the TSSOP(Dual Flat encapsulation from initial) to BGA package and stacked package (StackedPackage)；Such as: use the DRAM data bus of ultra-wide, use the method for packing (the most one by one the 2 pieces of die cut being crimped) of die-to-die simultaneously, so can reach raising DRAM data bandwidth, reduce power consumption simultaneously, but this prior art and current main flow DRAM manufacture method are the most incompatible, needing structure and encapsulation at DRAM to have also been made the biggest adjustment, practicality is relatively low.On the other hand, prior art is also adopted by: Wafer-To-Wafer encapsulates.Wafer consistent for two block sizes is directly carried out pressing by Wafer-To-Wafer encapsulation, the size of the logic region on two pieces of wafers and pin arrangement need completely the same, after pressing completes, all logic regions on two pieces of wafers i.e. complete to connect, after wafer is opened in cutting, form the one single chip group that single size structure just obtains connecting, this mode completes the connection of all chips on two pieces of wafers simultaneously, it is not necessary to as two chip blocks are attached by die-to-die encapsulation one by one, therefore cost is lower.
But there is the problem that yields is low in Wafer-to-wafer encapsulation always, because Wafer-to-wafer encapsulation needs chip corresponding on two pieces of wafers to be non-defective unit, the yields of the chipset after guarantee connection, defect rate on the most a certain piece of wafer is higher, will cause escorting rear chipset yields and drastically reduce.Such as: do wafer-level packaging with DRAM wafer and SOC wafer, if the yields of SOC wafer is 98%, the yields of DRAM wafer is 90%, then after encapsulation, the yields of chipset is 0.98*0.9=88.2%.So sacrifice the dram chip that SOC qualified on SOC wafer is qualified with on DRAM wafer, therefore can waste more qualified chip, add the cost of the production and operation.
Additionally, in the Chinese patent application of Publication No.: CN201310289419.9, disclose a kind of dynamic random access memory and manufacture method, semiconductor package part and manufacture method.Power pad, signal pad, microbonding dish are provided on memorizer wafer nude film；And on power pad, microbonding dish, forming its docking pad of connection, memory inside data/address bus is connected with microbonding dish；Thering is provided second wafer with logic chip, the second wafer also includes docking pad；Memorizer wafer and the second wafer realize wafer-level packaging by the docking pad electrical connection adapted, and the compatible existing DRAM processing technology of this mode improves the reading writing rate of DRAM, reduces overall power.But this kind of method needs additionally to increase semiconductor layer and makes microbonding dish, docking pad, increases DRAM making, packaging cost, this external memory wafer and the second wafer docking structural precision of bonding of pad, the reliability of electric property and there is also uncertainty.
Summary of the invention
The present invention provides a kind of method for packaging semiconductor, including:
The memorizer wafer being formed with dynamic random access memory is provided, memorizer wafer is formed some first silicon perforation docking pads；
The logic wafer being formed with logic chip is provided, logic wafer is formed some second silicon perforation docking pads；
The first silicon perforation docking pad and the second silicon perforation docking pad is electrically connected, it is achieved described memorizer wafer and the wafer-level packaging of logic wafer by silicon perforation means；
In one embodiment, wide input/output interface is provided in described memorizer wafer, the data/address bus of described dynamic random access memory is exported by wide input/output interface, and it is directly connected to logic wafer, the read-write bit wide of extended dynamic random access memory and read or write speed by silicon perforation means；
In one embodiment, the first silicon perforation docking pad, the size of the second silicon perforation docking pad are N*M；Wherein N is less than or equal to 20 microns, and M is less than or equal to 20 microns；
In one embodiment, it is more than the area by silicon perforation means Yu memorizer wafer junction by the area of silicon perforation means with logic wafer junction；
In one embodiment, the first silicon perforation docking pad, the second silicon perforation docking pad are: power pad, signal pad, testing weld pad, order control one or more in pad；
In one embodiment, the internal bus of dynamic random access memory includes: data/address bus and control bus, described internal bus is corresponding with one or more groups storage array in described dynamic random access memory, and the data width of described internal bus is more than or equal to 64 bits；
In one embodiment, the first silicon perforation docking pad of memorizer wafer is the most corresponding with the second silicon perforation docking number of pad, type and position on described logic wafer；
In one embodiment, one or more in the physical interface logic of the described dynamic random access memory of selectable closedown, serioparallel exchange logic, mode register, delay phase-locked loop；
In one embodiment, after described wafer-level packaging, splitting described memorizer wafer and logic wafer, it is thus achieved that quasiconductor cross tie part, described quasiconductor cross tie part includes described dynamic random access memory and logic chip；Described quasiconductor cross tie part is packaged, it is thus achieved that semiconductor package part；
The present invention also provides for a kind of semiconductor package part, including:
Dynamic random access memory, it includes some first silicon perforation docking pads；Logic chip, it includes some second silicon perforation docking pads；First silicon perforation docking pad of dynamic random access memory is docked pad with the second silicon perforation of described logic chip and is electrically connected by silicon perforation means.
The present invention also provides for a kind of dynamic random access memory manufacture method, it is characterised in that including:
Memorizer wafer is provided, described memorizer wafer is formed some first silicon perforation docking pads；Described memorizer wafer is repaired；After reparation, if the yields of described memorizer wafer is bonded with the second silicon perforation docking pad of logic wafer by silicon perforation means more than or equal to predetermined threshold, the most described first silicon perforation docking pad；
In one embodiment, described predetermined threshold value is 70% ~ 90%.
In one embodiment, if the yields of described memorizer wafer is less than predetermined threshold, then described memorizer wafer is split, it is thus achieved that described memory die also encapsulates.
Compared with prior art, technical scheme has the advantage that
First, read/be stored in memory cell to be carried out by ultra-wide bus, and it is provided without in prior art the serioparallel exchange unit of generally employing, on the silicon perforation docking pad that this ultra-wide bus is directly connected on the metal level on surface, and realize being electrically connected by silicon puncturing technique and external logic wafer, extend read-write bit wide and the read or write speed of dynamic random access memory.
Secondly, silicon perforation docking pad, while ensureing electricity transmission data, can significantly reduce the size of pad, increase the area of device functional area, it is simple to the more functional device of layout.
3rd, silicon perforation docking pad size is less, and the parasitic capacitance that therefore silicon perforation connects is the least, much smaller than the electric capacity of microbonding dish in aforementioned patent, it is possible to drive docking pad with less power consumption, and realizes the highest transfer rate.
4th, silicon perforation interconnection technique relative maturity, there is the highest yield (nearly 100%), relative to other memorizer wafer and the wafer-level packaging (such as microbonding disk technology) of logic wafer, improve the yield after memorizer wafer and logic wafer wafer-level packaging.
5th, because the power pad on memorizer wafer, signal pad, testing weld pad and order control pad can be connected on logic wafer corresponding silicon perforation docking pad by silicon perforation, so being also 1) after memorizer wafer is connected together by silicon perforation with logic wafer, re-test and patch memory wafer；2) tested and patch memory wafer by logic wafer；Provide probability.
Accompanying drawing explanation
By Figure of description and being used for illustrating the detailed description of the invention of some principle of the present invention subsequently together with Figure of description, further feature and advantage that the present invention is had will be clear from or more specifically be illustrated.
Fig. 1 is the DRAM structural representation of a kind of prior art；
Fig. 2 is the schematic flow sheet of an embodiment of method for packaging semiconductor of the present invention；
Fig. 3 is the structural representation of embodiment DRAM of method for packaging semiconductor of the present invention；
Fig. 4 is the side sectional view of the memorizer wafer that is packaged of method for packaging semiconductor of the present invention and logic wafer；
Fig. 5 is the top view of the memorizer wafer of method for packaging semiconductor of the present invention；
Fig. 6 is the top view of the logic wafer of method for packaging semiconductor of the present invention；
Fig. 7 is that the silicon of method for packaging semiconductor of the present invention is bored a hole in the perspective view of each interconnection layer；
The schematic flow sheet of Fig. 8 dynamic random access memory of the present invention manufacture method one embodiment.
Detailed description of the invention
Elaborate a lot of detail in the following description to fully understand the present invention.But the present invention can be different from alternate manner described here implement with multiple, those skilled in the art can do similar popularization in the case of intension of the present invention, and therefore the present invention is not limited by following public being embodied as.
Secondly, the present invention utilizes schematic diagram to be described in detail, when describing the embodiment of the present invention in detail, as a example by be easy to explanation, described schematic diagram is example, and it should in no way limit the scope of protection of the invention at this.
In the accompanying drawings, in order to become apparent from, the ratio of the shape of element there may be and zooms in or out, and corresponding numeral is for corresponding element throughout.It will be further understood that when one layer referred be on another layer or substrate time, it can be to be located immediately on another layer or substrate or can also there is intermediate layer.
The present invention provides a kind of method for packaging semiconductor, comprises the following steps in method for packaging semiconductor:
The memorizer wafer being formed with dynamic random access memory is provided, memorizer wafer is formed some first silicon perforation docking pads；The logic wafer being formed with logic chip is provided, logic wafer is formed some second silicon perforation docking pads；The first silicon perforation docking pad and the second silicon perforation docking pad is electrically connected, it is achieved described memorizer wafer and the wafer-level packaging of logic wafer by silicon perforation means；Wherein, wide input/output interface (WideI/O) is provided in memorizer wafer, the data/address bus of described dynamic random access memory is exported by wide input/output interface, and it is directly connected to logic wafer, the read-write bit wide of extended dynamic random access memory and read or write speed by silicon perforation means；Wherein, the first silicon perforation docking pad, the size of the second silicon perforation docking pad are N*M；Wherein N is less than or equal to 20 microns, and M is less than or equal to 20 microns；Wherein, it is more than the area by silicon perforation means Yu memorizer wafer junction by the area of silicon perforation means with logic wafer junction；Wherein, described first silicon perforation docking pad, the second silicon perforation docking pad are: power pad, signal pad, testing weld pad, order control one or more in pad；Wherein, the internal bus of dynamic random access memory includes: data/address bus and control bus, described internal bus is corresponding with one or more groups storage array in described dynamic random access memory, and the data width of described internal bus is more than or equal to 64 bits；Wherein, the first silicon perforation docking pad of memorizer wafer is the most corresponding with the second silicon perforation docking number of pad, type and position on logic wafer；Described method further comprises the steps of: one or more in the physical interface logic of the described dynamic random access memory of selectable closedown, serioparallel exchange logic, mode register, delay phase-locked loop;Described method also includes: step, after described wafer-level packaging, splits memorizer wafer and logic wafer, it is thus achieved that quasiconductor cross tie part, quasiconductor cross tie part includes dynamic random access memory and logic chip；Double interconnection of conductors part is packaged, it is thus achieved that semiconductor package part.
Below method for packaging semiconductor is specifically described: refer to Fig. 2 ~ Fig. 7；Fig. 2 is the schematic flow sheet of an embodiment of method for packaging semiconductor of the present invention；Fig. 3 is: for the structural representation of embodiment DRAM of method for packaging semiconductor of the present invention；Fig. 4 is the side sectional view of the memorizer wafer that is packaged of method for packaging semiconductor of the present invention and logic wafer；Fig. 5 is the top view of the memorizer wafer of method for packaging semiconductor of the present invention；Fig. 6 is the top view of the logic wafer of method for packaging semiconductor of the present invention；Fig. 7 is that the silicon of method for packaging semiconductor of the present invention is bored a hole in the perspective view of each interconnection layer.Refer to Fig. 2, Fig. 3, Fig. 4, perform step S110, memorizer wafer 100 is provided, memory die i.e. dynamic random access memory it is formed with on memorizer wafer 100, top layer metallic layer 110 it is formed with in memory die, the first silicon perforation docking pad it is formed with on top layer metallic layer 110, first silicon perforation docking pad includes: power pad 101, signal pad 102 and order control pad 103, draw the internal bus of memory die, internal bus includes: data/address bus 40 ' and control bus 40, described data/address bus 40 ' is connected with signal pad 102, described control bus 40 controls pad 103 with order and is connected.
With continued reference to Fig. 2, Fig. 3, specifically, described memory die includes organizing internal bus more, and described internal bus includes: data/address bus 40 ' and control bus 40.Described internal bus be connected with described storage array, the data/address bus 40 ' of wider width and control bus 40, its data width can be more than or equal to 64 bits, wider data/address bus 40 ' can improve data transmit efficiency.Described internal bus is at least connected with one group of storage array 10.For ensureing the reliability of DRAM or improving reusability, described internal bus can be connected with many group storage arrays.Described order controls pad and includes: instruction pad, address pad etc..
The formation power pad 101 controlled on top layer metallic layer 110 in described memory die of the present embodiment, signal pad 102, order control pad 103, testing weld pad (mark), and the most selectable formation power pad 101, signal pad 102 and order control one or more in pad 103, testing weld pad (mark)；And from the storage array of described memory die, draw wide internal bus be connected with pad, and be electrically connected with outside logic wafer by the silicon perforation means in subsequent step.Described, power pad 101, signal pad 102, order control pad 103, testing weld pad (mark) on the basis of ensureing data transmission quality, may be designed as less size, and use silicon puncturing technique fast and efficiently data to be transmitted, extend read-write bit wide and the read or write speed of dynamic random access memory.
Continue with reference to Fig. 2, Fig. 3, Fig. 4, power pad 101 is for powering for DRAM, described signal pad 102 is for being connected to the data/address bus of DRAM, this data/address bus can be fabricated to ultra-wide bus, at this, the bus definition more than or equal to 64bit figure place is ultra-wide bus, ultra-wide bus is electrically connected at outside by signal pad, and ensures the reliability of DRAM.Order controls pad 103 and is used for being connected to the control bus of DRAM, and this controls bus can use conventional bus lines, and conventional bus lines often uses 16 or 32 to realize.
With continued reference to Fig. 2, S120: the logic wafer 200 being formed with logic chip is provided, some second silicon perforation docking pads it are formed with on logic wafer 200, the character of the second silicon perforation docking pad is identical with the character of the first silicon perforation docking pad, specifically comprises the steps that power pad 201, signal pad 202, testing weld pad (mark) and order control one or more in pad (not indicating).
With continued reference to Fig. 2, Fig. 4, Fig. 7 perform step S130, S130: electrically connect the first silicon perforation docking pad and the second silicon perforation docking pad by silicon perforation means, it is achieved described memorizer wafer and the wafer-level packaging of logic wafer.Please also refer to Fig. 4, Fig. 7, Fig. 4 is passed some interconnection layers by the first silicon perforation butt welding panel surface by via by silicon puncturing technique, can be observed to be respectively the first via 300 by the aperture of memorizer wafer to logic wafer direction, second via 301,3rd via 302, in the present embodiment via the first via 300, the second via 301, the aperture of the 3rd via 302 is for being gradually increased, and the size of the first silicon perforation docking pad is the most corresponding more than or equal to the size of the first via 30.
In addition, being formed with some metal layer pad corresponding to memorizer wafer 100 on the metal level of logic wafer 200, these metal layer pad are that some metal layer pad are controlled, with the power pad 101 of memorizer wafer, signal pad 102 and order, the electrical connection that pad 103 adapts by TSV mode by the second silicon perforation docking pad 201,202.This step makes to be led to the power pad 101 of memorizer wafer 100, signal pad 102, order control pad 103 by the ultra-wide bus of DRAM and is electrically connected the second silicon perforation docking pad to logic wafer 200 by the silicon perforation of TSV mode again；The compatible existing DRAM processing technology of this type of mode, improves the reading writing rate of DRAM, reduces overall power, and makes unnecessary connection pad without increasing layer in the surface of memorizer wafer, logic wafer.
Please also refer to Fig. 4, Fig. 5, Fig. 6, owing to using TSV mode, ensure memorizer wafer 100 and logic wafer 200 be electrically connected performance on the basis of, described power pad 101, signal pad 102, testing weld pad (mark) and order control the size of pad 103 and can be controlled in the size (5 microns≤N≤50 micron less than or equal to N*M, 5 microns≤M≤50 micron), the space of crystal column surface need to be occupied owing to making pad, those skilled in the art of the present technique know that needs are in the case of ensureing electric property, reduce the application space of the silicon of crystal column surface and then increase the area in functional circuit region, the present embodiment uses the pad of 9 microns * 9 microns.According to increasing layer and making the mode of docking pad, the size of docking pad is generally 100 microns * 100 microns, this scheme can occupy the physical space of crystal column surface in a large number, those skilled in the art of the present technique know, the scope that crystal column surface is reserved in functional area is the biggest, the semiconductor device that can make is the most, is more improved device integration, reduces cost.
With continued reference to Fig. 2, after step S130 is finished, the most optionally performs step S140, close one or more in the physical interface logic of memory die, serioparallel exchange logic, mode register, delay phase-locked loop.Described physical interface logic, serioparallel exchange logic, mode register, delay phase-locked loop are traditional to be read the components and parts needed for DRAM by interface conversion logic circuit, when DRAM works under ultra-wide mode bus, these components and parts can be selectively closed off, to reduce energy consumption further.
With continued reference to Fig. 2, perform step S150 further: after described wafer-level packaging, splitting described memorizer wafer and logic wafer, it is thus achieved that quasiconductor cross tie part, described quasiconductor cross tie part includes described dynamic random access memory and logic chip；Described quasiconductor cross tie part is packaged, it is thus achieved that semiconductor package part.
With continued reference to Fig. 2, the most optionally performing step S160, form test logic chip in the scribe line of memorizer wafer, test logic chip is connected with memory chip, in order to test device.
The present embodiment not structure to current DRAM does bigger change, and add the data-bus width of DRAM, and directly it is electrically connected in the first silicon perforation docking pad, directly connected away by serial line interface, without the interface by turning serial parallel, reduce power consumption, improve the efficiency of data transmission.In addition the area that the first silicon perforation docking pad occupies is less, can increase the layout designs space of device, improve the integrated level of product.
Present invention also offers the schematic flow sheet of a kind of dynamic random access memory manufacture method first embodiment.Please continue to refer to the schematic flow sheet of Fig. 8 dynamic random access memory of the present invention manufacture method one embodiment, shown in Fig. 8, the present embodiment comprises the following steps:
Perform step S210, memorizer wafer is provided, memory die i.e. dynamic random access memory it is formed with on memorizer wafer, top layer metallic layer it is formed with in memory die, the first silicon perforation docking pad it is formed with on top layer metallic layer, first silicon perforation docking pad includes: power pad, signal pad, testing weld pad and order control one or more in pad, draw the internal bus of memory die, internal bus includes: data/address bus and control bus, described data/address bus is connected with data signal pad, described control bus controls pad with order and is connected.
Specifically, described memory die includes organizing internal bus more, and described internal bus includes: data/address bus and control bus.Described internal bus be connected with described storage array, the data/address bus of wider width and control bus, its data width can be more than or equal to 64 bits, wider data/address bus can improve data transmit efficiency.Described internal bus is at least connected with one group of storage array.For ensureing the reliability of DRAM or improving reusability, described internal bus can be connected with many group storage arrays.Described order controls pad and includes: instruction pad, address pad etc..
Formation power pad, signal pad, testing weld pad and the order control pad that the present embodiment is controlled on top layer metallic layer in described memory die, and from the storage array of described memory die, draw wide internal bus be connected with pad, and be electrically connected with outside logic wafer by the silicon perforation means in subsequent step.Described, power pad, signal pad, testing weld pad and order control pad on the basis of ensureing data transmission quality, may be designed as less size, and use silicon puncturing technique fast and efficiently data to be transmitted.
Specifically, described power pad is for powering for DRAM, described signal pad is for being connected to the data/address bus of DRAM, this data/address bus can be fabricated to ultra-wide bus, at this, the bus definition more than or equal to 64bit figure place is ultra-wide bus, ultra-wide bus is electrically connected at outside by signal pad, and ensures the reliability of DRAM.Order controls pad and is used for being connected to the control bus of DRAM, and this controls bus can use conventional bus lines, and conventional bus lines often uses 16 or 32 to realize.
With continued reference to Fig. 8, perform step S220, may select and memorizer wafer is repaired.It should be noted that the method repairing wafer is not especially limited by the present invention, in prior art, the method for existing multiple reparation wafer, such as: cut (lasertrimming) etc., all can be applicable to the present invention.By repairing, can further improve the yields of described memorizer wafer.
With continued reference to Fig. 8, perform step S230, whether the selectable yields judging memorizer wafer is more than or equal to predetermined threshold, if more than or equal to predetermined threshold, the most described first silicon perforation docking pad docks pad by silicon perforation means with the second silicon perforation of logic wafer and is bonded.Specifically, if described predetermined threshold value is relatively low, then the DRAM yields ultimately formed is relatively low, in the case of the wafer yields being formed with SOC is higher, can cause more waste.If described predetermined threshold value is higher, then the requirement using DRAM manufacture method of the present invention is higher, and the chance that the advantage of this method is played is less, accordingly, it is preferred that predetermined threshold value is 70% ~ 90%.
With continued reference to Fig. 8, if the yields of memorizer wafer is more than or equal to predetermined threshold, by silicon perforation (TSV) mode, the logic wafer of memorizer wafer and SOC is electrically connected in one.
Concrete, it is formed with some metal layer pad corresponding to memorizer wafer on the metal level of logic wafer, by TSV mode, some metal layer pad is controlled, with the power pad of memorizer wafer, signal pad, testing weld pad and order, the electrical connection that pad adapts.This step makes to be led to the power pad of memorizer wafer by the ultra-wide bus of DRAM, signal pad, order are controlled pad and bored a hole by the silicon of TSV mode and be electrically connected the metal layer pad to logic wafer；The compatible existing DRAM processing technology of this type of mode, improves the reading writing rate of DRAM, reduces overall power, and makes unnecessary connection pad without increasing layer in the surface of memorizer wafer, logic wafer.
Owing to using TSV mode, ensure memorizer wafer and logic wafer be electrically connected performance on the basis of, described power pad, signal pad, testing weld pad and order control the size of pad and can be controlled in the size (5 microns≤N≤50 micron less than or equal to N*M, 5 microns≤M≤50 micron), the space of crystal column surface need to be occupied owing to making pad, those skilled in the art of the present technique know that needs are in the case of ensureing electric property, reduce the application space of the silicon of crystal column surface and then increase the area in functional circuit region, the present embodiment uses the pad of 9 microns * 9 microns.According to increasing layer and making the mode of docking pad, the size of docking pad is generally 100 microns * 100 microns, this scheme can occupy the physical space of crystal column surface in a large number, those skilled in the art of the present technique know, the scope that crystal column surface is reserved in functional area is the biggest, the semiconductor device that can make is the most, is more improved device integration, reduces cost.
The most optionally perform step S240, close one or more in the physical interface logic of memory die, serioparallel exchange logic, mode register, delay phase-locked loop.Described physical interface logic, serioparallel exchange logic, mode register, delay phase-locked loop are traditional to be read the components and parts needed for DRAM by interface conversion logic circuit, when DRAM works under ultra-wide mode bus, these components and parts can be selectively closed off, to reduce energy consumption further.
The most optionally performing step S250, form test logic chip in the scribe line of memorizer wafer, test logic chip is connected with memory chip, in order to test device.
If the yields of memorizer wafer is less than predetermined threshold, then performs step S260, split memorizer wafer, it is thus achieved that memory die also encapsulates.Cutting DRAM wafer, is packaged according to original method for packing, forms dram chip.
The present embodiment not structure to current DRAM does bigger change, and add the data-bus width of DRAM, make DRAM can not only be used for ultra-wide bus DRAM to use, also can use as tradition DRAM when yield is inadequate, thus reduce from current DRAM technology to the risk and cost of new technique evolution, ensure comparatively ideal yields simultaneously, reduce manufacturing cost further.
Fig. 3 is the structural representation of the present embodiment memory die.As it is shown on figure 3, the memory die of the present embodiment includes: storage array 10, control logic circuit 20, interface conversion logic circuit 30, original bus 40 and ultra-wide bus 40 '.
Described storage array 10 includes: 8 bank(bank0 ~ bank7), it is used for storing data.
Described control logic circuit 20 includes: row address latch, storage array control circuit, column address latch, position selects logic circuit etc., are used for controlling described storage array, it is achieved to the read-write operation of particular memory location in described bank.
The data that described interface conversion logic circuit 30 is used for read out from described bank, through serioparallel exchange, transfer out from special interface.Through the data-bus width of described interface conversion logic circuit 30 by limit significantly.
Described original bus 40 includes: original address bus and legacy data bus.As it is shown on figure 3, described original address-bus width is typically about 15 bits, described legacy data highway width is generally 4,8,16 bits.In the present embodiment, the legacy data highway width before described interface logic change-over circuit serioparallel exchange is 16 bits, and the legacy data highway width constriction after described interface logic change-over circuit serioparallel exchange is for 4 bits.Legacy data bus after serioparallel exchange will be ultimately connected on original signal pad, with the needs of satisfied tradition DRAM encapsulation.
Described ultra-wide bus 40 ' including: ultra-wide address bus and ultra-wide data/address bus, for realizing the ultra-wide bus DRAM manufacture method of the present invention.As it is shown on figure 3, the width of described ultra-wide bus 40 ' is significantly wider than described original bus 40.Specifically, described ultra-wide address bus can be divided into multichannel (such as: 2,4,8 tunnels etc., only with 1 tunnel signal in the present embodiment), and each degree of having a lot of social connections is about 32 bits.Described ultra-wide data/address bus also can be divided into multichannel, and often degree of having a lot of social connections can be 64,128,256 bits, even broader.In the present embodiment, the width of described ultra-wide data/address bus is 128 bits.Described ultra-wide data/address bus is without described interface conversion logic circuit 30, but together with described ultra-wide address bus, is directly connected with the signal pad (not shown) in the first silicon perforation docking pad, to realize the DRAM of ultra-wide bus.
If cannot meeting the requirement of the yields of memorizer wafer and can only continuing to use traditional DRAM manufacture method, then the work process of the present embodiment DRAM is as follows:
First, needs are read out/memory unit address of write operation controls to described storage array through the transmission of described original address bus, described storage array forms row address after controlling to resolve and delivers to described row address latch, concurrently forms column address and delivers to the latch of described column address.Then, described row address latch chooses the corresponding row of a certain bank in described storage array through described original address bus.Described column address latches and selects logic through institute rheme, chooses the memory element of respective column in described corresponding row.Described memory element is read out/write operation.Data in described memory element are exported by wide input/output interface through wider legacy data bus (width 16 bit), and be connected directly on the second silicon perforation connection pad of logic wafer by silicon perforation means by the first silicon perforation docking pad of layer on surface of metal, extend read-write bit wide and the read or write speed of dynamic random access memory.Change and prior art needs by the way of parallel interface turns being transmitted of serial line interface.
If the requirement that need to meet memorizer wafer yields can use the method for the present invention to realize the DRAM of ultra-wide data/address bus, then the specific works process of the present embodiment DRAM is as follows:
First, it would be desirable to be read out/access unit address of write operation is directly transferred to described row address latch and described column address latches through described ultra-wide address bus (width 32 bit).Described row address latch chooses the corresponding row of a certain bank in described storage array through described original address bus.Described column address latches and selects logic through institute rheme, chooses the memory element of respective column in described corresponding row.Described memory element is read out/write operation.Data in described memory element are directly through the external interface (that is: the signal pad in the first silicon perforation docking pad) of described ultra-wide data/address bus (exceeding width 64 bit) transmission to DRAM.
Also providing for a kind of semiconductor package part in one embodiment of the invention, semiconductor package part includes: dynamic random access memory, and it includes some first silicon perforation docking pads；Logic chip, it includes some second silicon perforation docking pads；First silicon perforation docking pad of dynamic random access memory is docked pad with the second silicon perforation of described logic chip and is electrically connected by silicon perforation means.
The present invention relatively prior art has following Advantageous Effects；First, read/be stored in memory cell to be carried out by ultra-wide bus, and it is provided without in prior art the serioparallel exchange unit of generally employing, on the silicon perforation docking pad that this ultra-wide bus is directly connected on the metal level on surface, and realize being electrically connected by silicon puncturing technique and external logic wafer, extend read-write bit wide and the read or write speed of dynamic random access memory.Secondly, silicon perforation docking pad, while ensureing electricity transmission data, can significantly reduce the size of pad, increase the area of device functional area, it is simple to the more functional device of layout.3rd, silicon perforation docking pad size is less, and the parasitic capacitance that therefore silicon perforation connects is the least, much smaller than the electric capacity of microbonding dish in aforementioned patent, it is possible to drive docking pad with less power consumption, and realizes the highest transfer rate.4th, silicon perforation interconnection technique relative maturity, there is the highest yield (nearly 100%), relative to other memorizer wafer and the wafer-level packaging (such as microbonding disk technology) of logic wafer, improve the yield after memorizer wafer and logic wafer wafer-level packaging.5th, because the power pad on memorizer wafer, signal pad, testing weld pad and order control pad can be connected on logic wafer corresponding silicon perforation docking pad by silicon perforation, so being also 1) after memorizer wafer is connected together by silicon perforation with logic wafer, re-test and patch memory wafer；2) tested and patch memory wafer by logic wafer；Provide probability.
Although the present invention is open as above with preferred embodiment; but it is not for limiting the present invention; any those skilled in the art are without departing from the spirit and scope of the present invention; technical solution of the present invention is made possible variation and amendment by the method and the technology contents that may be by the disclosure above; therefore; every content without departing from technical solution of the present invention; any simple modification, equivalent variations and the modification made above example according to the technical spirit of the present invention, belongs to the protection domain of technical solution of the present invention.
Claims (13)
1. a method for packaging semiconductor, it is characterised in that including:
The memorizer wafer being formed with dynamic random access memory is provided, memorizer wafer is formed some first silicon perforation docking pads；
The logic wafer being formed with logic chip is provided, logic wafer is formed some second silicon perforation docking pads；
The first silicon perforation docking pad and the second silicon perforation docking pad is electrically connected, it is achieved described memorizer wafer and the wafer-level packaging of logic wafer by silicon perforation means.
Method for packaging semiconductor the most according to claim 1, it is characterized in that, wide input/output interface is provided in described memorizer wafer, the data/address bus of described dynamic random access memory is exported by wide input/output interface, and it is directly connected to logic wafer, the read-write bit wide of extended dynamic random access memory and read or write speed by silicon perforation means.
Method for packaging semiconductor the most according to claim 1, it is characterised in that described first silicon perforation docking pad, the size of the second silicon perforation docking pad are N*M；Wherein N is less than or equal to 20 microns, and M is less than or equal to 20 microns.
Method for packaging semiconductor the most according to claim 1, it is characterised in that the described area by silicon perforation means with logic wafer junction is more than the area by silicon perforation means Yu memorizer wafer junction.
Method for packaging semiconductor the most according to claim 1, it is characterised in that described first silicon perforation docking pad, the second silicon perforation are docked pad and be: power pad, signal pad, testing weld pad, order control one or more in pad.
Method for packaging semiconductor the most according to claim 5, it is characterized in that, the internal bus of described dynamic random access memory includes: data/address bus and control bus, described internal bus is corresponding with one or more groups storage array in described dynamic random access memory, and the data width of described internal bus is more than or equal to 64 bits.
Method for packaging semiconductor the most according to claim 1, it is characterised in that the first silicon perforation docking pad of described memorizer wafer is the most corresponding with the second silicon perforation docking number of pad, type and position on described logic wafer.
Method for packaging semiconductor the most according to claim 1, it is characterised in that also include: one or more in the physical interface logic of the described dynamic random access memory of selectable closedown, serioparallel exchange logic, mode register, delay phase-locked loop.
Method for packaging semiconductor the most according to claim 1, it is characterised in that also include:
After described wafer-level packaging, splitting described memorizer wafer and logic wafer, it is thus achieved that quasiconductor cross tie part, described quasiconductor cross tie part includes described dynamic random access memory and logic chip；
Described quasiconductor cross tie part is packaged, it is thus achieved that semiconductor package part.
10. a semiconductor package part, it is characterised in that including:
Dynamic random access memory, it includes some first silicon perforation docking pads；
Logic chip, it includes some second silicon perforation docking pads；
First silicon perforation docking pad of dynamic random access memory is docked pad with the second silicon perforation of described logic chip and is electrically connected by silicon perforation means.
11. 1 kinds of dynamic random access memory manufacture methods, it is characterised in that including:
Memorizer wafer is provided, described memorizer wafer is formed some first silicon perforation docking pads；
Described memorizer wafer is repaired；
After reparation, if the yields of described memorizer wafer is bonded with the second silicon perforation docking pad of logic wafer by silicon perforation means more than or equal to predetermined threshold, the most described first silicon perforation docking pad.
12. dynamic random access memory manufacture methods according to claim 11, it is characterised in that described predetermined threshold value is 70% ~ 90%.
13. dynamic random access memory manufacture methods according to claim 11, it is characterised in that also include:
If the yields of described memorizer wafer is less than predetermined threshold, then split described memorizer wafer, it is thus achieved that described memory die also encapsulates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510012706.4A CN105826274A (en) | 2015-01-09 | 2015-01-09 | Semiconductor package method, semiconductor package piece, and method for manufacturing dynamic random access memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510012706.4A CN105826274A (en) | 2015-01-09 | 2015-01-09 | Semiconductor package method, semiconductor package piece, and method for manufacturing dynamic random access memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105826274A true CN105826274A (en) | 2016-08-03 |
Family
ID=56514294
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510012706.4A Pending CN105826274A (en) | 2015-01-09 | 2015-01-09 | Semiconductor package method, semiconductor package piece, and method for manufacturing dynamic random access memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105826274A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108364949A (en) * | 2018-02-10 | 2018-08-03 | 盛科网络（苏州）有限公司 | A kind of method and chip interconnection architecture for realizing chip interconnection ultra high bandwidth |
| CN108962856A (en) * | 2017-05-18 | 2018-12-07 | 三星电子株式会社 | Semiconductor memory chips, semiconductor memory encapsulation and the electronic system using it |
| WO2021142816A1 (en) * | 2020-01-19 | 2021-07-22 | 华为技术有限公司 | Wafer to wafer structure and test method therefor, and high bandwidth memory and manufacturing method therefor |
| WO2022205705A1 (en) * | 2021-03-29 | 2022-10-06 | 长鑫存储技术有限公司 | Data transmission circuit and method, and storage device |
| US11869625B2 (en) | 2021-03-29 | 2024-01-09 | Changxin Memory Technologies, Inc. | Data transmission circuit and method, and storage device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103366798A (en) * | 2013-07-10 | 2013-10-23 | 格科微电子（上海）有限公司 | DRAM (Dynamic Random Access Memory) and production method as well as semiconductor packaging component and packaging method |
| CN103579114A (en) * | 2012-07-31 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Integrated semiconductor device and wafer level method of fabricating the same |
| US20140264709A1 (en) * | 2013-03-12 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect Structure for Connecting Dies and Methods of Forming the Same |
-
2015
- 2015-01-09 CN CN201510012706.4A patent/CN105826274A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579114A (en) * | 2012-07-31 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Integrated semiconductor device and wafer level method of fabricating the same |
| US20140264709A1 (en) * | 2013-03-12 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect Structure for Connecting Dies and Methods of Forming the Same |
| CN103366798A (en) * | 2013-07-10 | 2013-10-23 | 格科微电子（上海）有限公司 | DRAM (Dynamic Random Access Memory) and production method as well as semiconductor packaging component and packaging method |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108962856A (en) * | 2017-05-18 | 2018-12-07 | 三星电子株式会社 | Semiconductor memory chips, semiconductor memory encapsulation and the electronic system using it |
| CN108962856B (en) * | 2017-05-18 | 2023-06-06 | 三星电子株式会社 | Semiconductor memory chip, semiconductor memory package, and electronic system using the same |
| CN108364949A (en) * | 2018-02-10 | 2018-08-03 | 盛科网络（苏州）有限公司 | A kind of method and chip interconnection architecture for realizing chip interconnection ultra high bandwidth |
| WO2021142816A1 (en) * | 2020-01-19 | 2021-07-22 | 华为技术有限公司 | Wafer to wafer structure and test method therefor, and high bandwidth memory and manufacturing method therefor |
| CN114830310A (en) * | 2020-01-19 | 2022-07-29 | 华为技术有限公司 | Wafer stacking structure and testing method thereof, high-bandwidth memory and preparation method thereof |
| WO2022205705A1 (en) * | 2021-03-29 | 2022-10-06 | 长鑫存储技术有限公司 | Data transmission circuit and method, and storage device |
| US11869625B2 (en) | 2021-03-29 | 2024-01-09 | Changxin Memory Technologies, Inc. | Data transmission circuit and method, and storage device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9287268B2 (en) | Dynamic random access memory (DRAM) and production method, semiconductor packaging component and packaging method | |
| US11227639B2 (en) | Stacked DRAM device and method of manufacture | |
| US10651153B2 (en) | Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bonding | |
| CN103985648B (en) | The wafer-level packaging method of quasiconductor and semiconductor package part | |
| Kang et al. | 8 Gb 3-D DDR3 DRAM using through-silicon-via technology | |
| US11877439B2 (en) | Unified micro system with memory IC and logic IC | |
| TWI552161B (en) | 3d semiconductor device | |
| CN108962301B (en) | Storage device | |
| US7830692B2 (en) | Multi-chip memory device with stacked memory chips, method of stacking memory chips, and method of controlling operation of multi-chip package memory | |
| US8384432B2 (en) | Semiconductor device and information processing system including the same | |
| US10236039B2 (en) | Apparatuses and methods for chip identification in a memory package | |
| CN105826274A (en) | Semiconductor package method, semiconductor package piece, and method for manufacturing dynamic random access memory | |
| US12009043B2 (en) | Integrated circuit chip and die test without cell array | |
| CN203325472U (en) | DRAM and semiconductor packaging part | |
| WO2020000183A1 (en) | Wafer-level packaging method for semiconductor and semiconductor package | |
| US20240071556A1 (en) | Memory with parallel main and test interfaces | |
| KR101965906B1 (en) | Semiconductor device | |
| Gupta | Stacked 3d package with improved bandwidth and power efficiency |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160803 |
|
| WD01 | Invention patent application deemed withdrawn after publication |