JPH11340438A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage where increase in wiring signal delay time is suppressed while maintaining the margin of a wiring pitch, a mesh power supply is constituted on a guard ring part and a sense amplifier, and a power supply wiring resistance is reduced to a cross region at the remote end side when viewed from a power supply pad. SOLUTION: In an 64 Mb DRAM, wiring on a memory cell sub array 15 and that on a sub word driver 17 are allowed to cross an outer-periphery guard ring line at the upper and lower ends of a chip and are short-circuited by a through hole. As a result, a number of each thin wiring on the memory cell sub array 15 can be provided, thus reducing the resistance of power supply wiring up to the driver MOS transistor of the cross region of the memory cell sub array 15 at a remote end near the upper and lower ends of the chip from a power supply pad at the center of the chip, and hence contributing to the high-speed stable operation of the sense amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to an improvement in an arrangement wiring on a memory cell sub-array and a hierarchical word line system for reducing the area and increasing the speed.

[0002]

2. Description of the Related Art For example, in a 64Mb DRAM as an example of a semiconductor memory device, the concept of a mesh power supply line for reducing the wiring resistance in a chip, stabilizing the memory operation and increasing the speed is described in M. Taguchi et al. , "A 40-ns 64-Mb DRA
M with 64-b Parallel Data Bus Architecture, "IEEE
J. Solid-State Circuits, vol.26, pp.1493-1497, Nov.1
991., T. Yamada et al., "A 64-Mb DRAM with Meshed P
ower Line, "IEEE J. Solid-State Circuits, vol.26, p
pp. 1506-1510, Nov. 1991. In this technique, a power supply line is arranged in parallel with a column selection signal line, the direction is changed by a through hole on a sense amplifier, and power is supplied to a sense amplifier driving MOS transistor in an intersection area with low resistance. Further, the mesh power supply line of US Pat. No. 4,975,874 is also changed in direction through a through hole on the sense amplifier. Further, US Pat. No. 5,293,559 discloses a mesh power supply line in which a power supply line-column selection signal line-ground line-column selection signal line is alternately arranged in parallel with a bit line. Further, Japanese Patent Publication No. 7-114259 discloses a mesh power supply line having the same shape as a column selection signal line. In each of these, a power supply line is arranged in parallel with the column selection signal line to reinforce it. However, the number of wirings parallel to the column selection signal lines was the same as that of the column selection signal lines. In this case, the metal pitch in the column selection signal line direction is too small, and the wiring yield may be deteriorated.

On the other hand, the hierarchical word line system is 64 Mb DRA.
Used after M. The hierarchical word line method of DRAM is described in T. Sugibayashi et al., "A 30-ns 256-Mb DR
AM with a multidivided array structure, "IEEE J. S
olid-State Circuits, vol.28, pp.1092-1098, Nov.199
3., M. Nakamura et al., "A 29 ns 64 Mb DRAM with hi
erarchical array architecture, "in ISSCC Dig.Tech.
Papers, Feb. 1995, pp. 246-247.
In the hierarchical word line system described in these papers, the repetition pitch (width + space) of the metal wiring (main word line) is set to four times the sub word line pitch of the memory cell sub array.
In other words, the manufacturing yield of the metal wiring is increased. This quadruple can be reduced to a larger value, for example, eight times, by devising the circuit of the sub-word driver.

[0004] By combining these two concepts to realize a mesh power supply line on a memory cell sub-array,
It is disclosed in JP-A-9-135006. This focuses on relaxation of rules for metal wiring on a memory cell sub-array using a hierarchical word line system, and provides a through-hole on the memory cell sub-array to change the direction. In this method, the power supply line parallel to the column select signal line is changed in the direction parallel to the main word line by a through hole on the memory cell sub-array, and the through line on the sub word driver is changed again to be parallel to the column select signal line. Sense amplifier drive MO
Power is supplied to the S transistor. Although the power supply line originally exists on the sub-word driver, the power supply line is thin due to the restriction on the area, so that the resistance of the entire chip is reduced by using the wiring on a large number of memory cell sub-arrays.

[0005]

However, the method disclosed in Japanese Patent Application Laid-Open No.
In the technology of -135006, only a case where a through hole is provided on a memory cell sub-array is disclosed. The reason why the through-hole is provided on the memory cell sub-array is to change the direction, and the wiring must be provided in the orthogonal direction. As a result of a study conducted by the present inventor, it has been found that there is a method which is suitable for the 64 Mb chip level and which does not have a through-hole on the memory cell sub-array, and which is different from the known technique. The method of selecting the thickness of the wiring on the memory cell sub-array is also described in
As disclosed in JP 135006, it has been found that a method different from that changed by wiring is optimal.

Therefore, the present invention relates to the above-mentioned JP-A-9-135.
The structure is improved while maintaining the concept of the wiring on the memory cell sub-array combined with the hierarchical word line system of No. 006. In addition, the present invention relates to a device for a layout of a sub-word driver.

For example, a typical configuration of the hierarchical word line system has 256 sub-word lines. When this is logically performed by the main word line (MWB) and the predecoder line (FXB), 32 (MWB) × 8 (F
XB) or 64 (MWB) × 4 (FXB). At this time, the number of signals of the predecoder line is on the small number side (8 or 4), and the number of circuits of the sub-word driver as a load is inevitably increased. As a result, the signal delay time due to the wiring resistance and the capacitance of the predecoder line increases, which becomes a rate-limiting factor in the selection speed of the sub-word line. Therefore, a problem is to reduce the wiring resistance of the predecoder line.

In the 256 word line system, there is no room to arrange a line in a direction parallel to the main word line other than the predecoder line. Therefore, a low-resistance power supply method by the above method is required.

Further, a pattern after processing is completed by a dog bone associated with a contact for converting a first-layer metal wiring or bit line wiring as an output of the sub-word driver to a sub-word line of a MOS transistor gate layer on a memory cell sub-array. There is a risk of wiring short-circuits due to thickness. For this reason, it is necessary to take measures to prevent a short circuit while suppressing an increase in the area of the sub-word driver.

Another problem is to select the width and interval of the wiring on the memory cell sub-array.

Therefore, an object of the present invention is to firstly suppress an increase in the wiring signal delay time while maintaining a sufficient wiring pitch, and secondly, configure a mesh power supply on the guard ring portion and the sense amplifier, Thirdly, the power supply wiring resistance to the crossing area on the far end side as viewed from the pad is reduced, and thirdly, the increase in the layout size of the sub-word driver is suppressed as much as possible without short-circuiting at the dogbone portion of the takeout port. D that can relax the pitch between the wiring and the third-layer metal wiring in a well-balanced manner
A semiconductor storage device such as a RAM is provided.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor memory device according to the present invention has the following features.

The first is a hierarchical word line configuration. In the case where the logic is taken by the main word line (MWB) and the predecoder line (FXB), the number of signal lines is set to two for the signal lines on the minority side. Double, the overall metal wiring pitch remains loose, the total resistance of a small number of signals is reduced, and the wiring time constant is reduced.
The speed of sub word line switching is increased.

Second, the through hole of the wiring parallel to the column selection signal line is not placed on the memory cell sub-array, but on the sense amplifier or at the guard ring portion at the chip end passing through the memory cell sub-array via the through hole. To shunt and effectively realize a mesh power supply.

Thirdly, a short circuit in the dog bone portion is prevented by slightly shifting the contact center within the range of the contact diameter so that the contact center does not completely oppose the sub word driver outlet.

Fourth, the wiring width on the memory cell sub-array is made uniform, and the intervals are arranged at equal intervals. In this case, the interval is set larger than the width. However, if unnecessary, it is thinned out.

Therefore, according to the semiconductor memory device, the following operation and effect can be obtained.

First, it is possible to suppress an increase in a wiring signal delay time while keeping a sufficient wiring pitch.

Second, a mesh power supply is formed on the guard ring portion and the sense amplifier, and the power supply wiring resistance up to the crossing area on the far end side as viewed from the power supply pad can be reduced.

Third, an increase in the layout size of the sub-word driver can be minimized without causing a short circuit at the dogbone portion of the outlet.

Fourth, the pitch between the second-layer metal wiring and the third-layer metal wiring can be relaxed with good balance.

[0024]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described in detail with reference to FIGS. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

First, the layout configuration of the semiconductor memory device of the present embodiment will be described with reference to FIG. FIG. 1A is a schematic layout diagram of a semiconductor memory device, and FIG. 1B is a partially enlarged view.

The semiconductor memory device of the present embodiment is, for example, a 64 Mb DRAM. This memory chip 10 includes a main row decoder region 11, a main word driver region 12, a column decoder region 13, a peripheral circuit / bonding pad region 14, Memory cell sub-array 15,
Sense amplifier region 16, sub-word driver region 17,
The intersection area 18 and the like are formed by a known semiconductor manufacturing technique. In the following, like the main row decoder arranged in the main row decoder area 11, each area and the circuit arranged in the corresponding area are denoted by the same reference numerals to clarify the correspondence. I will explain.

In this 64 Mb DRAM, the basic memory cell subarray 15 has 256 word lines (WL) × 2
It is a 56-bit line pair (BL pair). FIG. 1 shows a chip configuration of 64 Mb using a conventional memory cell sub-array division. The word lines extend in the long side direction and the bit lines extend in the short side direction. Using a hierarchical word line configuration and a multi-segmented bit line configuration, a total of 64M is used for 8k word lines × 8k bit line pairs.
Make up the bits. These are known examples (M.Naka
mura et al., "A 29 ns 64 Mb DRAM with hierarchical
array architecture, "in ISSCC Dig.Tech.Papers, Fe
b.1995, pp.246-247.).

In the memory chip 10, a main word line for controlling the sub-word driver 17 and a pre-decoder line from the main row decoder region 11 and the main word driver region 12 at the center of the long side are output to the left and right. The center of the short side is a peripheral circuit / bonding pad area 14 between the memory cell sub-array 15 and the column decoder 1.
3 is placed. A column selection signal line, which is an output of the column decoder 13, passes over the memory cell sub-array 15 and controls a large number of sense amplifiers 16. Reference numeral 15 denotes a divided memory cell sub-array, which comprises 256 W × 256 BL pairs.

As shown in the partial enlarged view of FIG. 1B, sub-word drivers 17 are arranged on both left and right ends of the memory cell sub-array 15, and sense amplifiers 16 are arranged on both upper and lower sides. Therefore, the memory cell sub-array 15 is surrounded by the sense amplifier 16 and the sub-word driver 17. An area where the sub-word driver 17 and the sense amplifier 16 intersect is called an intersection area 18 and a sense amplifier driver and an IO switch circuit are provided. It is necessary to supply a low-resistance power supply line from a power supply pad to the sense amplifier driver MOS transistor in the intersection region 18, which is a problem.

Next, a circuit configuration of the memory cell sub-array 15 and its direct peripheral circuits, ie, the sense amplifier 16, the sub-word driver 17, and the intersection area 18, will be described with reference to FIG. FIG. 2A is a circuit diagram, and FIG. 2B is a layout diagram. Hierarchical word line system, shared sense amplifier system (system in which sense amplifier 16 is shared by upper and lower memory cell sub-arrays 15), distributed sense amplifier system (system in which sense amplifier driver is arranged in intersection area 18 between sense amplifier 16 and sub-word driver 17) ), Overdrive sense amplifier system (overdrive voltage is VD
DCLP, final cell storage voltage is VDL)
Is assumed.

In the hierarchical word line system, the repetition pitch (width + space) of the metal wiring (main word line) is set to, for example, 8 times the sub word line pitch of the memory cell sub array 15.
In other words, the manufacturing yield of the metal wiring is increased. In the sub-word driver 17, the main word line MW
B and the predecoder lines FXB, FX,
The sub word line is driven at the P level (3.8 V). The sense amplifier 16 amplifies the bit line signal, and finally rewrites the storage voltage VDL (2.0 V) to the memory cell. At this time, the sense amplifier 16 employs an overdrive method, is driven at a transiently high voltage VDDCLP (3.3 V), and prevents a decrease in speed when the sense amplifier 16 is driven only at a low voltage VDL.

The column selection is performed by the column selection signal line YS output from the column decoder 13, and the column selection signal line YS is set to High.
During the period of h, the switch MOS transistor in the sense amplifier 16 is turned on, and the bit lines BL and BLB are connected to the local IO.
Connection with lines LIO and LIOB is performed. I at intersection area 18
The O switch connects the local IO lines LIO, LIOB to the main IO lines MIO, MIOB, and transfers read / write information between the bit line BL and the local IO line LI.
This is performed between the O-main IO line MIO. The intersection area 18 mainly includes a sense amplifier driver including an FX driver, a CSP driver, a CSPN equalizer, a CSN driver, and the like (Odd), an FX driver, a LIO-M
IO switch, MIO equalizer, CSN driver, L
A switch mainly including an IO switch including an IO equalizer and a BLEQB driver (Even) is alternately arranged. This is because the layout is efficiently performed when the intersection region 18 requires a large variety of circuits for a small area.

In FIG. 2, the power supply line of VDDCLP is V
This is the source-side voltage applied to the PP gate. There are two reasons for using VDDCLP for the overdrive voltage. First
Is to alleviate the dependency of the overdrive sense amplifier on the power supply voltage VDD. The voltage of VDDCLP is VP
Controlled by P, VPP is a word line boosted voltage, and is substantially constant with respect to VDD change except for the aging region. Therefore, there is a function of alleviating a speed change due to a change in VDD. The second is measures against latch-up. Under the memory cell sub-array 15, the sense amplifier 16, and the sub-word driver 17, a triple well deep D
There is a WELL to which the highest VPP in circuit operation is applied. However, since VPP is gradually increased by the charge pump operation when the VDD power is turned on, a situation where VPP is lower than VDD may occur transiently. At this time, when the PMOS transistor of the sense amplifier 16 performs the VDD operation,
Although there is a possibility of latch-up, if VDDCLP is used for the sense amplifier driving MOS transistor and the BLEQB driver in the intersection region 18, VDDCLP rises later than VPP, so that it is safe for the latch amplifier.

VDDCLP, VDL, VSSA, VSS are provided on the intersection area 18 and the sub-word driver 17 in FIG.
The third-layer metal wiring M3 is arranged in the vertical direction in FIG. 2 so that various power lines such as the main IO line MIO and the predecoder line FXB are mixed. Therefore, the width of each power supply line cannot be sufficiently secured as 3 to 4 μm, the resistance of the power supply line from the power supply pad increases, and the advantage of the distributed sense amplifier driver cannot be enjoyed.

In FIG. 2, SHR and SHRB are shared sense amplifier separation signal lines, SAP1 is a first sense amplifier charge signal line for overdrive, SAP2 is a second sense amplifier charge signal line, and SAN is a sense amplifier discharge signal line. Lines, BLEQ and BLEQB indicate bit line equalizing signal lines, CSP and CSN indicate sense amplifier drive lines, and SW indicates a sub-word line.

FIG. 3 shows a hierarchical word line system.
3A is a schematic diagram showing a hierarchical word line on the memory cell sub-array 15, and FIG. 3B is a layout diagram. The logic is taken by the main word line MWB and the predecoder line FXB. For example, when the memory cell sub-array 15 has 256 sub-word lines, the logic is performed by 32 main word lines MWB and 8 pre-decoder lines FXB, and one of the 256 is selected. 1 in the subword driver area 17
There are 28 sub-word drivers, and 128 sub-word drivers are alternately arranged on the memory cell sub-array 15 in adjacent sub-word driver regions 17. Each main word line MWB is input to four sub-word driver circuits in each sub-word driver area 17. Each predecoder line F
XB is input to 32 sub-word driver circuits in each sub-word driver area 17. Therefore, when viewed as a load capacitance, the predecoder line FXB is larger than the MWB, and from the circuit operation of the sub word driver 17,
The path from the fall of XB to the rise of FX becomes the access critical path.

4 and 5 show a sub-word driver circuit. FIG. 4 (a) is a circuit diagram showing a sub-word driver, FIG. 4 (b) is a waveform diagram, and FIG. 5 is a layout diagram. Main word line MWB driver and predecoder line FXB
Are arranged in the row decoder and the array control area. The predecoder line FXB is arranged so as to cover the gap between the MWB drivers. MWB only one, FXB
Are allocated, and a total of 32 + 8 × 2 = 48 second-layer metal wires M2 are arranged on the memory cell sub-array 15. In addition, on the memory cell sub-array 15, 48 are evenly arranged. Therefore, the metal pitch relaxation is 256 / (32 + 8) = 6.4 times in the related art, but 256 / (32 + 16) = 5.33 times in the present invention. For example, the size of the memory cell sub-array 15 is 0.5 μm × 1.1.
When μm, the M2 pitch is 0.5 × 5.31 = 2.67 μm
m. For example, there may be a choice of a width of 1.2 μm and an interval of 1.47 μm. This is a value (pitch relaxation of 4 or more and 8 or less) that is sufficiently allowable to keep the advantages of the hierarchical word line system still in use. Resistance reduction of predecoder line FXB (2
According to the present invention, the word access time can be improved to 0.4 to 0.5 ns.

FIG. 6 shows an outlet of the sub-word driver 17, and FIGS. 6 (a) and 6 (b) are pattern diagrams showing a conventional example.
FIG. 6C is a pattern diagram showing an example of the present invention. The left side corresponds to a layout pattern and a mask pattern, respectively.
The right side corresponds to a developed pattern and a finished pattern. The output wiring of the sub-word driver 17 uses the bit line layer BL or the first metal wiring layer M1 in the circuit, and then makes contact at the boundary between the sub-word driver 17 and the memory cell sub-array 15, and the gate layer F of the MOS transistor.
Converted to G. In the conventional example, a dog bone causes a short circuit as shown in FIG. In FIG. 6 (b) of another conventional example, since the center of the contact is separated by more than the contact size, short-circuiting of the adjacent sub word line is unlikely to occur.
The size of the sub-word driver 17 becomes large.
In particular, the contact is on both sides of the region and therefore has a double effect. Furthermore, since there are 34 sub-word drivers 17 in the long side direction in the chip, the influence on the chip area is large. On the other hand, in the example of the present invention, the center of the contact is slightly shifted as shown in FIG.
The increase in size is also smaller than in FIG. Therefore, the yield and the dimensions can be exactly matched.

FIG. 7 shows the sense amplifier 16 and FIG.
(a) is a circuit diagram, and (b) is a layout diagram. Two adjacent sense amplifiers 16 are controlled by one column selection signal line YS. Interposing one power supply line PS between two column selection signal lines YS can be arranged without deteriorating the wiring yield. On the memory cell sub-array 15, the third layer metal wiring M3 has (64 + 32) 96
Place a book. 32 is the maximum possible number and is left empty when not needed. At this time, the pitch relaxation degree of the metal wiring is 5.33 times the bit line pitch because three wirings are provided for each pair of 8 bit lines (16 bit lines). Is the same as Normally, the pitch between the gate layer word line and the bit line BL is the same or the bit line BL is large, so that the pitch relaxation between the second layer metal wiring M2 and the third layer metal wiring M3 is about the same or slightly M3 is loose. It is just a good degree in process processing. For example, the size of a memory cell is 0.5 μm (WL)
× 1.1 μm (2BL), the M3 pitch is 0.55
× 5.33 = 2.94 μm. 1.3μm width, 1.64 spacing
There may be a choice of μm.

4 and 5 and FIG. 7, the pitch of the second-layer metal wiring M2 <the pitch of the third-layer metal wiring M3 can be satisfied. Generally, the third layer metal wiring M3 is used for a power supply or a long signal wiring on a chip,
In particular, since it is necessary to lower the resistance, it is made thicker than the second-layer metal wiring M2 and the first-layer metal wiring M1. For example, M3, M2, M
1 have a thickness of 0.7 μm, 0.5 μm, and 0.3 μm, respectively. Accordingly, it is desirable from the viewpoint of manufacturing yield that the space for the third-layer metal wiring M3 be larger than the space for the second-layer metal wiring M2 in the processing.

FIGS. 8A and 8B show wirings on the memory cell sub-array 15. FIG. 8A is a schematic diagram, FIG. 8B is a layout diagram, and FIG. 8C is an enlarged diagram. Memory cell sub-array 1
5 is a configuration of 256 W × 256 BL pairs = 64 k bits. The horizontal direction is the second-layer metal wiring M2, which is composed of two main word lines MWB and one predecoder line FXB. The vertical direction is the third-layer metal wiring M3, and three units of two of the column selection signal lines YS and one of the power supply wirings PS are used as a unit. The third-layer metal wiring M3 in the vertical direction is
It can be used for other internal power supply lines and pulse signal lines other than VDD and VSS. Even if the width of each line is small, if a plurality of lines are used together, the total width can be made larger than the width of the power supply wiring on the sub-word driver 17, so that the effect of reducing the resistance is great. Note that 1RM in FIG.
WB and 1RYS are main word lines for redundancy, respectively.
4 shows a column selection signal line.

As shown in FIG. 8C, for example, the dimension in the word line direction of the memory cell sub-array 15 is 0.5 μm ×
When 256W = 128 μm, the second layer metal wiring M
Since (32 + 16) wirings are arranged as 2
2 is 2.67 μm, the wiring width is 1.2 μm,
The spacing can be 1.47 μm. On the other hand, the dimension in the bit line direction is 0.55 μm × 256 BL = 282 μm.
m, (64 + 3)
2) Since three wires are arranged, the pitch of M3 is 2.94.
μm, so that the wiring width can be 1.3 μm and the interval can be 1.64 μm.

FIG. 9 is a layout diagram showing the wiring intersection processing on the end of the memory cell sub-array 15 on the chip outer periphery and the sense amplifier 16. Memory cell sub-array 15
The power supply line of the third-layer metal wiring M3 that passes through the upper wiring in parallel with the column selection signal line YS may be changed in direction by 90 degrees by a through hole on the memory cell sub-array 15, but it corresponds to the sense amplifier. If there is no horizontal wiring and it cannot be done, it is temporarily extended to the chip outer periphery, connected to the guard ring line existing there, and distributed sense amplifiers in the intersection region 18 via the power supply line on the sub-word driver 17. The power is connected to the driving MOS transistor. In this way, the wiring resistance of the power supply line can be reduced for a large-scale array.

This guard ring line is located between the memory cell sub-array 15 and the scribe area. In this example, there are three guard ring wires, of which the outer and middle wires are for manufacturing reliability (to prevent moisture from entering the chip).
To VDD (n + power supply) and VSS (P-Sub power supply). In order to secure a space between the memory cell sub-array 15 and the base on the inside, the wiring may be freely designed for all three layers. For example, the third-layer metal wiring M3 is VSSA, the second-layer metal wiring M2 is VDDCLP, and the first-layer metal wiring M1 is VSA.
Used for BB. VPP, VBLR, and VSS are connected to the driver circuit in the intersection region 18 by using a through hole on the sense amplifier 16 and a second-layer metal wiring M2 in the horizontal direction on the sense amplifier 16. VPLT is a plate voltage supply line, and is not particularly limited. VSSA (for the memory cell sub-array 15) and VSS (for a general circuit) have the same external pins, but are separated after the pads to prevent noise interference. .

In FIG. 9, 32 power supply lines can be originally arranged on the memory cell sub-array 15 and the sense amplifier 16, but VDDCLP, VPP, VBLR are arranged on the left memory cell sub-array 15. ,
Twenty VSS and VSSA are arranged, four each, and VPP, VBLR, V
Sixteen SSs and four VSSAs are arranged. The power supply line of VDDCLP is not arranged on the memory cell sub-array 15 on the right side. However, as shown in FIG.
This is because P is required.

FIG. 10 is a schematic diagram schematically showing one power supply wiring in the entire chip. With vertical lines,
The wiring on the memory cell sub-array 15 indicated by the broken line and the wiring on the sub-word driver 17 indicated by the solid line intersect the outer peripheral guard ring line at the upper and lower ends of the chip and are short-circuited by through holes. The wiring on the memory cell sub-array 15 is thin, but a large number of wirings can be taken, thereby contributing to lowering the resistance as a whole. Accordingly, the power supply wiring resistance from the power supply pad at the center of the chip to the driver MOS transistor in the intersection region 18 of the memory cell subarray 15 at the far end near the upper and lower ends of the chip is reduced, contributing to the high-speed stable operation of the sense amplifier 16. Can be. Alternatively, instead of a direct power supply from the outside, the connection of the output voltage of the internal power supply circuit in the center of the chip may be used.

FIG. 11 is different from FIG.
FIG. 11A is a schematic diagram showing wiring on the memory cell sub-array 15, and FIG.
(b) shows a layout diagram. Main word line MWB is 6
4 lines, 16 predecoder lines FXB (8 types x 2 lines)
Thus, one of 512 can be selected. In the horizontal direction, a further 16 lines are used as power lines such as VDD and VSS, through holes are provided on the memory cell sub-array 15, and the third-layer metal wiring M3 and the second-layer metal wiring M2 are conducted. In this way, if 64 + 32 = 96 lines are placed in 512 sub-word lines, the pitch relaxation degree is 5.31.
8 and the same as FIG. Further, the power supply lines can be meshed using the through holes on the memory cell sub-array 15.

In the example of the 512W × 512BL pair, for example, when the dimension of the memory cell sub-array 15 in the word line direction is 0.5 μm × 512W = 256 μm,
Since (64 + 32) wires are arranged as the second-layer metal wires M2, the pitch of M2 is 2.67 μm, the width of the wires can be 1.2 μm, and the interval can be 1.47 μm. On the other hand, the dimension in the bit line direction is 0.55 μm × 5
When 12BL × 2 = 563 μm, since (128 + 64) wirings are arranged as the third-layer metal wiring M3, the pitch of M3 is 2.94 μm and the width of the wiring is 1.3.
μm and the interval can be 1.64 μm.

Therefore, according to the semiconductor memory device of the present embodiment, the main word line M
When logic is taken between WB and predecoder line FXB, MW
By allocating only one line to B and two lines to FXB and arranging them on the memory cell sub-array 15, the word resistance can be reduced by lowering the resistance of the predecoder line FXB while maintaining a sufficient metal pitch in the hierarchical word line system. The system access time can be improved.

The power supply line of the third-layer metal wiring M3, which has passed through in parallel with the column selection signal line YS, once extends to the outer periphery of the chip, and is connected to the guard ring line existing there. By connecting the power supply to the sense amplifier driving MOS transistor in the crossing region 18 via the power supply line, the wiring resistance of the power supply line for a large-scale array can be reduced.

Further, by slightly shifting the contact center within the range of the contact diameter at the outlet of the sub-word driver 17, it is possible to prevent a short circuit in the dog bone portion and to reduce the increase in the layout size of the sub-word driver 17. it can.

Further, the wiring width on the memory cell sub-array 15 is made uniform, and the spacing is also made equal, so that the second
The pitch between the layer metal wiring M2 and the third layer metal wiring M3 can be relaxed with good balance.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, 6
The case where the present invention is applied to a 4Mb DRAM has been described, but the present invention is not limited to this.
And other large-capacity DRAMs, and synchronous DRAMs
The present invention can be widely applied, and the effect of the present invention is further increased by adopting such a large capacity configuration.

[0055]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) In the hierarchical word line system configuration, when the logic is performed by the main word line and the predecoder line, the number of signal lines is doubled for the signal lines on the minority side, and While still taking advantage of the word line pitch relaxation,
It is possible to reduce the wiring resistance of the predecoder line and shorten the access time for selecting the sub word line.

(2) The through hole of the wiring parallel to the column selection signal line is not placed on the memory cell sub-array, but on the sense amplifier. Shunt and
By realizing the mesh power supply effectively, it is possible to reduce the resistance of the power supply wiring to the sense amplifier driver.

(3) By slightly displacing the contact centers within the range of the contact diameter so that the contact centers do not completely oppose each other, short-circuiting between adjacent sub-word lines does not occur at the dogbone portion of the output extraction contact of the sub-word driver.
In addition, since the dimensions do not become extremely large, it is possible to select a good compromise between the area and the yield.

(4) The wiring width on the memory cell sub-array is also equal, the spacing is equal, and the spacing is larger than the width, so that the second-layer metal wiring and the third-layer metal wiring are balanced. The pitch can be relaxed. In this case, since the bit line pitch is slightly larger than the word line pitch, the third-layer metal wiring pitch can be slightly larger than the second-layer metal wiring pitch.

[Brief description of the drawings]

FIGS. 1A and 1B are a schematic layout diagram and a partially enlarged view showing a semiconductor memory device according to an embodiment of the present invention.

FIGS. 2A and 2B are a circuit diagram and a layout diagram showing a peripheral circuit directly around a memory cell in a semiconductor memory device according to an embodiment of the present invention;

FIGS. 3A and 3B are a schematic diagram and a layout diagram showing hierarchical word lines on a memory cell sub-array in a semiconductor memory device according to an embodiment of the present invention.

FIGS. 4A and 4B are a circuit diagram and a waveform diagram showing a sub-word driver in a semiconductor memory device according to an embodiment of the present invention.

FIG. 5 is a layout diagram showing a sub-word driver in the semiconductor memory device according to one embodiment of the present invention;

FIGS. 6A to 6C are pattern diagrams showing a conventional example of a subword outlet and an example of the present invention in a semiconductor memory device according to an embodiment of the present invention;

FIGS. 7A and 7B are a circuit diagram and a layout diagram showing a sense amplifier in a semiconductor memory device according to an embodiment of the present invention; FIGS.

FIGS. 8A to 8C are a schematic diagram, a layout diagram, and an enlarged diagram showing wirings on a memory cell sub-array in a semiconductor memory device according to an embodiment of the present invention.

FIG. 9 is a layout diagram showing a wiring intersection process on a memory cell sub-array end and a sense amplifier in the semiconductor memory device according to one embodiment of the present invention;

FIG. 10 is a schematic diagram showing power supply connection of the entire chip in the semiconductor memory device according to one embodiment of the present invention;

FIGS. 11A and 11B are a schematic diagram and a layout diagram showing another wiring on a memory cell sub-array in the semiconductor memory device according to the embodiment of the present invention; FIGS.

[Explanation of symbols]

 Reference Signs List 10 memory chip 11 main row decoder area 12 main word driver area 13 column decoder area 14 peripheral circuit / bonding pad area 15 memory cell sub-array 16 sense amplifier area 17 sub-word driver area 18 intersection area BL, BLB bit line BLEQ, BLEQB bit line equalization Signal line CSP, CSN Sense amplifier drive line FX, FXB Predecoder line LIO, LIOB Local IO line MIO, MIOB Main IO line MWB Main word line PS Power supply line SAN Sense amplifier discharge signal line SAP1, SAP2 Sense amplifier charge signal line SHR, SHRB Shared sense amplifier separation signal line SW sub word line YS column selection signal line

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshiji Ueda 5-2-2-1, Kamisumihonmachi, Kodaira-shi, Tokyo Inside Hitachi Cho-SII Systems Co., Ltd. (72) Inventor Manabu Ishimatsu Tokyo 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Super LSI Systems

Claims (9)

[Claims] 1. A semiconductor memory device including a memory cell sub-array, a sense amplifier and a sub-word driver arranged adjacent to the memory cell sub-array, and an intersection region between the sense amplifier and the sub-word driver, wherein Discharge is performed by the sense amplifier driving MOS transistors dispersed in the intersection area, and power is supplied to the sense amplifier driving MOS transistors to a normal power supply wiring on the sub-word driver. A power supply line in parallel with the selection signal line, connected by a through hole at an intersection with a guard ring portion around the chip, and connected with a low resistance from a power supply pad or an internal power supply circuit in the central portion of the chip to the intersection region A semiconductor memory device using a supply method. 2. The semiconductor memory device according to claim 1, wherein a power supply wiring on said memory cell sub-array has a ratio of one power supply line to two of said column selection signal lines.
A semiconductor memory device in which two column selection signal lines control two sense amplifiers in a sense amplifier column. 3. The semiconductor memory device according to claim 2, wherein a metal pitch used for a power supply wiring on said memory cell sub-array and said column selection signal line is four times a bit line pitch on said memory cell sub-array region. A semiconductor memory device characterized by being at least twice and at most eight times. 4. The semiconductor memory device according to claim 3, wherein said column selection signal lines and said power supply lines are arranged at substantially equal widths / intervals on said memory cell sub-array. . 5. A semiconductor memory device including a memory cell sub-array, a sense amplifier and a sub-word driver arranged adjacent to the memory cell sub-array, and an intersection area between the sense amplifier and the sub-word driver. A line (MWB) and n predecoder lines (FXB) perform a logical operation with the sub-word driver, and (m × n)
In the hierarchical word line system in which one is selected from the sub word lines, when there is a relation of m >> n in the logical operation, the speed of the wiring layout on the memory cell sub array is reduced by a low resistance. A semiconductor memory device using a hierarchical word line system in which two memory cells are used and the main word lines and the predecoder lines are combined (m + 2n) on the memory cell sub-array. 6. The semiconductor memory device according to claim 5, wherein said (m + 2n) signal lines are arranged at substantially equal widths / intervals on said memory cell sub-array. 7. The semiconductor memory device according to claim 6, wherein m × n / (m + 2n) which is a metal pitch (width + interval) of wiring on said memory cell sub-array is 4 or more and 8 or more.
A semiconductor memory device characterized by the following. 8. The semiconductor memory device according to claim 2, wherein a second layer metal wiring parallel to said main word line (MWB) is provided on said memory cell sub-array, and a second layer metal wiring parallel to said column selection signal line. A semiconductor memory device, wherein the pitch of the third-layer metal wiring is set slightly larger than the pitch of the second-layer metal wiring. 9. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is a DRAM.