JP2000124415A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory device of layout technique, where a sense amplifier can be made to operate at a high speed reducing an increase in the area of the sense amplifier to an irreducible minimum through a sense amplifier driver dispersed installation method. SOLUTION: A four-bank 256 Mbit DRAM is composed of a four-bank memory cell array region, an array controller region and a Y decoder region corresponding to the memory cell array region, and a common peripheral circuit region. NMOS transistors M3 and M4 in an N channel side sense amplifier circuit 14 and an NMOS transistor M1 in a pull-down side sense amplifier driver circuit 18 are laid out through a manner where the gates G of the NMOS transistors M3 and M4 are formed in the shape of a letter U, the NMOS transistor M1 is arranged between the gates G, furthermore the gate G of the NMOS transistor M1 is divided in two, and a part of a diffusion layer L is removed. A P channel is the same as above.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout technology for a semiconductor memory device, and more particularly to a so-called sense amplifier driver distributed arrangement method in which driver MOS transistors for driving a sense amplifier are dispersedly arranged in the sense amplifier. The present invention relates to a technology effective when applied to a semiconductor memory device.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, in a DRAM as an example of a semiconductor memory device, a driver MOS transistor for driving a sense amplifier is provided for each memory mat, for example, 256 or 512 MOS transistors. A technique of arranging about one per sense amplifier is conceivable.

[0003] As a technique related to such a semiconductor memory device such as a DRAM, for example,
The technology described in “Advanced Electronics I-9 Ultra LSI Memory” issued by Baifukan Co., Ltd. on May 5 is included.

[0004]

By the way, in the DRAM as described above, the most effective means for increasing the speed of the sense amplifier is to increase the constant of the MOS transistor for the sense amplifier driver. However, it is considered that it is difficult to increase the execution driver constant of the sense amplifier driver MOS transistor due to the limitation of the layout area.

On the other hand, a sense amplifier driver M
By arranging one OS transistor in each sense amplifier, it is possible to increase the effective driver constant without demerit in layout and to increase the speed. This is a layout technique called a sense amplifier driver distributed arrangement method.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device of a layout technology which uses a sense amplifier driver distributed arrangement method to minimize an increase in the area of a sense amplifier portion and to operate a sense amplifier at high speed. Is provided.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor memory device according to the present invention uses the sense amplifier driver distributed arrangement method and has the following features.

(1). MOs for Two N-Channel Sense Amplifiers
S transistor, MO for two P-channel sense amplifiers
Forming the gate of the S transistor in a U-shape on the diffusion layer,
And N-channel sense amplifier MOS transistor, P
Between the channel sense amplifier MOS transistors, the N channel side or P channel side sense amplifier driver MOS transistors are arranged by sharing the diffusion layer.

(2) A plurality of, for example, two, gates of the MOS transistor for the sense amplifier driver are provided separately.

(3) A metal wiring layer is shunted on a plurality of gates of the sense amplifier driver MOS transistor.

(4) Part of the diffusion layer of the sense amplifier driver MOS transistor is removed. At the portion where the diffusion layer is removed, a plurality of gates are connected or a diffusion layer of a sense amplifier MOS transistor is connected.

Therefore, according to the semiconductor memory device, the following operation and effect can be obtained.

(1). N-channel and P-channel sense amplifier MOS transistors and sense amplifier driver MOS
Since the diffusion layer of the transistor is common, an increase in the area of the sense amplifier can be minimized.

(2) By providing a plurality of gates, the effective driver constant of the sense amplifier driver MOS transistor is doubled, so that the sense amplifier can be operated at high speed.

(3) By using a metal wiring layer having a low resistance as a shunt, the gate input signal of the sense amplifier driver is propagated at high speed, so that the sense amplifier can be operated at high speed.

(4) Since it is possible to change the execution driver constant while keeping the area constant, the operation speed and power consumption of the sense amplifier can be adjusted.

As a result, the cost can be reduced by reducing the area of the entire chip, and the speed of the sense amplifier can be increased. In particular, it is effective for DRAMs and LSIs with DRAMs, and can also be used as a high-speed technology for analog circuits and low-voltage driven LSIs.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic layout diagram showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a schematic layout diagram showing a sense amplifier in the semiconductor memory device of the embodiment, and FIG. FIG. 4 is a layout diagram showing a sense amplifier driver distributed arrangement system, FIG. 5 is a layout diagram showing a metal wiring layer, FIG. 6 is a layout diagram showing a metal wiring layer shunted on a gate, 7 is a layout diagram showing a gate connection, FIG. 8 is a layout diagram showing a diffusion layer connection, and FIG. 9 is a circuit diagram showing a sense amplifier driver distributed arrangement system in which one driver is arranged for one sense amplifier.

First, a schematic layout configuration of an example of the semiconductor memory device according to the present embodiment will be described with reference to FIG.

The semiconductor memory device according to the present embodiment is, for example, as shown in FIG.
And a memory cell array region 1 having a four-bank configuration of bank 0 to bank 3, and array controller regions 2 and Y arranged corresponding to each memory cell array region 1.
A decoder region 3 and a peripheral circuit region 4 commonly arranged in each memory cell array region 1 are formed on one semiconductor chip by a known semiconductor manufacturing technique. In FIG. 1, the vertical direction is the row direction (word line direction), and the horizontal direction is the column direction (bit line direction).

In this DRAM, the semiconductor chip is divided into upper and lower sides in the row direction and right and left sides in the column direction, and the memory cell array region 1 is further divided into two in each divided region. These two divided memory cell array regions 1 correspond to one bank, and are arranged in pairs with an array controller region 2 corresponding to each memory cell array region 1 interposed therebetween. A Y-decoder region 3 corresponding to each memory cell array region 1 is arranged at the center side of each of the two divided memory cell array regions 1, and a row address buffer (not shown) is further provided as a peripheral circuit region 4 at the center side. , A column address buffer, a predecoder, a timing generation circuit, a data input / output circuit, and the like.

Each of the memory cell array regions 1 is divided into a grid in a row direction and a column direction as shown in FIGS. 1 (b) and 1 (c), and a memory cell array 5, a sense amplifier array 6, and a sub-word array 7 are formed. A sense amplifier array 6 is arranged adjacent to the memory cell array 5 in the column direction, and a sub-word array 7 is arranged adjacent to the memory cell array 5 in the row direction. In the cross area 8, an FX driver and a control circuit for a sense amplifier group are also arranged.

The sense amplifier array 6 in each memory cell array region 1 is composed of a plurality of sense amplifier (SA) rows, as shown in an example in FIG. 2, for example. 1 shows an example in which one sense amplifier driver is allocated and arranged. Shared sense amplifier separation circuits 11 and 12 for separating adjacent memory cell arrays 5 and a bit line precharge circuit 1 for precharging complementary bit lines are provided in the sense amplifier and sense amplifier driver regions.
3. N-channel and P-channel sense amplifier circuits 14 and 15 for detecting and amplifying the signal of the complementary bit line, column selection for connecting the complementary bit line and the input / output line by gate control of the column selection signal Circuit 16 and substrate feeding circuit 1
7, a pull-down sense amplifier driver circuit 18 for driving the N-channel sense amplifier circuit 14, and a pull-up sense amplifier driver circuit 19 for driving the P-channel sense amplifier circuit 15 are arranged.

FIG. 3 shows an example of a circuit configuration of a sense amplifier driver distributed arrangement system in which one sense amplifier driver is assigned to these three sense amplifiers.
It is. The sense amplifier driver includes an N-channel (hereinafter simply referred to as N) MOS transistor M1 (M1a, M1b) of the pull-down side sense amplifier driver circuit 18 and a P-channel (hereinafter simply referred to as P) MOS transistor of the pull-up side sense amplifier driver circuit 19. Transistor M2 (M2
a, M2b). The sense amplifiers are NMOS transistors M3, M of the N-channel side sense amplifier circuit 14.
4. PMOS transistors M5 and M6 of P channel side sense amplifier circuit 15, shared sense amplifier separation circuit 1
1 and 12, NMOS transistors M7 to M10, and bit line precharge circuit 13 with NMOS transistor M11
To M13.

In FIG. 3, BL-T *, BL-
B * (* = 1 to 3) are bit lines, SHR-L, SHR-
R is the shared sense amplifier separation signal line of the shared sense amplifier separation circuits 11 and 12, BLEQ is the bit line precharge signal line of the bit line precharge circuit 13, and VBL
R is a bit line precharge voltage, CSN and CSP are sense amplifier drive lines for the sense amplifier circuits 14 and 15, SA
N and SAP indicate a sense amplifier charge / discharge signal line, VSSA indicates a ground voltage, and VDL indicates a bit line voltage.

In particular, in the present embodiment, the layout of the sense amplifier and the sense amplifier driver is devised. This will be described in detail with reference to FIGS. 4 shows an example of a gate layer and a diffusion layer of a sense amplifier driver distributed arrangement system, FIG. 5 shows an example of an upper metal wiring layer of FIG. 4, and FIG. 6 shows an example of a metal wiring layer shunting on the upper gate of FIG. , And shows four sense amplifiers in which three sense amplifiers and one adjacent sense amplifier are added.

In FIG. 4, the layout of the NMOS transistors M3 and M4 of the N-channel sense amplifier circuit 14 and the NMOS transistor M1 of the pull-down sense amplifier driver circuit 18, and the PMOS transistors M5 and M5 of the P-channel sense amplifier circuit 15 M6 and the PMO of the pull-up side sense amplifier driver circuit 19.
The layout of the S transistor M2 will be described.

First, the N-channel side sense amplifier circuit 14
With regard to the layout of the NMOS transistors M3 and M4 and the NMOS transistor M1 of the pull-down side sense amplifier driver circuit 18, first, the gates G of the NMOS transistors M3 and M4 are formed on the diffusion layer L forming the source and the drain. Is formed in a U-shape, and 180
It is rotated and turned to face each other. Thus, the gate G
Is formed in a U-shape, so that the diffusion layer L constituting the source of the NMOS transistors M3 and M4 is
It can be shared between the S transistors M3 and M4.

Second, the NMOS transistor M1 of the pull-down side sense amplifier driver circuit 18 is disposed between the NMOS transistors M3 and M4 of the sense amplifier circuit 14. Thus, by disposing the NMOS transistor M1 between the NMOS transistors M3 and M4, the diffusion layer L forming the source and the drain can be shared with the diffusion layer L of the NMOS transistors M3 and M4 of the sense amplifier circuit 14. it can.

Third, the NMOS transistor M1 of the pull-down side sense amplifier driver circuit 18 has two gates G (M1a, M1b) separated from each other, and connects the diffusion layer L constituting the source to the ground voltage VSSA. Connection side and sense amplifier drive line CSN of diffusion layer L forming the drain
Can be separated from the connection side. By thus dividing the gate G into two, the execution driver constant of the NMOS transistor M1 can be doubled.

Fourth, the diffusion layer L forming the source and drain of the NMOS transistor M1 of the pull-down side sense amplifier driver circuit 18 has a part (A part) overlapping with the gate G separated into two parts removed. It is arranged in a rectangular shape. By removing the diffusion layer L in this manner, the effective driver constant can be changed while keeping the chip area constant.

In FIG. 5, N of the sense amplifier circuit 14
The diffusion layers L forming the drains of the MOS transistors M3 and M4 are respectively connected to the first metal wiring layers M through contacts.
L1 is connected using the sense amplifier drive line CS
N. Further, the diffusion layers L constituting the sources of the NMOS transistors M3 and M4 are connected to each other via the contacts using the first metal wiring layer ML1, and become bit lines BL-T * and BL-L *, respectively.

In FIG. 6, the gate G of the NMOS transistor M1 of the pull-down side sense amplifier driver circuit 18 is shunted on the gate G via a contact by the second metal wiring layer ML2, which is connected to the sense amplifier charge / discharge signal line SAN. Becomes In this manner, the second metal wiring layer ML2 having a low resistance can be used for the sense amplifier charge / discharge signal line SAN which is an input signal of the sense amplifier driver circuit 18. This is the fifth point.

As described above, the NMOS transistors M3 and M4 of the N channel side sense amplifier circuit 14 and the NMO of the pull down side sense amplifier driver circuit 18
The first to fifth five devices are applied to the layout with the S transistor M1.

The P channel side sense amplifier circuit 15
The layout of the PMOS transistors M5 and M6 of the pull-up side and the PMOS transistor M2 of the pull-up side sense amplifier driver circuit 19 is also the same as that described above.
The first, in which the gates G of the OS transistors M5, M6 are formed in a U-shape, the second, in which the PMOS transistor M2 is disposed between the PMOS transistors M5, M6, the gate G of the second, PMOS transistor M2 is separated into two. Third, P
A fourth gate G of the PMOS transistor M2 in which a part (part B) of the diffusion layer L of the MOS transistor M2 is removed.
Are shunted by the second metal wiring layer ML2.

Therefore, according to the present embodiment, the NMOS
Transistors M3 and M4, PMOS transistors M5
The gate G of M6 is formed in a U-shape, and the NMOS transistor M1 and the PMOS transistor M2 are respectively formed by NMOS.
Transistors M3 and M4, PMOS transistors M5
By disposing it between M6, the sense amplifier circuit 1
The diffusion layers L of the sense amplifier driver circuits 18 and 19 and the sense amplifier driver circuits 18 and 19 become common, and an increase in the area can be minimized.

Further, the NMOS transistors M1, PM
By separating the gate G of the OS transistor M2 into two, the execution driver constant of the sense amplifier driver circuits 18 and 19 is doubled, and the sense amplifier circuits 14 and 15 are doubled.
Can be operated at high speed.

Further, the NMOS transistor M1, the PMO
By removing a part of the diffusion layer L of the S transistor M2, the effective driver constants of the sense amplifier driver circuits 18 and 19 can be changed while keeping the chip area constant, and the operating speed of the sense amplifier circuits 14 and 15 can be changed. And the current consumption can be adjusted.

Further, the NMOS transistors M1, PM
The gate G of the OS transistor M2 is connected to the second metal wiring layer ML.
2, the input signals of the sense amplifier driver circuits 18 and 19 operate at high speed, and the sense amplifier circuits 14 and 15 are used.
Can be operated at high speed.

When a part of the diffusion layer L of the sense amplifier driver circuits 18 and 19 is removed as in the above embodiment, for example, as shown in FIG. Two gates G can be connected at the portions where the 19 diffusion layers L are removed (portions A and B) (portions C and D). In this case, it is not necessary to connect the two gates G by the first metal wiring layer ML1 as shown in FIG. Thus, the first metal wiring layer ML1 for connecting the two gates G can be used as another wiring, and an increase in the chip area due to the wiring can be prevented.

Further, for example, as shown in FIG. 8, the sense amplifier circuits 14, 1 are formed at portions (A, B) of the sense amplifier driver circuits 18, 19 from which the diffusion layer L is removed.
5, the sense amplifier drive line CSN of the two NMOS transistors M3 and M4, and the two PMOS transistors M5 and M5.
The M6 sense amplifier drive lines CSP can be connected by the diffusion layers L (E and F portions). In this case,
It is not necessary to connect the first metal wiring layer ML1 as shown in FIG. As a result, the first metal wiring layer ML1 can be used for connection to the gate input, the ground voltage VSSA, and the bit line voltage VDL side, which is advantageous for speeding up the sense amplifier circuits 14 and 15.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, 3
Although an example of a circuit configuration in which one sense amplifier driver is assigned to one sense amplifier has been described above,
In consideration of the execution driver constant, the chip area, and the like, a sense amplifier driver distributed arrangement method in which one sense amplifier driver is arranged in one sense amplifier as shown in FIG. 9 is also possible. The number of sense amplifiers can be changed as appropriate.

Although the description has been made with reference to the example of a 4-bank 256-Mbit DRAM, the present invention is not limited to this, and there is a tendency to increase the number of banks to two banks, eight banks, and even more, and a capacity of 64 Mbits, 1 Gbits, and the like. The DRAM of the present invention can be widely applied, and the effect of the present invention is further increased by adopting such a multi-bank, large-capacity configuration.

Further, the gate of the MOS transistor constituting the sense amplifier is not limited to the U-shape, but may be an O-shape having a closed shape.

The case where the present invention is applied to a DRAM has been described. However, other memories such as a synchronous DRAM,
This is effective for a DRAM-mounted LSI, and can be applied as a high-speed technology such as an analog circuit and a low-voltage driving LSI.

[0050]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) The gate of the sense amplifier MOS transistor is formed in a U-shape on the diffusion layer, and the N-channel
By arranging a MOS transistor for a sense amplifier driver in common with a diffusion layer between MOS transistors for a P channel sense amplifier,
Since the OS transistor and the MOS transistor for the sense amplifier driver have a common diffusion layer, it is possible to minimize an increase in the area of the sense amplifier.

(2) Since the execution driver constant of the sense amplifier driver MOS transistor is doubled by separately providing a plurality of sense amplifier driver MOS transistor gates, the sense amplifier is operated at high speed. It becomes possible.

(3) By shunting the metal wiring layer on the gate of the sense amplifier driver MOS transistor which is separated into a plurality of MOS transistors, a metal wiring layer having a low resistance can be used as a shunt. Gate input signal propagates at high speed, so that the sense amplifier can operate at high speed.

(4) By removing a part of the diffusion layer of the sense amplifier driver MOS transistor, it is possible to change the execution driver constant while keeping the area constant, so that the operating speed and power consumption of the sense amplifier are adjusted. It is possible to do.

(5) By connecting a plurality of gates at the portion where the diffusion layer is removed, the metal wiring layer can be used as another wiring, so that an increase in the chip area due to the wiring can be prevented. It becomes possible.

(6) By connecting the diffusion layer of the sense amplifier MOS transistor at the portion where the diffusion layer has been removed,
Since the metal wiring layer can be used for connection such as gate input, the speed of the sense amplifier can be increased.

(7) According to the above (1) to (6), in a DRAM using a sense amplifier driver distributed arrangement method, an LSI mounted with DRAM, etc., an increase in the area of the sense amplifier portion is minimized, and Can be operated at high speed, so that the cost can be reduced by reducing the area of the entire chip, and the speed of the sense amplifier can be increased.

[Brief description of the drawings]

FIGS. 1A, 1B, and 1C are schematic layout diagrams showing a semiconductor memory device according to an embodiment of the present invention;

FIGS. 2A and 2B are schematic layout diagrams showing a sense amplifier in a semiconductor memory device according to an embodiment of the present invention; FIGS.

FIG. 3 is a circuit diagram showing a sense amplifier driver distributed arrangement method in the semiconductor memory device according to one embodiment of the present invention;

FIG. 4 is a layout diagram showing a sense amplifier driver distributed arrangement method in the semiconductor memory device according to one embodiment of the present invention;

FIG. 5 is a layout diagram showing a metal wiring layer in the semiconductor memory device according to one embodiment of the present invention;

FIG. 6 is a layout diagram showing a metal wiring layer shunting over a gate in the semiconductor memory device according to one embodiment of the present invention;

FIG. 7 is a layout diagram showing gate connections in the semiconductor memory device according to one embodiment of the present invention;

FIG. 8 is a layout diagram showing diffusion layer connections in the semiconductor memory device according to one embodiment of the present invention;

FIG. 9 is a circuit diagram showing a sense amplifier driver distributed arrangement method in which one driver is arranged for one sense amplifier in the semiconductor memory device according to one embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Memory cell array area 2 Array controller area 3 Y decoder area 4 Peripheral circuit area 5 Memory cell array 6 Sense amplifier array 7 Subword array 8 Cross area 11, 12 Shared sense amplifier separation circuit 13 Bit line precharge circuit 14 N channel side sense amplifier circuit 15 P-channel side sense amplifier circuit 16 Column selection circuit 17 Substrate power supply circuit 18 Pull-down side sense amplifier driver circuit 19 Pull-up side sense amplifier driver circuit M1, M3, M4, M7 to M13 NMOS transistors M2, M5, M6 PMOS transistor BL− T *, BL-B * Bit line SHR-L, SHR-R Shared sense amplifier separation signal line BLEQ Bit line precharge signal line VBLR Bit line precharge voltage CSN, CSP Suanpu driving line SAN, SAP sense amplifier discharge signal line VSSA ground voltage VDL bit line voltage G gate L diffusion layer ML1 first metal wiring layer ML2 second metal interconnect layer

Continuing from the front page (72) Inventor Yukihide Suzuki 5-2-21-1 Kamimizu Honcho, Kodaira-shi, Tokyo Inside Hitachi Super-LSI Systems Co., Ltd. (72) Inventor Koji Arai, Kodaira-shi, Tokyo 5-22-1, Mizumotocho Inside Hitachi Super LSI Systems, Ltd. (72) Inventor Yasushi Nagashima F-term in Hitachi, Ltd. Device Development Center 3-6-1, Shinmachi, Ome-shi, Tokyo (Reference) 5F048 AA01 AB01 AC03 BB01 BB02 BC01 5F083 AD00 GA01 GA09 LA01 LA03 LA11 LA21

Claims (8)

[Claims] 1. A sense amplifier including a pair of N-channel MOS transistors and a pair of P-channel MOS transistors connected to complementary bit lines of a memory cell array, and the sense amplifiers are driven and distributed in the sense amplifiers. A pair of N-channel MOS transistors and the gates of the pair of P-channel MOS transistors are formed in a U-shape on a diffusion layer, and the pair of N-channel MOS transistors and A pair of P-channel MOS
2. The semiconductor memory device according to claim 1, wherein the driver MOS transistors on the N-channel side or the P-channel side are arranged so as to share the diffusion layer between the transistors. 2. The semiconductor memory device according to claim 1, wherein said driver MOS transistor has a plurality of gates separated from each other. 3. The semiconductor memory device according to claim 2, wherein the gate of the driver MOS transistor divided into a plurality of MOS transistors is shunted by a metal wiring layer on the gate. Semiconductor storage device. 4. The semiconductor memory device according to claim 2, wherein the diffusion layer of the driver MOS transistor is arranged so as to remove a part overlapping with the plurality of gates separated from each other. Semiconductor storage device. 5. The semiconductor memory device according to claim 4, wherein said plurality of gates are connected to each other at a portion where a diffusion layer of said driver MOS transistor is removed. A semiconductor memory device characterized by the following. 6. The semiconductor memory device according to claim 4, wherein the diffusion layer of the pair of N-channel MOS transistors or the diffusion layer of the pair of P-channel MOS transistors is removed at a portion where the diffusion layer of the driver MOS transistor is removed. And a semiconductor memory device. 7. A sense amplifier connected to a complementary bit line of a memory cell array, and a driver MO that drives the sense amplifier and is disposed in the sense amplifier in a distributed manner.
A semiconductor memory device, comprising: an S transistor; and wherein the driver MOS transistor has a plurality of gates separated from each other. 8. The semiconductor memory device according to claim 1, wherein said driver MOS transistor is disposed between one of N-channel MOS transistors or one of P-channel MOS transistors. Semiconductor storage device.