JP3583916B2 - Semiconductor storage device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device technology. For example, as the capacity of a DRAM or the like increases, the distance from a sense amplifier to a main amplifier increases, so that access delay becomes a problem. In particular, the output of the sense amplifier is a very small signal. In addition, the present invention relates to a technique which is effective when applied to a semiconductor memory device which is suitable as a countermeasure against the delay due to a long wiring length.
[0002]
[Prior art]
For example, according to the study by the present inventor, M.I. Nakamura, "A 29ns 64Mb DRAM with Hierarchical Array Architecture," ISSCC pp246-247 in 1995. In this technique, a sense amplifier signal is amplified by a sub-amplifier circuit and then output to a main amplifier, thereby enabling high-speed operation. This sub-amplifier circuit is arranged in the intersection region between the sense amplifier region and the sub-word driver region, and the control signal of the sub-amplifier circuit is input from the main word driver region side.
[0003]
[Problems to be solved by the invention]
By the way, in the delay countermeasure technology such as the DRAM described above, it is necessary to match the timing of the control signal of the sub-amplifier circuit with the column selection line signal. It is difficult, and the sub-amplifier circuit of the non-selected memory mat is also activated, which may increase power consumption.
[0004]
Therefore, an object of the present invention is to apply a new sub-amplifier circuit and a control method thereof to input a control signal of the sub-amplifier circuit from the column decoder side so that the timing can be easily adjusted with the column selection line signal. And a semiconductor memory device capable of reducing power consumption by stopping the sub-amplifier circuit.
[0005]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0006]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0007]
That is, in the semiconductor memory device of the present invention, a sub-amplifier circuit for amplifying a sense amplifier signal is disposed in an intersection region between a sense amplifier region and a sub-word driver region adjacent to a memory cell array region, and a column decoder region is provided on a sense amplifier region side. This is applied to a hierarchical input / output configuration in which a main word driver region is arranged on the sub word driver region side, and is configured by inputting a control signal of the sub amplifier circuit from the column decoder region side.
[0008]
This sub-amplifier circuit takes a logic with a mat select signal input from the main word driver area side, and activates only the sub-amplifier circuit of the selected memory mat by the mat select signal.
[0009]
Specifically, the sub-amplifier circuit is turned on when the mat select signal is activated by the input of the bank active command, and is connected to the first gate circuit for connecting the sub-input / output line and the main input / output line, and turned off. A second gate circuit for changing the potential of the sub input / output line from a bit line equalize level to a read / write equalize level, and a differential amplifier circuit which is turned on when a control signal of the sub amplifier circuit is activated by input of a read command And a fourth gate circuit for turning off the sub input / output line and separating the main input / output line from the main input / output line, and is particularly applied to DRAMs, synchronous DRAMs and the like. is there.
[0010]
Therefore, according to the semiconductor memory device, since both the control signal of the sub-amplifier circuit and the column selection line signal are controlled from the column decoder region side, the timing can be easily adjusted, and the timing margin required in the conventional method can be reduced. Speeding up becomes possible. That is, the timing margin between the control signal of the sub-amplifier circuit and the column selection line signal can be made zero by using the same path.
[0011]
Further, since the unselected sub-amplifier circuits can be stopped, power consumption can be reduced. Furthermore, the sub-amplifier circuit can be devised to reduce the number of control signals from three to one. That is, by taking the logic of the mat selection signal and the control signal of the sub-amplifier circuit from the column decoder area, only the sub-amplifier circuit of the selected memory mat can be activated.
[0012]
As a result, in a semiconductor memory device such as a DRAM or a synchronous DRAM, the access time is reduced to improve the performance, the power consumption is reduced to improve the performance, and the number of signal lines is reduced to reduce the cost. be able to.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.
[0014]
1A and 1B are a layout diagram and a partially enlarged view showing a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a memory mat configuration in the semiconductor memory device according to the embodiment. FIG. 3 is a circuit diagram showing a sub-amplifier circuit, and FIGS. 4 and 5 are waveform diagrams showing a read operation and a write operation.
[0015]
First, the layout configuration of the semiconductor memory device of the present embodiment will be described with reference to FIG.
[0016]
The semiconductor memory device of the present embodiment is, for example, a 64-Mbit DRAM using a hierarchical input / output line configuration, and includes a main row decoder region 1, a main word driver region 2, a column decoder region 3, a peripheral circuit / bonding pad region. 4, a memory cell array region 5, a sense amplifier region 6, a sub-word driver region 7, an intersection region 8, and the like, and are formed on one memory chip by a known semiconductor manufacturing technique.
[0017]
In this DRAM, for example, as shown in FIG. 1, memory mats including a memory cell array region 5 and the like are divided and arranged on the left and right sides in the row direction of the memory chip, and on the upper and lower sides in the column direction. The memory mats arranged on the left and right sides are arranged in pairs with a main row decoder area 1 arranged in the center via a main word driver area 2 corresponding to each memory mat.
[0018]
Further, column decoder regions 3 corresponding to the respective memory mats are arranged at the center of the memory mats arranged above and below the memory chip. Further, a row address buffer, a column address buffer, a predecoder, a timing generation circuit, a data input / output circuit (not shown) and the like are arranged as a peripheral circuit / bonding pad area 4 in the center thereof. Is provided.
[0019]
In the memory mat, for example, as shown in FIG. 2, sense amplifier region 6 is arranged in the column direction of memory cell array region 5, and sub-word driver region 7 is arranged in the row direction, and sense amplifier region 6 and sub-word driver region 7 are arranged. A sub-amplifier circuit 9 as a control circuit for the sense amplifier group is arranged in an intersection area 8 with the sub-amplifier 9. In this memory cell array region 5, the word lines are in the row direction (horizontal direction), and the bit lines are in the column direction (vertical direction). Obviously, the present invention can be used in an arrangement opposite to this.
[0020]
In particular, in the present embodiment, this memory mat has a hierarchical input / output in which a sub-amplifier circuit 9 for amplifying a sense amplifier signal is arranged in an intersection area (intersection) 8 between a sense amplifier area 6 and a sub-word driver area 7. In order to make the control signal DREADT of the subamplifier circuit 9 the same path as the signal of the column selection line YS, the control signal DREADT of the subamplifier circuit 9 is input from the column decoder region 3 side. .
[0021]
Further, in sub-amplifier circuit 9, it is configured to take logic with mat select signal BLEQ input from sub-word driver region 7, and only sub-amplifier circuit 9 of the activated memory mat is connected to main input / output line MIOT / B. The sub-amplifier circuit 9 of the non-selected memory mat is configured not to be activated.
[0022]
The control signal DREADT of the subamplifier circuit 9 is generated by the predecode activation signal DRDIOT of the column decoder area 3 and is input from the column decoder area 3 to the subamplifier circuit 9. Further, the sub input / output line SIOT / B from the sub amplifier circuit 9 is connected to the sense amplifier region 6, and from the sense amplifier region 6, the bit line BLT / B controlled by the column selection line YS connects the memory cell array region 5 The main input / output line MIOT / B is connected to a main amplifier.
[0023]
Subsequently, an example of a circuit configuration of the sub-amplifier circuit 9 and an outline of its operation will be described with reference to FIG.
[0024]
The sub-amplifier circuit 9 includes a switching circuit including CMOS pass gates Q1 to Q4 controlled by a mat selection signal BLEQ and an inverted signal of the sub-amplifier circuit control signal DREADT, and a difference between NMOS transistors Q5 to Q9 controlled by a sub-amplifier circuit control signal DREADT. And a level conversion circuit composed of NMOS transistors Q10 to Q12 controlled by an inverted signal of a mat selection signal BLEQ, and inverters IV1 and IV2 for inverting signals. A function of controlling connection between the output line MIOT / B and the sub input / output line SIOT / B is provided.
[0025]
In the circuit configuration of sub-amplifier circuit 9, when a bank active command is input, mat select signal BLEQ is activated, CMOS pass gate Q1 is turned on, and sub-input / output line SIOT / B and main input / output line MIOT / B are connected. Is connected. At the same time, the NMOS transistor Q12 turns off, and the potential of the sub input / output line SIOT / B is changed from the bit line equalize level VBLR to the read / write equalize level VDD.
[0026]
Further, when a read command is input, the sub-amplifier circuit control signal DREADT of the memory mat in which the column selection line YS is selected is activated. Therefore, the NMOS transistor Q9 is turned on, the differential amplifier circuit is turned on, the CMOS pass gate Q4 is turned off, and the sub input / output line SIOT / B and the main input / output line MIOT / B are disconnected to read data. At this time, since the unselected sub-amplifier circuit 9 is disconnected from the main input / output line MIOT / B or is not activated, there is no problem.
[0027]
When a write command is input, data is written from the main input / output line MIOT / B while the sub-amplifier circuit 9 remains inactive. At this time, the non-selected sub-amplifier circuit 9 is similar to that at the time of reading.
[0028]
Next, with respect to the operation of the present embodiment, a read operation and a write operation will be described with reference to FIGS.
[0029]
First, when a memory mat is activated by a bank active command, as shown in FIG. 4, a mat select signal BLEQ, which is a bit line equalize signal, goes high. As a result, the selected sub input / output line SIOT / B and a part of the unselected sub input / output line SIOT / B (row activated memory mat) are precharged to the equalization level VDD at the time of reading / writing, and It can be connected to the input / output line MIOT / B.
[0030]
Thereafter, in the read operation, when the column selection line YS is selected by the read command, the sub-amplifier circuit control signal DREADT of the selected memory mat is activated to turn on the differential amplifier circuit. Thus, the signal on the sub input / output line SIOT / B can be amplified and transferred to the main input / output line MIOT / B.
[0031]
Although a part of the sub-amplifier circuit 9 of the non-selected memory mat (column-activated memory mat) is activated by the differential amplifier circuit, it is not connected to the main input / output line MIOT / B. It will not be.
[0032]
At the time of the write operation, as shown in FIG. 5, the sub-amplifier circuit control signal DREADT is inactive and remains at the Low level due to the write command. Thus, the sub input / output line SIOT / B and the main input / output line MIOT / B remain connected, and writing can be performed from the main input / output line MIOT / B.
[0033]
At the time of this write operation, the sub-amplifier circuit 9 of the present embodiment does not require connection of the sub-input / output lines SIOT / B, so that it is only necessary to select the column selection line YS, and therefore, high-speed writing can be performed. .
[0034]
Therefore, according to the semiconductor memory device of the present embodiment, it is possible to input the sub-amplifier circuit control signal DREADT from the column decoder region 3 side and make the sub-amplifier circuit control signal DREADT the same path as the signal of the column selection line YS. Therefore, the timing can be easily adjusted, the timing margin can be made unnecessary, and the operation can be performed at high speed.
[0035]
Further, by taking logic with mat select signal BLEQ in sub-amplifier circuit 9, only sub-amplifier circuit 9 of the selected memory mat is activated and sub-amplifier circuit 9 of the non-selected memory mat is not activated, so that power consumption is reduced. be able to.
[0036]
Further, with the circuit configuration of the sub-amplifier circuit 9, only one sub-amplifier circuit control signal DREADT can be used as compared with the conventional method that requires three control signals of read, write, and equalize.
[0037]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0038]
For example, in the above-described embodiment, an example of a 64-Mbit DRAM has been described. However, the present invention is not limited to this, and can be widely applied to a DRAM having a larger capacity such as 256 Mbits. The effect of the present invention is further increased by adopting a configuration with a large capacity.
[0039]
In addition, it goes without saying that the memory mat configuration of the memory chip is not limited to the four-division configuration shown in FIG.
[0040]
In the above description, the case where the invention made by the inventor is mainly applied to a semiconductor memory device using a DRAM, which is a technical field to which the invention belongs, is described. However, the present invention is not limited to this, and a synchronous DRAM, an SRAM, etc. The present invention can be widely applied to other semiconductor memory devices in general.
[0041]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0042]
(1). By inputting the control signal of the sub-amplifier circuit from the column decoder area side, it is possible to control from the column decoder area side along the same path together with the column selection line signal, so that the timing can be easily adjusted and the timing margin can be reduced. And access can be speeded up.
[0043]
(2). By taking the logic with the mat selection signal in the sub-amplifier circuit, it is possible to activate only the sub-amplifier circuit of the selected memory mat by this mat selection signal and stop the sub-amplifier circuit of the non-selected memory mat, thereby reducing power consumption. It becomes possible.
[0044]
(3). By having a gate circuit controlled by a bank active command, a read command, and a write command, the number of control signal lines in the sub-amplifier circuit can be reduced.
[0045]
(4). According to the above (1) to (3), in a semiconductor memory device such as a DRAM and a synchronous DRAM, an improvement in performance by shortening access time, an improvement in performance by reduction in power consumption, and a reduction in cost by reduction in the number of signal lines are realized. Becomes possible.
[Brief description of the drawings]
FIGS. 1A and 1B are a layout diagram and a partially enlarged view showing a semiconductor memory device according to an embodiment of the present invention;
FIG. 2 is an explanatory diagram showing a memory mat configuration in the semiconductor memory device according to one embodiment of the present invention;
FIG. 3 is a circuit diagram showing a sub-amplifier circuit in the semiconductor memory device according to one embodiment of the present invention;
FIG. 4 is a waveform diagram showing a read operation in the semiconductor memory device according to one embodiment of the present invention;
FIG. 5 is a waveform chart showing a write operation in the semiconductor memory device according to one embodiment of the present invention;
[Explanation of symbols]
1 Main row decoder area 2 Main word driver area 3 Column decoder area 4 Peripheral circuit / bonding pad area 5 Memory cell array area 6 Sense amplifier area 7 Subword driver area 8 Intersection area 9 Subamplifier circuit BLT / B Bit line YS Column select line MIOT / B Main input / output line SIOT / B Sub input / output line DREADT Subamplifier circuit control signal BLEQ Mat select signal DRDIOT Predecode start signal Q1 to Q4 CMOS pass gate Q5 to Q12 NMOS transistors IV1 and IV2 Inverter

Claims (4)

A sub-amplifier circuit for amplifying a sense amplifier signal is arranged at an intersection area between a sense amplifier area and a sub-word driver area adjacent to the memory cell array area, and a column decoder area on the sense amplifier area side and a main word on the sub-word driver area side. A semiconductor memory device having a hierarchical input / output configuration in which driver regions are arranged, wherein a control signal for the sub-amplifier circuit is input from the column decoder region side. 2. The semiconductor memory device according to claim 1, wherein said sub-amplifier circuit takes a logic with a mat select signal input from said main word driver area side, and only the sub-amplifier circuit of a selected memory mat by said mat select signal is activated. A semiconductor memory device characterized in that the semiconductor memory device is formed. 3. The semiconductor memory device according to claim 2, wherein said sub-amplifier circuit is turned on when said mat select signal is activated by input of a bank active command to connect a sub-input / output line and a main input / output line. A first gate circuit, a second gate circuit that turns off and changes the potential of the sub input / output line from a bit line equalize level to a read / write equalize level, and a control signal of the subamplifier circuit is activated by input of a read command A third gate circuit for turning on the differential amplifier circuit when turned on and a fourth gate circuit for turning off the sub input / output line and the main input / output line Storage device. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a DRAM or a synchronous DRAM.

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