JP4243389B2 - Semiconductor memory device and semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a semiconductor device, and more particularly to a technology effective when used in a dynamic RAM (random access memory) having a large storage capacity and high speed operation.
[0002]
[Prior art]
As a result of the investigation after the present invention has been considered, it is considered that the invention is related to the present invention described later, Japanese Patent Laid-Open No. 6-318391 (hereinafter referred to as Prior Art 1), Japanese Patent Laid-Open No. It was found that there is a prior art 2). In the prior art 1, as shown in FIGS. 18 and 19 of the accompanying drawings, a localize / precharge circuit is provided for each of the local IO line pair and the global IO line pair. In the prior art 2, the precharge circuit is provided for each of the local data bus and the global data bus. In this case, the local data bus includes a first precharge circuit for reading and writing, and a second precharge circuit for stabilizing the sense amplifier when the local data bus is not selected. Short circuit MOSFETs are provided on both sides of the selection circuit for selecting the local input / output lines in the hierarchical input / output lines as described above in order to realize a large storage capacity and high speed operation as in the present invention described later. There is no description that suggests the necessity of this.
[0003]
[Problems to be solved by the invention]
In a dynamic RAM (Random Access Memory), as the storage capacity increases, a word is used to secure a read signal amount from a dynamic memory cell, or to speed up selection operation and reduce power consumption. A hierarchical system is employed in which lines and bit lines are divided into a plurality of parts. As a result, the parasitic capacitance of the bit line and the word line to which the memory cell is connected can be reduced, and a high speed memory cell selection operation can be performed while ensuring the read signal amount. Such a hierarchical system itself is known in the above publications and the like.
[0004]
As the storage capacity increases, the number of divisions of the word lines and bit lines also increases. In the dynamic memory cell, a minute voltage formed by the charge coupling between the information charge stored in the storage capacitor and the precharge charge of the bit line is used as a read signal, so that the memory cell connected to the bit line Increasing the number is difficult because of the read signal amount. For this reason, the number of divisions of the bit lines inevitably increases, and as a result, the main input / output lines (global IO or global data bus in the above publication) tend to be long.
[0005]
As described above, when the length of the main input / output line is increased, the number of local input / output lines connected to the main input / output line is increased, and the number of switch MOSFETs constituting the column selection path is increased, Charge time will be longer. That is, even if a short-circuit MOSFET is provided for each local IO as in the prior art 1 and each local IO can be set to the same potential during the precharge period, the global IO is provided with only one precharge circuit. Therefore, in a place far away from such a precharge circuit, the precharge operation cannot be performed completely and a potential difference may occur. In addition, since the global mel IO has a large parasitic capacitance with respect to one local IO, the inventors of the present application have found that the potential difference is a large one that is not negligible for the local IO in terms of the amount of charge. It was issued.
[0006]
For this reason, when a read or write signal is transmitted, a potential difference due to the insufficient precharge time of the global IO is superimposed on the transmission signal as an offset. In the read operation, it is necessary to delay the operation start timing of the main amplifier until a necessary input signal amount is obtained due to the potential difference. In the write operation, there arises a problem that it takes a long time to invert the sense amplifier by the signal of the write amplifier due to the potential difference and to apply the full amplitude write voltage to the selected bit line.
[0007]
An object of the present invention is to provide a semiconductor memory device and a semiconductor device that realize an increase in storage capacity and a high speed operation. Another object of the present invention is to provide a semiconductor memory device and a semiconductor device which realize high integration in addition to increase in storage capacity and high speed operation. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. A plurality of complementary bit line pair signals in the memory cell array are each amplified by a plurality of first amplifier circuits, the plurality of first amplifier circuits are selected by a first selection circuit and connected to the first common complementary line pair, The first common complementary line pair is connected to the second common complementary line pair from the second selection circuit in correspondence with a plurality of memory blocks having such circuits, and a predetermined voltage is applied to the second common complementary line pair. In a semiconductor memory device including a first precharge circuit and an amplifier circuit for amplifying a read signal from the memory cell transmitted to the second common complementary line pair, the first selection circuit is formed on both sides of the plurality of first selection circuits. A pair of short-circuit MOSFETs for short-circuiting each of the one common complementary line pair and the second common complementary pair are provided, and the second selection circuit is set in a selected state during the precharge period of the first precharge circuit and the short To turn on the MOSFET.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a schematic layout diagram of an embodiment of a dynamic RAM to which the present invention is applied. In the figure, the overall arrangement of the dynamic RAM to which the present invention is applied is described. These are arranged on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. Formed in.
[0010]
The memory chip has about 16K bit lines in the longitudinal direction of the chip (in this application, bit lines are used in the same meaning as data lines or digit lines) and BL pairs (BLpair) are arranged in the short direction. Word lines WL are arranged. Therefore, the memory chip of this embodiment has a storage capacity of 16K × 16K = 256M (bits) as a whole. As described above, the memory array having a storage capacity of 256 Mbits as a whole is divided into four. The memory arrays divided into four are configured as memory banks (BANK) each having a storage capacity of about 64 Mbits.
[0011]
Although not shown, an internal power supply circuit including an address input circuit, a data input / output circuit, an input / output interface circuit composed of a bonding pad array, and a step-down circuit is provided at the center with respect to the longitudinal direction of the memory chip. The column decoder YDEC is disposed in the portion in contact with the memory array on both sides of the central portion. As described above, a main row decoder or the like is formed at the center of each of the four memory arrays in the longitudinal direction divided into two on the left and right and two on the top and bottom with respect to the longitudinal direction of the memory chip. An array controller AC is arranged. A main word line MWL is extended in the longitudinal direction of the memory chip with the array controller AC as a center. A column selection line YS is extended from the column decoder YDEC in the short direction of the memory chip.
[0012]
FIG. 2 shows a schematic layout diagram of an embodiment of a memory array constituting one memory bank. In the figure, one of the memory banks divided into two by the array controller is shown as an example. The divided memory array is divided into 6 pieces in the main word line direction and 16 pieces in the bit line direction. A sub word driver (sub word line driving circuit) SWD is provided in the sub array (sub array) divided into six in the word line direction as described above. The sub word driver SWD is divided into lengths of about 1/6 of the main word line MWL, and forms a selection signal for a sub word line extending in parallel therewith.
[0013]
In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. Two sub-word lines are arranged. In order to select one sub word line from the sub word lines divided into four in the main word line direction and two each in the complementary bit line direction, the sub word selection driver Be placed. The sub word selection driver generates a selection signal for selecting one of the two sub word selection lines extending in the arrangement direction of the sub word drivers.
[0014]
As described above, one memory array has a storage capacity of 16 Kbits in the complementary bit line direction. However, if 16K memory cells are connected to one complementary bit line, the parasitic capacitance of the complementary bit line increases, and the signal level read out cannot be obtained due to the capacitance ratio with a fine information storage capacitor. Further, it is divided into 16 in the complementary bit line direction. That is, the complementary bit line is divided into 16 by the sense amplifier SA. Although not particularly limited, the sense amplifier SA is configured by a shared sense system, and except for the sense amplifiers SA arranged at both ends of the memory array, complementary bit lines are provided on the left and right with respect to the sense amplifier SA. These complementary bit lines are selectively connected.
[0015]
As described above, the subarray is divided into six parts in the word line direction and sixteen parts in the bit line direction. Therefore, the number of subarrays constituting one memory bank is 16 × 6 × 2 = 192. By dividing the bit line as described above, the number of memory cells connected to one divided bit line is 512 (excluding redundant cells), and the number of memory cells connected to the sub word line is 688. (Including redundant cells).
[0016]
When the complementary bit lines are divided into 12 in the word line direction, 16K ÷ 12≈683, and the complementary bit line pair should originally be composed of a combination of subarrays having 683 and 682, but as described later, one column In order to connect two pairs of complementary bit lines to two pairs of local input / output lines LIO in the two subarrays by the selection signal YS, it is necessary to ensure that the numbers are even. In this embodiment, although not particularly limited, the complementary bit line pairs provided in one subarray are configured by the above-mentioned 688 pairs including redundant bit lines, or a combination of 696 pairs therewith.
[0017]
By reducing the number of word line divisions as described above, in a single memory bank, the number of sub-word drivers SWD arranged in the main word line direction is divided into 12, for example, compared with 18 in the case of 16 divisions. , 14 can be reduced. As a result, it is possible to reduce the chip size in the extending direction of the word line direction (longitudinal direction of the memory chip), and the length of the main word line MWL is correspondingly shortened. Can also be achieved.
[0018]
FIG. 3 is a schematic layout diagram showing one embodiment of the sub-array and its peripheral circuit in the dynamic RAM according to the present invention. In FIG. 3, the subarray (subArray) is composed of 512 subword lines (SWL) × 688 bit line pairs (BLpair) as described above. 128 main word lines MWL such as 0 to 127 are provided for the sub-array. Four sub word lines SWL are assigned to one main word line. That is, according to the combination of the selection signal of the main word line MWL and the four sub word line selection signals FXB0 to FXB3, the sub word driver SWD can select one of the four sub word lines selected from the main word line MWL. Select.
[0019]
The sub word driver SWD selects the sub word lines of the two sub arrays formed so as to sandwich it. Therefore, 256 sub word drivers SWD are provided even though there are 512 sub word lines SWL. From the viewpoint of one subarray, among the 512 subword lines, 256 of the subword lines are selected by the upper subword driver SWD and the other half are selected by the lower subword driver SWD. In this way, the configuration in which the sub word drivers SWD are divided up and down with respect to the sub word lines SWD can double the arrangement pitch of the sub word drivers SWD with respect to the arrangement pitch of the sub word lines SWL, and secure the driving capability of the sub word drivers SWD. However, a high-density array of sub-word lines can be realized.
[0020]
The sense amplifier SA employs a shared sense amplifier system and is selectively used for two subarrays sandwiching the sense amplifier SA. Therefore, half of the 344 sense amplifiers SA are provided for the bit line pairs provided in the subarray. In this case, similarly to the relationship between the sub word driver and the sub word line, it is possible to realize a high-density array of complementary bit line pairs while increasing the sensitivity of the sense amplifier.
[0021]
In the region where the sense amplifier is formed, a shared switch MOSFET, a bit line precharge MOSFET, a column selection MOSFET, its selection signal line, and a local IO line are formed as will be described later. In this embodiment, the sense amplifiers SA are shown to be divided by 172, but this means that the local I / O lines LIO are divided in such divided parts in relation to a main I / O line MIO described later. It shows that it is divided.
[0022]
FIG. 4 shows a schematic layout diagram of an embodiment of a memory array constituting one memory bank. This figure corresponds to FIG. 2 and shows the configuration of the bit line direction and hierarchical IO. FIG. 5 shows an enlarged view corresponding to two columns (2 × 6 = 12) of subarrays arranged in the word line direction.
[0023]
In FIG. 4, about 1K worth of column selection signals such as YS0 to YS1023 are formed by the Y decoder YDEC. Each of these signal lines is extended in four groups so as to extend on the subarray. In this embodiment, the column selection signal lines YS0 to YS1023 are divided into two, YS0 to YS511 and YS512 to YS1023. For example, YS0 and YS512 are selected one by one. That is, in one memory bank, 8K memory cells are selected by selecting one word line. Among them, 0 to 511 selection signals are required for reading in units of 16 bits.
[0024]
The selection signal lines YS0 to YS511 extend linearly from the Y decoder YDEC so as to penetrate 16 subarrays in the bit line extending direction, and are provided with sense amplifiers corresponding to the 16 subarrays. Branching in the direction of the word line, and at such a branching portion, the sense amplifier row corresponding to the three sub-arrays corresponding to the left half arranged in the direction of the word line in FIG. The selection signal lines YS512 to YS1023 extend linearly from the Y decoder YDEC as described above, and branch in the word direction at the portion where each sense amplifier corresponding to each of the 16 subarrays is provided. A sense amplifier array corresponding to three sub-arrays corresponding to half is extended.
[0025]
Four pairs of main input / output lines MIO form a set, and a total of four sets are arranged in the extension line direction of the bit line. The main input / output line MIO extends above the sub-word driver SWD and the intersection region IS sandwiched between the sub-word driver SWD and the sense amplifier SA. Therefore, the main input / output line MIO is extended so as to be parallel to the column selection line YS extending linearly from the Y decoder YDEC.
[0026]
As shown in the enlarged view of FIG. 5, the local input / output line LIO is divided into four in the main word line direction by making a pair of complementary lines corresponding to the true T and bar B indicated by the solid line and the dotted line. That is, as described above, the six subarrays are divided into three by the intersection area IS and the subword driver SWD arranged at the center. The sub-array divided into three parts as described above is divided into 172 parts as shown in FIG. 3 in the sense amplifier SA corresponding to the sub-array provided in the intermediate part, and the divided parts are divided. The local input / output line LIO is isolated.
[0027]
The four pairs of main input / output lines MIO are connected to the local input / output lines LIO divided into four equal parts and having the same length as described above. Although not particularly limited, the local input / output lines LIO are arranged in pairs of sense amplifiers SA corresponding to one subarray and sense amplifiers SA corresponding to a crossing area and a half subarray as shown by a solid line and a dotted line. In the subarray, when one subword line SWL is selected, two sense amplifiers SA arranged on both sides of the subword line SWL are activated, and two pairs of complementary bit lines selected by the column selection line YS among them are activated. Are connected to two pairs of local input / output lines LIO arranged corresponding to the two sense amplifier rows.
[0028]
Two pairs of local input / output lines LIO provided corresponding to the sense amplifier SA column are respectively selected at the intersections with the main input / output lines MIO, that is, the selection circuits (indicated by black circles in the intersection area IS) ( The I / O switch is connected to the main input / output line MIO. As a result, in the memory array of FIG. 4, 16-bit data is read to the 16 pairs of main input / output lines MIO0T, B to MIO15T, B. Since one memory bank is provided with two memory arrays shown in FIG. 4 with the array controller AC interposed therebetween, a total of 32 bits can be selected, and each is connected to an input terminal of a main amplifier MA (not shown). Reportedly.
[0029]
For example, when reading is performed in units of 16 bits, the 32 pairs of main input / output lines MIO and 32 main amplifiers MA are divided into two parts each of which are selected by a 1-bit Y address signal. do it. In the burst mode, when the column address is switched for continuous reading or writing, when one main amplifier MA or the like is activated to perform the reading operation, the other local input / output line on which the next reading or the like is performed It is possible to perform precharge and equalize operations on the LIO and the main input / output line MIO.
[0030]
If the memory access is performed in units of 8 bits, the main amplifier MA and the like may be selected four times by using the 2-bit Y address signal, and the memory access is performed in units of 4 bits. In the configuration to be performed, the main amplifier MA and the like may be selected by dividing each of the four main amplifiers MA into eight times using a 3-bit Y address signal. Such bit configuration switching can be easily set by a bonding option, a metal option, or the like.
[0031]
FIG. 6 shows a schematic layout diagram of an embodiment of a memory array constituting one memory bank. This figure corresponds to FIG. 2 and illustrates the selection operation of the selection circuit. Although the selection circuit performs the selection operation of the IO line, the selection signal is formed by the X-system address signal. That is, the selection operation is performed by the mat selection signal BLEQ provided in the array controller. The mat selection signal BLEQ consists of 0 to 17, and two signals sandwiching the selected sub-array (memory mat) are selected.
[0032]
Of the sub-arrays (memory mats) divided into 16 in the bit line direction as described above, when the memory mat 15 is selected as shown, in other words, in the memory array, the farthest from the Y decoder YDEC. When the main word line (sub word line) corresponding to the six sub-arrays provided at the position is selected, the two mat selection signals BLEQ 16 and 17 provided on the sense amplifier SA and the intersection area IS sandwiching the sub-array are at the low level. The selection level is as follows. On the other hand, the remaining 16 mat selection signals BLEQ0 to BLEQ corresponding to the sub-arrays where the main word line is not selected are set to a high level non-selection level.
[0033]
The IO line selection circuit allocated to the two intersecting areas IS as described above determines the local input / output line LIO and the main input / output line MIO according to the selection level such as the low level of the mat selection signals BLEQ16 and 17. Connect. The selection circuits corresponding to the main input / output line MIO and other memory mats are turned off by the mat selection signals BLEQ0-15. Thus, the main input / output line MIO is connected only to the local input / output line LIO corresponding to the selected memory mat.
[0034]
In the selection operation as described above, when the memory mat 15 is selected, the local input / output line LIO and the main input / output line MIO are not connected to other memory mats, but the complementary bit lines of each subarray are connected to each other. Four pairs of local input / output lines LIO corresponding to each sub-array are connected. For this reason, the local input / output line LIO corresponding to the non-selected memory mat is given a different precharge voltage when the local input / output line LIO is selected, as will be described later.
[0035]
FIG. 15 shows a circuit diagram of a simplified embodiment from address input to data output, centering on the sense amplifier portion of the dynamic RAM according to the present invention. In the figure, a sense amplifier 16 sandwiched between two subarrays 15 from above and below and a circuit provided in the intersection area 18 are shown as examples, and the others are shown as block diagrams.
[0036]
As the dynamic memory cell, one of the dynamic memory cells provided between the sub word line SWL provided in the one subarray 15 and one of the complementary bit lines BL and BLB is exemplarily shown as a representative. ing. The dynamic memory cell includes an address selection MOSFET Qm and a storage capacitor Cs. The gate of the address selection MOSFET Qm is connected to the sub word line SWL. The drain of the MOSFET Qm is connected to the bit line BL. A storage capacitor Cs is connected to the source of the MOSFET Qm. In the present application, MOSFET is a general term for an insulated gate field effect transistor (IGFET). Therefore, the gate electrode is not limited to a metal and may include a polysilicon layer, or a gate insulation. The film may be an insulating film in addition to the silicon oxide film.
[0037]
The other electrode of the storage capacitor Cs is made common to receive the plate voltage VPLT. A negative back bias voltage VBB is applied to the substrate (channel) of the MOSFET Qm. Although not particularly limited, the back bias voltage VBB is set to a voltage such as −1V. The selection level of the sub word line SWL is set to a high voltage VPP that is higher than the high level of the bit line by the threshold voltage of the address selection MOSFET Qm.
[0038]
When the sense amplifier is operated at the internal step-down voltage VDL, the high level amplified by the sense amplifier and applied to the bit line is set to the internal voltage VDL level. Therefore, the high voltage VPP corresponding to the selection level of the word line is set to VDL + Vth + α. A pair of complementary bit lines BL and BLB of the sub-array provided on the left side of the sense amplifier 16 are arranged in parallel as shown in FIG. The complementary bit lines BL and BLB are connected to input / output nodes of the unit circuit of the sense amplifier by shared switch MOSFETs Q1 and Q2.
[0039]
The unit circuit of the sense amplifier 16 is composed of a CMOS latch circuit composed of N-channel type amplification MOSFETs Q5 and Q6 and P-channel type amplification MOSFETs Q7 and Q8 whose gates and drains are cross-connected to form a latch. The sources of N-channel MOSFETs Q5 and Q6 are connected to a common source line CSN. The sources of P-channel MOSFETs Q7 and Q8 are connected to a common source line CSP. A power switch MOSFET is connected to each of the common source lines CSN and CSP.
[0040]
Although not particularly limited, the common source line CSN to which the sources of the N-channel amplification MOSFETs Q5 and Q6 are connected is not particularly limited, but is brought to the ground potential by the N-channel power switch MOSFET Q14 provided in the intersection area 18. Corresponding operating voltage is given. Similarly, an N-channel power MOSFET Q15 for supplying the internal voltage VDL is provided on the common source line CSP to which the sources of the P-channel amplification MOSFETs Q7 and Q8 are connected. The power switch MOSFETs may be distributed in each unit circuit as will be described later with reference to FIG.
[0041]
The sense amplifier activation signals SAN and SAP supplied to the gates of the N-channel type power MOSFETs Q14 and Q15 are in-phase signals that are set to a high level when the sense amplifier is activated. The high level of the signal SAP is a signal of the boosted voltage VPP level. Since the boosted voltage VPP is about 3.6 V when VDL is 1.8 V, the N-channel MOSFET Q15 can be sufficiently turned on to bring the common source line CSP to the internal voltage VDL level.
[0042]
At the input / output node of the unit circuit of the sense amplifier, there are provided an equalize MOSFET Q11 for short-circuiting the complementary bit line and a precharge (equalize) circuit comprising switch MOSFETs Q9 and Q10 for supplying a half precharge voltage VBLR to the complementary bit line. . The gates of these MOSFETs Q9 to Q11 are commonly supplied with a precharge signal PCB. Although not shown, the driver circuit for generating the precharge signal PCB is provided with an inverter circuit in the intersection area 18 so as to make the rise and fall fast. That is, at the start of memory access, the MOSFETs Q9 to Q11 constituting the precharge circuit are switched at high speed through inverter circuits distributed in each intersection area 18 prior to the word line selection timing. .
[0043]
In the intersection area 18, switch MOSFETs Q19 and Q20 constituting a selection circuit (or IOSW) are placed. Further, in addition to the circuit shown in the figure, if necessary, a half precharge circuit for the common source lines CSP and CSN of the sense amplifier, a half precharge circuit for the local input / output line LIO, and a VDL precharge for the main input / output line. A circuit, a distributed driver circuit of shared selection signal lines SHR and SHL, and a pair of short-circuit MOSFETs M1 and M2 according to the present invention are provided on both sides of the selection circuit.
[0044]
The unit circuit of the sense amplifier is connected to similar complementary bit lines BL and BLB of the subarray 15 on the lower side of the figure via shared switch MOSFETs Q3 and Q4. For example, when the sub word line SWL of the upper sub array is selected, the upper shared switch MOSFETs Q1 and Q2 of the sense amplifier are turned on, and the lower shared switch MOSFETs Q3 and Q4 are turned off. The switch MOSFETs Q12 and Q13 constitute a column selection circuit. The switch MOSFETs Q12 and Q13 are turned on when the selection signal YS is set to a selection level (high level), and input / output nodes and local input / output lines of the unit circuit of the sense amplifier. LIO1 and LIO1B (LIO2 and LIO2B) are connected.
[0045]
Since the sense amplifier 16 and the crossing area 18 are provided with two pairs of local input / output lines, for example, LIO1 and LIOIB and LIO2 and LIO2B as described above, two pairs of subarrays 15 are complemented by the one selection signal YS. Bit lines are connected to the two pairs of local input / output lines LIO1 and LIOIB and LIO2 and LIO2B. The other sense amplifier 16 (not shown) across the sub-array 15 is also provided with two pairs of local input / output lines in the same manner as described above, and four pairs of complementary bit lines in the sub-array as described above have four pairs of local inputs. Connected to the output line.
[0046]
As described above, when the upper shared switch MOSFETs Q1 and Q2 are in the ON state, the memory cell connected to the selected sub word line SWL is connected to the upper complementary bit lines BL and BLB at the input / output node of the sense amplifier. Are transmitted to the local input / output lines LIO1 and LIO1B through the column selection circuits (Q12 and Q13). The local input / output lines LIO1 and LIO1B extend in the horizontal direction in FIG. The local input / output lines LIO1 and LIO1B are connected to the main input / output lines MIO and MIOB to which the input terminals of the main amplifier 61 are connected via a selection circuit (IOSW) including N-channel MOSFETs Q19 and Q20 provided in the intersection area 18. Connected to.
[0047]
The selection circuit IOSW constituting the IO switch circuit is switch-controlled by the mat selection signal formed by decoding the X-system address signal as described above. Note that the selection circuit IOSW may have a CMOS switch configuration in which P-channel MOSFETs are connected in parallel to the N-channel MOSFETs Q19 and Q20 as described below. In the burst mode of the synchronous DRAM, the column selection signal YS is switched by a counter operation, and two pairs of complementary bit lines of the local input / output lines LIO1, LIO1B and LIO2, LIO2B and the subarray shown in the above example are shown. The connection with BL and BLB is sequentially switched.
[0048]
The address signal Ai is supplied to the address buffer 51. This address buffer operates in a time-sharing manner and takes in the X address signal and the Y address signal. The X address signal is supplied to the predecoder 52, and a selection signal for the main word line MWL is formed via the main row decoder 11 and the main word driver 12. The address buffer 51 receives an address signal Ai supplied from an external terminal, and is operated by a power supply voltage VDDQ supplied from the external terminal.
[0049]
The predecoder is operated by a step-down voltage VPERI (VDD) obtained by stepping down the predecoder, and the main word driver 12 is operated by a step-up voltage VPP. As the main word driver 12, a logic circuit with a level conversion function for receiving the predecode signal is used. A column decoder (driver) 53 includes a drive circuit in which an operating voltage is formed by the MOSFET Q23 constituting the VCLP generation circuit, receives a Y address signal supplied by the time-division operation of the address buffer 51, and The selection signal YS is formed.
[0050]
The main amplifier 61 is operated by the step-down voltage VPERI (VDD), and is output from the external terminal Dout through the output buffer 62 operated by the power supply voltage VDDQ supplied from the external terminal. A write signal input from the external terminal Din is taken in through the input buffer 63 and supplied to the main input / output lines MIO and MIOB through a write amplifier (write driver) included in the main amplifier 61 in FIG. The input section of the output buffer 62 is provided with a level conversion circuit and a logic section for outputting the output signal in synchronization with the timing signal corresponding to the clock signal.
[0051]
Although not particularly limited, the power supply voltage VDDQ supplied from the external terminal is set to 3.3 V in the first embodiment, the step-down voltage VPERI (VDD) supplied to the internal circuit is set to 2.5 V, and the sense The operating voltage VDL of the amplifier is 1.8V. The word line selection signal (boosted voltage) is set to 3.6V. The bit line precharge voltage VBLR is set to 0.9 V corresponding to VDL / 2, and the plate voltage VPLT is also set to 0.9 V. The substrate voltage VBB is set to -1.0V. The power supply voltage VDDQ supplied from the external terminal may be set to a low voltage such as 2.5 V as the second form. In such a low power supply voltage VDDQ, the step-down voltage VPERI (VDD) and the step-down voltage VDL may be set to about 1.8V.
[0052]
Alternatively, the power supply voltage VDDQ supplied from the external terminal is set to 3.3 V, and the step-down voltage VPERI (VDD) supplied to the internal circuit and the operating voltage VDL of the sense amplifier are set to 2.0 V or 1.8 V, respectively. May be. As described above, various embodiments can be adopted as the internal voltage with respect to the external power supply voltage VDDQ.
[0053]
FIG. 7 is a circuit diagram showing the principal part of one embodiment of the semiconductor memory device according to the present invention, and FIG. 16 is an operation waveform diagram thereof. FIG. 7 shows a pair of local input / output lines LIOT and LIOB, a pair of main input / output lines MIOT and MIOB, and respective circuits related thereto. The local input / output lines LIOT and LIOB are connected to the input / output nodes of the unit circuit of the sense amplifier via the column switch MOSFET as described above in the sense amplifier (SA) column indicated by a black box.
[0054]
The local input / output lines LIOT and LIOB are formed so as to extend the sense amplifier row, and are connected to 512 pairs of column switch MOSFETs in the sense amplifier row. In the crossing area IS sandwiched between the sense amplifier and the sub word driver, the main input / output lines MIOT and MIOB are connected to the MOSFETs Q8 to Q11 constituting the selection circuit. This selection circuit is composed of a CMOS switch in which a P-channel MOSFET Q8 (Q9) and an N-channel MOSFET Q10 (Q11) are paired. A mat selection signal BLEQ that is set to a low level when supplied is supplied to the gates of the P-channel MOSFETs Q8 and Q9, and an inverted signal BLEQB is supplied to the gates of the N-channel MOSFETs Q10 and Q11.
[0055]
In the above configuration, the local input / output lines LIOT, LIOB and the complementary bit lines are connected to the complementary bit lines and the local bit lines LIOT, LIOB by the column selection signal YS even in the non-selected subarray (memory mat). If the same precharge voltage VDL from the same main input / output line MIO as the selected one remains, the precharge voltage of the complementary bit line is changed via the amplification MOSFET constituting the sense amplifier in the non-operation state. Therefore, the local input / output lines LIOT and LIOB are provided with precharge circuits including N-channel MOSFETs Q1 to Q3. This precharge circuit is provided with local input / output lines LIOT and LIOB in the subarray when the local input / output lines LIOT and LIOB are in a non-selected state, that is, in a precharge cycle in which the selection circuit is turned off. Is set to the same precharge voltage VBLR as that of the complementary bit line to stabilize the precharge voltage of the complementary bit line.
[0056]
The main input / output lines MIOT and MIOB are connected to the input terminal of the main amplifier MA provided on the Y decoder YDEC side as described above. The main amplifier MA is not particularly limited, but the circuit configuration is composed of a CMOS latch circuit similar to the sense amplifier described above, and performs an amplification operation at the operation timing. A precharge circuit comprising MOSFETs Q12 to Q14 is provided at the input portion of the main amplifier MA. These MOSFETs Q12 to Q14 are composed of P-channel MOSFETs, and are composed of MOSFETs Q14 and Q13 that supply the operating voltage VDL to the main input / output MIOT and MIOB, and MOSFET Q12 that short-circuits both the main input / output lines MIOT and MIOB. . A precharge signal EQIOB is supplied to the gates of these MOSFETs Q12 to Q14.
[0057]
In this embodiment, a pair of short-circuit MOSFETs M1 and M2 are provided on both sides of the MOSFETs Q8 to Q11 constituting the selection circuit (IO switch). These MOSFETs M1 and M2 are formed in the intersection area IS. The precharge signal EQIOB is supplied to the gates of the MOSFETs M1 and M2. Since the short-circuit MOSFETs M1 and M2 are provided on both sides of a plurality of selection circuits connected to the main input / output lines MIOT and MIOB, as shown in FIG. 16, depending on the low level of the precharge signal EQIOB generated at the end of the read cycle. The short-circuit MOSFETs M1 and M2 are turned on, and LIOT / B and MIOT / B can be equalized at high speed.
[0058]
In FIG. 16, a voltage VDL is an operating voltage of the sense amplifier as described above, and is set to 1.6 V, for example. The voltage VCL is an operating voltage of the indirect peripheral circuit and has the same meaning as VPRI, for example, 2.5V. VPP is the boosted voltage, for example, 3.5V. The signal MIW is a write activation signal, and the write signal is transmitted to the complementary bit line LB to which the selected memory cell is connected via the MIO and LIO by the high level of the signal MIW. The signal DIOET is a start signal for the sub-amplifier circuit, and operates to amplify the read signal from the bit line enabled at the time of reading and writing or the write signal from the MIO to increase the voltage difference of the LIO.
[0059]
Each of the MOSFETs M1 and M2 simply performs a short-circuit operation and does not supply a precharge voltage VDL. For this reason, if the short-circuit MOSFETs M1 and M2 are simply provided, there is a possibility that the precharge voltage VDL may not be reached if the precharge (equalize) period is short at a position away from the precharge circuit (Q12 to Q14). However, due to the short-circuit operation of the short-circuit MOSFETs M1 and M2, on both sides of the selection circuit, the main input / output lines MIOT and MIOB and the local input / output lines LIOT and LIOB have the same potential even if they do not become the precharge voltage VDL. Can do. As described above, in the main input / output lines MIOT and MIOB and the local input / output lines LIOT and LIOB, a potential difference corresponding to the previous read signal and write signal can be prevented from occurring at the end of the precharge. Thereby, in the read operation and write operation after the precharge operation, substantial signal transmission can be performed at high speed, and the read operation and write operation can be speeded up.
[0060]
In the burst mode in the synchronous DRAM, continuous memory access is performed by switching the Y address from the clock signal, and the precharge (equalization) period is shortened as the frequency of the clock signal increases. In the present invention, the precharge period is shortened so that the main input / output lines MIOT and MIOB are provided by providing the short-circuit MOSFET as described above even if the potentials of the respective nodes are not all set to the desired precharge potential VDL. By eliminating the potential difference between the local input / output lines LIOT and LIOB, the reading operation and the writing operation are speeded up. That is, the precharge voltages of the main input / output lines MIOT and MIOB and the local input / output lines LIOT and LIOB can perform the amplification operation of the main amplifier MA, and the local input / output lines LIOT necessary for the inversion operation of the sense amplifier SA in the write operation. , LIOB need only be secured, and need not be set to VDL.
[0061]
In this embodiment, the local input / output lines LIOT and LIOB are provided with sub-amplifier circuits composed of MOSFETs Q4 to Q7 for high-speed read operation. These MOSFETs Q4 to Q7 are arranged in the intersection area IS. When the sub-amplifier circuit as described above is provided in the intersection area IS, it is desirable to dispose activation MOSFETs as described later in the sense amplifier SA array in order to secure an element formation area.
[0062]
The sub-amplifier circuit includes latch-type amplifier MOSFETs Q4 and Q5 whose gates and drains are cross-connected and connected to the local input / output lines LIOT and LIOB, a common source of the MOSFETs Q4 and Q5, and circuit ground The MOSFETs Q6 and Q7 are provided between the potential VSS and flow an operating current. The operation timing signal DIOET is supplied to the gate of the MOSFET Q6, and the mat selection signal BLEQB is supplied to the gate of the MOSFET Q7. That is, only the sub-amplifier circuits connected to the local input / output lines LIOT and LIOB corresponding to the selected memory mat are operated in accordance with the signal transmission timing of reading and writing.
[0063]
By providing the sub-amplifier circuit as described above, by connecting a large number of column selection MOSFETs, it is possible to speed up the signal change of the local input / output lines LIOT and LIOB having a relatively large parasitic capacitance, A write operation can be enabled. When such a sub-amplifier circuit is provided, if the potential difference in the precharge operation as described above remains in the local input / output lines LIOT and LIOB, it is amplified as it is, so that the operation timing is delayed. There is a need. However, when the short-circuit MOSFET M1 is provided as in this embodiment, the timing margin as described above becomes unnecessary, and higher speed operation can be realized.
[0064]
FIG. 8 is a circuit diagram showing the principal part of another embodiment of the semiconductor memory device according to the present invention. In the figure, MOSFETs M3 and M4 for supplying a precharge voltage VDL are added to the main input / output lines MIOT, MIOB side of the selection circuit in addition to the circuit of the embodiment of FIG. As a result, the main input / output lines MIOT and MIOB can be supplied with the precharge voltage VDL from a plurality of locations where the selection circuit is provided. A precharge operation in time can be enabled.
[0065]
FIG. 9 is a circuit diagram showing the principal part of still another embodiment of the semiconductor memory device according to the present invention. In the figure, MOSFETs M5 and M6 for supplying a precharge voltage VDL are also added to the local input / output lines LIOT and LIOB of the selection circuit in addition to the circuit of the embodiment of FIG. Thus, the main input / output lines MIOT and MIOB are supplied with the precharge voltage VDL from a plurality of locations where the selection circuit is provided, and the precharge voltage VDL is also supplied on the local input / output lines LIOT and LIOB side. Thus, the precharge operation can be performed in a shorter time.
[0066]
However, the precharge circuit provided in the local input / output lines LIOB and LIOB uses the precharge signal X so that only the local input / output lines LIOT and LIOB corresponding to the mat selection signal BLEQB perform the precharge operation. There is a need. That is, since the precharge voltage VBLR is supplied to the unselected local input / output lines LIOT and LIOB, it is necessary to control the VDL and VBLT so that they do not collide with each other.
[0067]
FIG. 10 is a circuit diagram showing the principal part of one embodiment of the semiconductor memory device according to the present invention. This figure is for explaining the embodiment of FIG. 7 in more detail. With respect to the MIO line composed of the main input / output line MIOT, the local input / output lines LIOT corresponding to the respective memory mats via the plurality of selection circuits in the intersection area IS corresponding to the plurality of memory mats as described above. And LIOB are connected.
[0068]
In this embodiment, short-circuit MOSFETs M1 and M2 are provided on both sides of the selection circuit corresponding to each memory mat. The gates of these short-circuit MOSFETs M1 and M2 are commonly connected to the gates of the short-circuit MOSFETs M1 and M2 corresponding to other memory mats provided in the same manner, and supplied with a precharge signal EQIOB. The precharge signal EQIOB also turns on the short-circuit MOSFET M1 between the local input / output lines LIOT and LIOB of the non-selected memory mat. Therefore, in such unselected local input / output lines LIOT and LIOB, the short-circuit MOSFET M1 on the local input / output lines LIOT and LIOB side is a short-circuit MOSFET having a precharge voltage VBLR corresponding to the half precharge voltage of the bit line. Will be performed.
[0069]
On the other hand, in the unselected local input / output lines LIOT and LIOB, the main input / output line MIOT and the short-circuit MOSFET M2 on the MIOB side operate as a short-circuit MOSFET of the MIO line. Therefore, as described above, the main input / output lines MIOT and MIOB act to have at least the same potential during the precharge period.
[0070]
The output side of the main amplifier MA is connected to global input / output lines GIOT and GIOB. The global input / output lines GIOT and GIOB are 16 pairs of signal lines when memory access is performed in units of 16 bits as described above, and are connected to the output terminals of two main amplifiers in one memory bank. Connected. When there are four memory banks in the memory chip as shown in FIG. 1, the output terminals of two main amplifiers are arranged to be connected to each memory bank. The global input / output lines GIOT and GIOB form a signal transmission path that connects the output terminal of the main amplifier MA, the input terminal of the output buffer 62, and the output terminal of the input buffer 63 in FIG.
[0071]
FIG. 11 is a timing chart for explaining an example of the operation of the semiconductor memory device according to the present invention. FIG. 4A shows an example of the read mode, and FIG. 4B shows an example of the write mode. In the DDR synchronous DRAM in which data is input (written) and output (read) in synchronization with the rising and falling timings of the clock signal CLK (/ CLK) as shown in FIG. It is necessary to perform the precharge operation during a period, and it is significant to provide the short-circuit MOSFETs M1 and M2 as described above.
[0072]
FIG. 12 is a timing chart for explaining the present invention. In the figure, operations of a synchronous DRAM (hereinafter abbreviated as SDRAM) and a DDR SDRAM are compared. In a DDR SDRAM, data can be input and output at twice the speed even with the same clock frequency. This means that the precharge period of the main input / output line MIO and the local input / output line LIO is shortened.
[0073]
Therefore, in the case where the clock frequency is increased and the DDR operation as described above is performed, securing the precharge period of the main input / output line MIO and the local input / output line LIO is a bottleneck and hinders speeding up. . In the present invention, basically, such a problem can be solved by a simple configuration in which short-circuit MOSFETs are provided on both sides of an IO switch (selection circuit) that connects the main input / output line MIO and the local input / output line LIO. There is an excellent effect of being able to.
[0074]
FIG. 13 is a circuit diagram showing one embodiment of the sense amplifier portion of the dynamic RAM according to the present invention. The circuit symbols attached to the MOSFETs of this embodiment correspond to those shown in FIG. 15 and partially overlap the MOSFETs shown in FIGS. 7 to 9, but each has a separate circuit function. It should be understood that it has.
[0075]
As described above, the unit circuit of the sense amplifier is composed of N-channel MOSFETs Q5 and Q6 and P-channel MOSFETs Q7 and Q8. The sources of these latched N-channel MOSFETs Q5 and Q6 and P-channel MOSFETs Q7 and Q8 are N-channel MOSFETs and P-channel MOSFETs that constitute other similar sense amplifiers (not shown) provided corresponding to the same subarray. The sources of the MOSFETs are connected to common source lines CSN and CSP that are commonly connected to each other.
[0076]
The common source line CSN is supplied with an operating voltage VSSA via an N-channel MOSFET Q14 that receives a timing signal SAN. The common source line CSP is supplied with an operating voltage VDL via an N-channel MOSFET Q15 that receives a timing signal SAP. Is supplied. In this embodiment, the ground potential VSSA, which is one operating voltage of the sense amplifier, is separated from the ground potential VSS so as not to be affected by noise from the peripheral circuit or the like. The ground potential supplied from the external terminal is applied. That is, the ground potential VSSA applied to the sense amplifier is directly applied from the external terminal by a wiring provided separately from the peripheral circuit and the input / output circuit.
[0077]
A pair of input / output nodes (sense nodes) SAT and SAB of the latch circuit are pre-configured by an equalize MOSFET Q11 for short-circuiting them and a precharge MOSFET Q9 and Q10 for transmitting a half precharge voltage VBLR to the sense nodes SAT and SAB. A charge circuit is provided. The sense nodes SAT and SAB are connected to the local input / output lines LIOT and LIOB via column switch MOSFETs Q12 and Q13 whose gates are supplied with a column selection signal YS. The column selection signal YS is supplied in common to the selection switch MOSFETs corresponding to four pairs of LIOs, although not particularly limited. Then, shared switch MOSFETs Q1 and Q2 are provided between the complementary bit lines BLLT and BLLB provided on the left side of the sense amplifier section, and between the complementary bit lines BLRT and BLRB provided on the right side. Shared switch MOSFETs Q3 and Q4 are provided.
[0078]
A control signal SHL is supplied to the gates of the shared switch MOSFETs Q1 and Q2, and a control signal SHR is supplied to the gates of the shared switch MOSFETs Q3 and Q4. A dynamic type memory comprising the address selection MOSFET Qm and the storage capacitor Cs at the intersections of the complementary bit lines BLLT and BLLB on the left side of the sense amplifier section and the sub word lines SWL1, SWL2, etc. arranged so as to be orthogonal thereto. A cell is provided. Similarly, the address selection MOSFET Qm and the storage capacitor Cs are formed at the intersections of the complementary bit lines BLRT and BLRB on the right side of the sense amplifier section and the sub word lines SWL3 and SWL4 arranged so as to be orthogonal thereto. A dynamic memory cell is provided.
[0079]
FIG. 14 shows a schematic element layout diagram of one embodiment of the sense amplifier unit used in the dynamic RAM according to the present invention. In this embodiment, power switch MOSFETs Q14 and Q15 for driving the sense amplifiers are distributed along the sense amplifier row. In other words, the power switch MOSFETs Q14 and Q15 having small element sizes are provided in a distributed manner in the sense amplifier row, instead of being arranged in a large size in the intersection area as described above.
[0080]
Although not particularly limited, in this embodiment, the two MOSFETs Q14 and Q15 are arranged corresponding to 16 unit circuits. In other words, the unit circuit provided at the left end will be described as an example. The shared switch MOSFETs Q1 and Q2, the MOSFET Q9-11 constituting the precharge circuit, the switch MOSFETs Q12 and Q13 constituting the column selection circuit, and the CMOS latch circuit are sequentially arranged from the upper side. The P-channel amplification MOSFETs Q7 and Q8 to be configured, the N-channel amplification MOSFETs Q5 and Q6 and the shared switch MOSFETs Q3 and Q4 to constitute the CMOS latch circuit with the formation region of the power switch MOSFETs Q14 and Q15 interposed therebetween are arranged.
[0081]
The power switch MOSFETs Q14 and Q15 have a channel width sufficiently larger than that of the shared switch MOSFETs Q1, Q2, etc., for example, so that the gate is extended along the sense amplifier row. A large current can be passed. In this case, the MOSFET Q14 that drives the common source line CSN of the N-channel MOSFET is supplied with the power supply voltage VDD or the boosted voltage VPP at the gate because the voltage supplied to the gate is relatively low like VDL. The size is larger than that of the MOSFET Q15.
[0082]
When the power switch MOSFETs for driving the sense amplifiers are distributed in this way, the distance between the sense node and the power switch MOSFET can be shortened, and the operation timings of the plurality of sense amplifiers provided in the subarray can be made uniform with each other. In addition, the cross area can be divided into another pair of short-circuited MOSFETs M1 and M2, and in addition to this, a sub-amplifier circuit comprising MOSFETs Q4 to Q7, or a precharge MOSFET such as MOSFETs M3 to M6 as required. It can be used effectively to provide.
[0083]
The effects obtained from the above embodiment are as follows.
(1) The signals of the plurality of complementary bit line pairs in the memory cell array are each amplified by a plurality of first amplifier circuits, and the plurality of first amplifier circuits are selected by the first selection circuit to form the first common complementary line pair. The first common complementary line pair is connected to the second common complementary line pair from the second selection circuit corresponding to a plurality of memory blocks having such circuits, and the second common complementary line pair is connected to the predetermined number. In a semiconductor memory device including a first precharge circuit for applying a voltage and an amplifier circuit for amplifying a read signal from the memory cell transmitted to the second common complementary line pair, both sides of the plurality of first selection circuits A pair of short-circuit MOSFETs for short-circuiting the first common complementary line pair and the second common complementary pair, respectively, and setting the second selection circuit in a selected state during a precharge period of the first precharge circuit. By turning on the short-circuit MOSFET and making the potentials of the signal line pairs equal, it is possible to obtain an effect that signal transmission can be performed at high speed while securing a voltage necessary for signal transmission.
[0084]
(2) In addition to the above configuration, a second precharge circuit for supplying an intermediate voltage of the operating voltage of the first amplifier circuit to the complementary bit line pair is provided, and one of the memory cells is selected by the selection of the word line. The first amplifying circuit performs an amplifying operation on the read signal appearing on one bit line by using the precharged intermediate voltage on the other bit line as a reference voltage, and the first common complementary line pair includes the first signal. By providing the third precharge circuit that precharges the first common complementary line pair that has not been selected in the selection circuit to the intermediate voltage, an effect that the operation can be stabilized can be obtained.
[0085]
(3) In addition to the above configuration, as the first amplifier circuit, a CMOS latch circuit composed of a pair of P-channel MOSFET and N-channel MOSFET whose gate and drain are cross-connected, and a sense amplifier By using the switch MOSFET that applies the operating voltage to the sources of the P-channel MOSFET and the N-channel MOSFET during the operation period, it is possible to obtain a highly sensitive sensing operation.
[0086]
(4) In the dynamic RAM, a selection circuit is provided for a plurality of memory blocks that connect the input / output nodes of the sense amplifier to the local input / output line pairs by a column selection circuit controlled by a column selection signal. A first precharge circuit connected to the main input / output line pair and applying a predetermined voltage to the main input / output line pair is provided, and the local input / output line pair and the main input / output line pair are provided on both sides of the plurality of selection circuits. A pair of short-circuit MOSFETs for short-circuiting each other, and turning on the pair of short-circuit MOSFETs during the precharge period of the first precharge circuit to equalize the main input / output line pair and local input / output line pair potentials. , Signal transmission at high speed while ensuring the voltage necessary for signal transmission in read and write operations The effect that it can be made is obtained.
[0087]
(5) In addition to the above configuration, a second precharge circuit for supplying an intermediate voltage of the operation voltage of the sense amplifier to the complementary bit line pair is provided, and one bit is selected from the memory cell by selecting the word line. A read signal appearing on the line is used as a reference voltage by using the precharged intermediate voltage of the other bit line as a reference voltage, and a third precharge circuit is provided in the local input / output line pair. By precharging the local input / output line pair to the intermediate voltage, the operation can be stabilized.
[0088]
(6) In addition to the above configuration, a complementary bit line pair is arranged on the left and right with the input / output node of the sense amplifier as the center, and is selected by the shared switch MOSFET, and the word line is connected to the main word line. A sub word line is selected by a sub word driver using a signal of a main word line and a signal of a sub word selection line as a hierarchical structure of a plurality of sub word lines commonly assigned to the main word line, and the sub word is excluded except for an end of the memory cell array. Sub-word line selection signals provided on the left and right sides of the driver are formed, and the amplified signals from the complementary bit lines provided on the left and right sides of the sense amplifier are detected except for the ends of the memory cell array. The effect that high-density arrangement of lines and complementary bit lines is also possible is obtained.
[0089]
(7) In addition to the above-described configuration, the memory cells are arranged in a matrix state in a region surrounded by the sub-word driver and the sense amplifier to form a sub-array, and correspond to sub-arrays that are geometrically adjacent to each other. By providing the selection circuit and the pair of short-circuit MOSFETs in an intersecting region between the sub-word driver and the sense amplifier, an effect that a high-density arrangement is possible can be obtained.
[0090]
(8) In addition to the above configuration, the latch circuit is supplied with the operating voltage via a power switch MOSFET, and the power switch MOSFET is formed in the semiconductor region where the sense amplifier is formed. By providing a plurality of sets so that each of the plurality of latch circuits is shared, the cross region can be effectively used.
[0091]
(9) In addition to the above configuration, the pair of short-circuit MOSFETs are P-channel MOSFETs to which a common control signal is supplied, thereby reducing the number of control signal lines and the precharge voltage VDL according to the normal signal level. The effect that the short circuit operation corresponding to can also be performed is acquired.
[0092]
(10) In addition to the above configuration, by making the control signal the same as the precharge control signal of the first precharge circuit, it is possible to simplify the control circuit.
[0093]
(11) In addition to the above-described configuration, the local input / output line pair includes a MOSFET in which a gate and a drain are cross-connected, and a sub-amplifier circuit for amplifying a signal transmitted thereto is provided in the crossing region. Further providing in FIG. 4 provides an effect that the short-circuit operation of the short-circuit MOSFET can be more effectively utilized to achieve high-speed read and write operations.
[0094]
(12) In addition to the above configuration, the precharge operation can be speeded up by further providing a fourth precharge circuit corresponding to each of the selection circuits and the same as the first precharge circuit. The effect that it can be obtained.
[0095]
(13) In addition to the above configuration, the fourth precharge circuit is provided on both the main input / output line pair side and the local input / output line pair side while being provided on the local input / output line pair side. By stopping the operation of the fourth precharge circuit when the corresponding local input / output line pair is not selected, it is possible to further increase the speed of the precharge operation and stabilize the unselected bit line. can get.
[0096]
(14) In addition to the above-described configuration, the first precharge circuit and the fourth precharge circuit are configured by P-channel MOSFETs, so that the control signal is shared and the signal level is set to a normal level. The effect that a logic level can be used is acquired.
[0097]
The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the dynamic RAM shown in FIG. 1, FIG. 2, etc., the configurations of the memory array, sub-array and sub-word driver can take various embodiments, and the input / output interface of the dynamic RAM has a synchronous specification. In addition, various embodiments such as those adapted to Rambus specifications can be adopted.
[0098]
The word line may adopt a word shunt method in addition to the hierarchical word line method as described above. The semiconductor memory device can be similarly applied to a read-only memory such as a static RAM, EPROM, or EEPROM in addition to the DRAM as described above, in which the IO line has a hierarchical structure as described above. . The present invention can be widely used in a semiconductor memory device in which IO lines have a hierarchical structure as described above and a semiconductor device including such a memory circuit.
[0099]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. A plurality of complementary bit line pair signals in the memory cell array are each amplified by a plurality of first amplifier circuits, the plurality of first amplifier circuits are selected by a first selection circuit and connected to the first common complementary line pair, The first common complementary line pair is connected to the second common complementary line pair from the second selection circuit in correspondence with a plurality of memory blocks having such circuits, and a predetermined voltage is applied to the second common complementary line pair. In a semiconductor memory device including a first precharge circuit and an amplifier circuit for amplifying a read signal from the memory cell transmitted to the second common complementary line pair, the first selection circuit is formed on both sides of the plurality of first selection circuits. A pair of short-circuit MOSFETs for short-circuiting each of the one common complementary line pair and the second common complementary pair are provided, and the second selection circuit is set in a selected state during the precharge period of the first precharge circuit and the short The MOSFET is turned on and by equalizing the potentials of the respective signal line pairs, the signal transmission can be performed at high speed while maintaining the voltage necessary for signal transduction.
[Brief description of the drawings]
FIG. 1 is a schematic chip layout diagram showing one embodiment of a dynamic RAM to which the present invention is applied.
FIG. 2 is a schematic layout diagram showing one embodiment of a memory array constituting one memory bank in the dynamic RAM according to the present invention.
FIG. 3 is a schematic layout diagram showing one embodiment of a sub-array and its peripheral circuits in the dynamic RAM according to the present invention.
FIG. 4 is a schematic layout diagram showing one embodiment of a memory array constituting one memory bank in the dynamic RAM according to the present invention.
FIG. 5 is a partially enlarged view of the memory array shown in FIG. 4;
FIG. 6 is a schematic layout diagram showing one embodiment of a memory array constituting one memory bank in the dynamic RAM according to the present invention.
FIG. 7 is a principal circuit diagram showing one embodiment of a semiconductor memory device according to the present invention;
FIG. 8 is a principal circuit diagram showing another embodiment of the semiconductor memory device according to the present invention;
FIG. 9 is a main portion circuit diagram showing another embodiment of the semiconductor memory device according to the present invention;
FIG. 10 is a principal circuit diagram showing one embodiment of a semiconductor memory device according to the present invention;
FIG. 11 is a timing chart for explaining an example of the operation of the semiconductor memory device according to the present invention.
FIG. 12 is a timing chart for explaining the semiconductor memory device according to the present invention.
FIG. 13 is a circuit diagram showing one embodiment of a sense amplifier section of a dynamic RAM according to the present invention.
FIG. 14 is a schematic element layout diagram showing one embodiment of a sense amplifier unit used in the dynamic RAM according to the present invention.
FIG. 15 is a circuit diagram showing one embodiment of a dynamic RAM according to the present invention.
FIG. 16 is an operation waveform diagram showing an example of the operation of the semiconductor memory device according to the present invention.
[Explanation of symbols]
IS ... intersection area, SA ... sense amplifier, SWD ... subword driver, YDEC ... Y decoder, MA ... main amplifier,
Q1-Q14 ... MOSFET, M1, M2 ... Short-circuit MOSFET, M3-M6 ... Precharge MOSFET,
DESCRIPTION OF SYMBOLS 11, 12 ... Decoder, main word driver, 15 ... Subarray, 16 ... Sense amplifier, 17 ... Subword driver, 18 ... Cross area, 51 ... Address buffer, 52 ... Predecoder, 53 ... Decoder, 61 ... Main amplifier, 62 ... Output buffer, 63 ... input buffer,

Claims (23)

A memory cell array comprising a plurality of word lines, a plurality of complementary bit line pairs, and a plurality of memory cells provided corresponding to the word lines and the complementary bit line pairs;
A plurality of first amplifier circuits each for amplifying signals of the plurality of complementary bit line pairs;
A first selection circuit for selecting the plurality of first amplification circuits;
A plurality of memory blocks each including a first common complementary line pair provided for the first selection circuit;
A plurality of second selection circuits for selecting the first common complementary line pair corresponding to the plurality of memory blocks;
A second common complementary line pair provided for the plurality of second selection circuits;
A first precharge circuit for applying a predetermined voltage to the second common complementary line pair;
An amplification circuit for amplifying a read signal from the memory cell transmitted to the second common complementary line pair;
A pair of MOSFETs for short-circuiting the first common complementary line pair and the second common complementary pair are provided on both sides of the plurality of second selection circuits,
During the precharge period of the first precharge circuit, the second selection circuit is set in a selected state, the pair of short-circuit MOSFETs are turned on, and the voltages on both sides of the corresponding second selection circuit are changed from the first precharge circuit. A semiconductor memory device, characterized by being substantially equal to a voltage corresponding to the predetermined potential supplied. Oite the semiconductor memory device according to claim 1,
The complementary bit line pair is provided with a second precharge circuit for supplying an intermediate voltage of the operating voltage of the first amplifier circuit,
The first amplifier circuit amplifies a read signal that appears on one bit line from a memory cell by selecting the word line, using the precharged intermediate voltage of the other bit line as a reference voltage. ,
Above first common complementary line pair is provided a third precharge circuit, a semiconductor characterized by precharging the first common complementary line pair in the non-selected in the first selection circuit to the intermediate voltage Storage device. Oite the semiconductor memory device according to claim 2,
The first amplifier circuit includes a CMOS latch circuit composed of a pair of P-channel MOSFET and N-channel MOSFET whose gate and drain are cross-connected,
A semiconductor memory device comprising a switch MOSFET for applying an operating voltage to the sources of the P-channel MOSFET and N-channel MOSFET during an operation period of a sense amplifier. A plurality of word lines formed by connecting address selection terminals of a plurality of dynamic memory cells, and
A plurality of complementary bit line pairs each including a plurality of dynamic memory cells connected to each other;
A sense amplifier including a plurality of latch circuits each of which receives an operating voltage in response to an operation timing signal and amplifies the signals of the complementary bit line pairs;
A column selection circuit that is switch-controlled by a column selection signal;
A plurality of memory blocks each comprising a local input / output line pair connected to the input / output node of the sense amplifier by the column selection circuit;
A selection circuit that is switch-controlled by a selection signal and provided for the plurality of memory blocks;
A main input / output line pair connected to a plurality of local input / output lines corresponding to the plurality of memory blocks via the selection circuit;
A first precharge circuit for applying a predetermined voltage to the main input / output line pair;
A main amplifier for amplifying a read signal from the memory cell transmitted to the main input / output line pair;
A pair of short-circuit MOSFETs for short-circuiting the local input / output line pair and the main input / output line pair are provided on both sides of the plurality of selection circuits, and the pair of short-circuit MOSFETs are turned on during the precharge period of the first precharge circuit. A semiconductor memory device characterized by being in a state. Oite the semiconductor memory device according to claim 4,
The complementary bit line pair is provided with a second precharge circuit for supplying an intermediate voltage of the operating voltage of the sense amplifier,
The sense amplifier amplifies a read signal that appears on one bit line from the memory cell by selection of the word line, using the precharged intermediate voltage of the other bit line as a reference voltage,
3. The semiconductor memory device according to claim 1, wherein a third precharge circuit is provided in the local input / output line pair, and the local input / output line pair not selected in the selection circuit is precharged to the intermediate voltage. Oite the semiconductor memory device according to claim 5,
The sense amplifier has an input / output node having a pair of complementary bit lines arranged on the left and right around the input / output node and a shared switch MOSFET for selectively connecting the pair of complementary bit lines arranged on the left and right to the input / output node. Further comprising
The word line is composed of a main word line and a plurality of sub word lines commonly assigned to the main word line.
The gate of the address selection MOSFET of the dynamic memory cell is connected to the sub word line,
One of the plurality of sub word lines is selected by a sub word driver that receives a signal of the main word line and a signal of a sub word selection line,
The sub-word driver forms a selection signal for sub-word lines provided on the left and right with the exception of the end of the memory cell array,
2. The semiconductor memory device according to claim 1, wherein the sense amplifier senses an amplified signal from complementary bit lines provided on the left and right sides of the memory cell array except for an end portion thereof. Oite the semiconductor memory device according to claim 6,
In the semiconductor region where the sub-word driver and the sense amplifier are formed,
The memory cells are arranged in a matrix state in a region surrounded by these to form a subarray,
The selection circuit and the pair of short-circuit MOSFETs are provided in an intersection region sandwiched between the sub-word driver and the sense amplifier corresponding to sub-arrays that are geometrically adjacent to each other on the semiconductor region. Semiconductor memory device. Oite the semiconductor memory device according to claim 7,
The operating voltage is applied to the latch circuit via a power switch MOSFET,
Such a power switch MOSFET is provided in a semiconductor region where the sense amplifier is formed.
A semiconductor memory device characterized in that a plurality of sets are provided so as to share a plurality of latch circuits formed therein. Oite the semiconductor memory device according to any one of claims 4 to 8,
The pair of short-circuit MOSFETs are P-channel MOSFETs to which a common control signal is supplied. Oite the semiconductor memory device according to claim 9,
The semiconductor memory device, wherein the control signal is the same as a precharge control signal of the first precharge circuit. Oite the semiconductor memory device according to any one of claims 8 to 10,
The local input / output line pair includes a MOSFET in which a gate and a drain are cross-connected,
A semiconductor memory device, wherein a sub-amplifier circuit for amplifying a signal transmitted thereto is further provided in the crossing region. Oite the semiconductor memory device according to claim 7,
A semiconductor memory device, further comprising a fourth precharge circuit corresponding to each of the selection circuits, the same as the first precharge circuit. Oite the semiconductor memory device according to claim 12,
The fourth precharge circuit is provided on both the main input / output line pair side and the local input / output line pair side,
4. The semiconductor memory device according to claim 4, wherein the operation of the fourth precharge circuit provided on the local input / output line pair side is stopped when the corresponding local input / output line pair is not selected. Oite the semiconductor memory device according to claim 12 or 13,
The semiconductor memory device, wherein the first precharge circuit and the fourth precharge circuit are constituted by P-channel MOSFETs. Multiple word lines,
Multiple bit lines,
A plurality of memory cells provided corresponding to the plurality of word lines and the plurality of bit lines;
A first amplifier circuit coupled to the plurality of bit lines and amplifying the voltages of the plurality of bit lines;
A circuit for supplying a signal to the plurality of word lines;
A first transmission line pair provided corresponding to the plurality of bit lines and transmitting data;
A second transmission line pair for transmitting data;
A second amplifier circuit coupled to the second transmission line pair for amplifying the voltage of the second transmission line pair;
A switch circuit coupled to the first transmission line pair and the second transmission line pair;
A P-channel first MOSFET having a source-drain path coupled to the two transmission lines constituting the first transmission line pair;
It and a second 2MOSFET of P-channel type having a drain path, - source coupled between the two transmission lines that constitute the second transmission line pairs
The first MOSFET and the second MOSFET are disposed on both sides of the switch circuit,
The plurality of word lines, the plurality of bit lines, and the plurality of memory cells are formed in a first quadrilateral region,
The first amplifier circuit is formed in a second quadrangular region adjacent to the first quadrangular region in the extending direction of the plurality of bit lines,
A circuit for supplying a signal to the plurality of word lines is formed in a third quadrilateral region adjacent to the first quadrangular region in an extending direction of the plurality of word lines;
The first MOSFET and the second MOSFET are formed in a fourth quadrilateral region adjacent to the second and third quadrilateral regions. Oite the semiconductor memory device according to claim 15,
The switch circuit includes a first 3MOSFET having a source-drain engaged binding between one of the one and the second transmission line pair of said first transmission line pair,
A semiconductor device comprising: a fourth MOSFET having a source and a drain coupled to the other of the first transmission line pair and the other of the second transmission line pair. Oite the semiconductor memory device according to claim 15,
The semiconductor device according to claim 1, wherein the switch circuit is formed in the fourth quadrangular region. Oite the semiconductor memory device according to claim 15,
The plurality of bit lines constitute a plurality of bit line pairs, and the first amplifier circuit includes a plurality of unit amplifier circuits provided corresponding to the plurality of bit line pairs. Multiple word lines,
Multiple bit lines,
A plurality of memory cells provided corresponding to the plurality of word lines and the plurality of bit lines;
A first amplifier circuit coupled to the plurality of bit lines and amplifying the voltages of the plurality of bit lines;
A first transmission line pair that is provided in common to the plurality of bit lines and transmits data;
A second transmission line pair for transmitting data;
A second amplifier circuit coupled to the second transmission line pair for amplifying the voltage of the second transmission line pair;
A first switch circuit coupled between the first transmission line pair and the second transmission line pair;
A second switch circuit coupled between two transmission lines constituting the first transmission line pair;
A third switch circuit coupled between two transmission lines constituting the second transmission line pair;
The second switch circuit and the third switch circuit are disposed on both sides of the first switch circuit,
A first voltage supply circuit coupled to the first transmission line pair and supplying a first voltage to the first transmission line pair;
A second voltage supply circuit coupled to the second transmission line pair and supplying a second voltage to the second transmission line pair;
The second switch circuit is turned on when the first voltage supply circuit supplies the first voltage to the first transmission line pair, and the two voltage supply circuit transmits the second voltage to the second transmission. wherein a is a conductive state with Oite the first switch circuit when supplied to the wire pair. Oite the semiconductor memory device according to claim 19,
The second switch circuit includes a first MOSFET having a source-drain path coupled between two transmission lines constituting the first transmission line pair,
The first switch circuit includes a second MOSFET having a source-drain coupled between one of the first transmission line pairs and one of the second transmission line pairs;
A semiconductor device comprising: a third MOSFET having a source-drain coupled to the other of the first transmission line pair and the other of the second transmission line pair. Oite the semiconductor memory device according to claim 19,
The first voltage is a precharge voltage of the first amplifier circuit,
The second voltage is a precharge voltage of the second amplifier circuit,
The semiconductor device, wherein the first voltage and the second voltage are different voltages. Multiple word lines,
Multiple bit lines,
A plurality of memory cells provided corresponding to the plurality of word lines and the plurality of bit lines;
A first amplifier circuit coupled to the plurality of bit lines and amplifying the voltages of the plurality of bit lines;
A first transmission line pair provided for the plurality of bit lines and transmitting data;
A second transmission line pair for transmitting data;
A second amplifier circuit coupled to the second transmission line pair for amplifying the voltage of the second transmission line pair;
A first switch circuit coupled between the first transmission line pair and the second transmission line pair;
A second switch circuit coupled between two transmission lines constituting the first transmission line pair;
A third switch circuit coupled between the two transmission lines constituting the second transmission line pair;
The second switch circuit and the third switch circuit are disposed on both sides of the first switch circuit,
The second switch circuit and the third switch circuit are controlled by a common signal ,
When the first switch circuit is conductive, the first transmission line pair is controlled to the same voltage as the second transmission line pair, and when the first switch circuit is not conductive, the first transmission line pair wherein a Rukoto is controlled to a voltage different from the second transmission line pair. Oite the semiconductor memory device according to claim 22,
The second switch circuit includes a P-channel type first MOSFET having a source-drain coupled to two transmission lines constituting the first transmission line pair,
The third switch circuit includes a P-channel type second MOSFET having a source-drain coupled to two transmission lines constituting the second transmission line pair,
The gate of the first MOSFET and the gate of the second MOSFET receive the common signal,
It said first switch circuit includes a first 3MOSFET having a source-drain engaged binding between one of the one and the second transmission line pair of said first transmission line pair,
A semiconductor device comprising: a fourth MOSFET having a source and a drain coupled to the other of the first transmission line pair and the other of the second transmission line pair.

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