JPH1154726A - Dynamic ram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a dynamic RAM wherein high scale integration and low consumption power are enable, by a method wherein a subword selection line is arranged to a plurality of subarrays, passing on the subarrays. SOLUTION: Every two memory arrays are arranged on the left and the right of the longitudinal direction of a semiconductor chip. An address input circuit, a data input and output circuit, and an input and output interface circuit constituted of a bonding pad row, etc., are arranged on the center part 14, and column decoder regions 13 are arranged on parts in contact with the memory arrays. Main row decoder regions 11 are arranged on the upper and lower central parts to the longitudinal direction, main word driver regions 12 are formed on and under the main row decoder regions 11, and main word lines of vertically divided memory arrays are driven, respectively. Thereby a practical threshold voltage value can be increased, a subthreshold leakage current can be reduced, special isolation of a P-type well region in which the direct peripheral circuits are formed is unnecessary, and high scale integration is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM (random access memory), for example, a MOSFET having a low threshold voltage while employing a divided word line system having a main word line and a sub word line. (Insulated gate field effect transistor).

[0002]

2. Description of the Related Art As is well known, a dynamic memory cell comprises an address selection MOSFET and an information storage capacitor, and performs an information storage operation depending on whether or not electric charge exists in the capacitor. The storage charge of the capacitor is lost due to a subthreshold leak current flowing through the source and drain paths of the address selection MOSFET in the off state. Therefore, in the conventional dynamic RAM,
A back bias voltage is supplied to the substrate from the viewpoints of reducing the sub-threshold leakage current by increasing the threshold voltage of the address selection MOSFET and reducing the parasitic capacitance at the source and drain diffusion layers connected to the bit line side. Is what you do. On the other hand, MOSFETs other than the address selection MOSFET are electrically connected to the semiconductor region in which the memory cell is formed from the viewpoint that operating at a low threshold voltage is advantageous in operating speed. A bias voltage such as a circuit ground potential is applied to the isolated semiconductor region. A so-called triple well structure is employed for such electrical semiconductor region separation.

As shown in the schematic sectional view of FIG.
In the heavy well structure, the back bias voltage VB
The P-type well region PWELL in which B is applied and the memory cell is formed is electrically separated from the P-type well region in which the peripheral N-channel MOSFET where the ground potential VSS of the circuit is applied is electrically separated from the P-type well region. It is formed in a deep N-type well region DWELL formed in the substrate P-sub. An N-type well region N for isolation is provided between the N-type MOSFET and a P-type well region PWELL in which a direct peripheral circuit such as a sense amplifier is formed.
A WELL is formed.

[0004]

The element is further miniaturized to achieve a large storage capacity and a high degree of integration, and accordingly, the threshold voltage of the MOSFET is further reduced. Leakage current flowing in the source-drain path when the MOSFET is off due to a low threshold voltage of such a MOSFET (hereinafter referred to as threshold leakage current)
This causes a problem that current consumption increases. Further, in the triple well structure, it is necessary to separate a P-type well region in which a memory cell is formed from a P-type well region in which an N-channel MOSFET of a direct peripheral circuit is formed. Has been prevented.

An object of the present invention is to provide a dynamic RAM realizing high integration and low power consumption. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, an amplification MOSFET of a sense amplifier for amplifying a minute voltage according to the information charge of the storage capacitor read from the dynamic memory cell to the bit line from the dynamic memory cell, and a precharge for applying a precharge voltage to the bit line MOSF
ET, column switch MOSFET to select bit line
Wherein the N-channel MOSFET of the memory array is formed in a deep N-type well region and formed in a P-type well region to which a negative substrate back bias voltage is applied. The P-channel MOSFET of the array is formed in the N-well region formed in the deep N-well region and supplied with a boosted voltage corresponding to the word line selection level.

[0007]

FIG. 1 is a schematic layout diagram showing one embodiment of a dynamic RAM according to the present invention. In the figure, of the circuit blocks constituting the dynamic RAM, a portion related to the present invention is shown so as to be understood. It is formed on one semiconductor substrate.

In this embodiment, although not particularly limited, the memory array is divided into four as a whole. Two memory arrays are divided into two on the left and right sides in the longitudinal direction of the semiconductor chip, and an address input circuit, a data input / output circuit, an input / output interface circuit including a bonding pad row, and the like are provided in the central portion 14. Column decoder regions 13 are arranged in portions of both sides of the central portion 14 in contact with the memory array.

As described above, in each of the four memory arrays divided into two on the left and right and two on the upper and lower sides with respect to the longitudinal direction of the semiconductor chip, the main row decoder is disposed at the upper and lower central parts in the longitudinal direction. An area 11 is provided. Main word driver regions 12 are formed above and below the main row decoder, and drive the main word lines of the vertically divided memory array.

The above-mentioned memory cell array (sub-array) 15
Are formed so as to be surrounded by the sense amplifier region 16 and the sub-word driver region 17 with the memory cell array 15 interposed therebetween, as shown in the enlarged view. An intersection between the sense amplifier region and the sub-word driver region is an intersection region (cross area) 18. The sense amplifiers provided in the sense amplifier region 16 are configured by a shared sense method, and except for the sense amplifiers arranged at both ends of the memory cell array, complementary bit lines are provided on the left and right around the sense amplifier. Selectively connected to the complementary bit lines of the memory cell array.

As described above, the memory arrays divided into four on the left and right sides in the longitudinal direction of the semiconductor chip are arranged in groups of two. In the two memory arrays thus arranged in pairs, the main row decoder region 11 and the main word driver 12 are arranged in the center. This main row decoder 11
It is provided in common corresponding to the two memory arrays which are divided up and down around the center. The main word driver 12 generates a selection signal of a main word line extended so as to penetrate the one memory array. Also,
The main word driver 12 is also provided with a driver for selecting a sub-word, and extends in parallel with the main word line to form a selection signal for the sub-word selection line, as described later.

Although not shown, one memory cell array (sub-array) 15 shown as an enlarged view has 256 sub-word lines and 256 pairs of complementary bit lines (or data lines) orthogonal thereto. In the one memory array, 16 memory cell arrays (sub arrays) 15 are provided in the word bit line direction. Therefore, the sub word lines as a whole are provided for about 4K, and 8 sub word lines are provided in the word line direction. The bit line is about 2
K are provided. Since eight such memory arrays are provided in total, a large storage capacity such as 8 × 2K × 4K = 64 Mbits is provided.

The one memory array is divided into eight in the main word line direction. A sub-word driver (sub-word line driving circuit) 17 is provided for each of the divided memory cell arrays 15. The sub-word driver 17 is divided into の 長 of the length of the main word line, and forms a sub-word line selection signal extending in parallel with the length. In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. Are arranged four sub-word lines. In order to select one sub-word line from among the sub-word lines divided into eight in the main word line direction and four in the complementary bit line direction, a sub-word selection driver is used. Be placed. This sub-word selection driver is extended in the arrangement direction of the sub-word drivers.
A selection signal for selecting one of the sub-word selection lines is formed.

Focusing on the one memory array, 1
One sub-word selection line is selected in a sub-word driver corresponding to one memory cell array including a memory cell to be selected among eight memory cell arrays allocated to one main word line, resulting in one main word One sub-word line is selected from 8 × 4 = 32 sub-word lines belonging to the line. As described above, 2K (2048) memory cells are provided in the main word line direction.
/ 8 = 256 memory cells are connected.
Although not particularly limited, in a refresh operation (for example, a self-refresh mode), eight sub-word lines corresponding to one main word line are selected.

As described above, one memory array has a storage capacity of 4K bits in the complementary bit line direction. However, if as many as 4K memory cells are connected to one complementary bit line, the parasitic capacitance of the complementary bit line increases, and a signal level that is read out cannot be obtained due to the capacitance ratio with a fine information storage capacitor. To
It is also divided into 16 in the complementary bit line direction. That is,
The complementary bit line is divided into 16 by the sense amplifier 16 indicated by a thick black line. Although not particularly limited, the sense amplifiers 16 are configured by a shared sense system, and are provided at both ends of the memory array.
Except for the above, complementary bit lines are provided on the left and right with respect to the sense amplifier 16, and are selectively connected to one of the left and right complementary bit lines.

FIG. 2 is a schematic layout diagram for explaining a dynamic RAM according to the present invention. The figure shows a schematic layout of the entire memory chip,
The layout of one memory array divided into eight is shown. This figure illustrates the embodiment of FIG. 1 from another point of view. That is, as in FIG. 1, the memory chip is located in the left and right and up and down directions with respect to the longitudinal direction (word line direction).
Each memory array is divided into four parts, and a plurality of bonding pads and indirect peripheral circuits (Bondin peripheral circuits) such as an address buffer, a control buffer, a predecoder, a timing control circuit, etc.
g Pad & perifheral Circuit).

Each of the two memory arrays has a storage capacity of about 8 Mbits, and one of them is divided into eight in the word line direction as shown in an enlarged manner. A sub-array divided into 16 in the bit line direction is provided. On both sides of the sub-array in the bit line direction, sense amplifiers (Sence Amplifiers) are arranged in the bit line direction. A sub-word driver (Sub-Wo) is provided on both sides of the sub-array in the word line direction.
rd Driver) is placed.

The one array is provided with a total of 4096 word lines and 2048 pairs of complementary bit lines.
As a result, the storage capacity is about 8 Mbits in total. As described above, 4096 word lines are divided into 16 sub-arrays and arranged, so that one sub-array is provided with 256 word lines (sub-word lines). In addition, since 2048 pairs of complementary bit lines are divided into eight sub-arrays as described above, one sub-array is provided with 256 pairs of complementary bit lines.

At the center of the two arrays, a main row decoder is provided. That is, on the left side of the array shown in the figure, an array control circuit and a main word driver (Main Word driver) are provided corresponding to the main row decoder provided in common with the array provided on the right side. Is provided. The array control circuit includes a driver for driving the first sub-word selection line. A main word line extending so as to penetrate the eight divided sub-arrays is arranged in the array. The main word driver drives the main word line. Like the main word line, the first sub-word selection line is extended so as to pass through the eight divided sub-arrays. Above the array, a Y decoder (YDecoder) and a Y select line driver (YS
driver).

FIG. 3 is a schematic layout diagram showing one embodiment of a subarray and its direct peripheral circuits in a dynamic RAM according to the present invention. FIG.
Are exemplarily shown as representatives of the four sub-arrays SBARY arranged at hatched positions in the memory array shown in FIG. By shading the region where the sub-array SBARY is formed, the sub-word driver region, the sense amplifier region, and the cross area provided around the region are distinguished.

The subarray SBARY is divided into the following four types. That is, when the extending direction of the word line is the horizontal direction, the first sub-array SBA
RY has 256 sub-word lines SWL and 256 complementary bit line pairs. Therefore, the above 2
The 256 sub-word drivers SWD corresponding to the 56 sub-word lines SWL are connected to the left and right of the sub-array by one.
It is divided into 28 pieces and arranged. The 256 sense amplifiers SA provided corresponding to the 256 pairs of complementary bit lines BL are of a shared sense amplifier type as described above, and are divided into 128 units above and below the sub-array.

As described above, the second sub-array SBARY arranged on the upper right has 256 sub-word lines SWL.
In addition to the book, eight spare word lines are provided. Therefore, the 264 sub-word drivers SWD corresponding to the above-mentioned 256 + 8 sub-word lines SWL are divided and arranged on the left and right of the sub-array in units of 132. As described above, the lower right sub-array has 256 pairs of complementary bit lines B
L, and 128 sense amplifiers are arranged vertically as described above. The 128 pairs of complementary bit lines formed in the upper and lower sub-arrays SBARY on the right side are commonly connected to the sense amplifier SA interposed therebetween via a shared switch MOSFET.

The third sub-array SBARY arranged at the lower left as described above is composed of 256 sub-word lines SWL, like the sub-array SBARY adjacent to the right.
As described above, 128 sub-word drivers are divided and arranged. The subarrays SBA arranged on the lower left and right sides
The 128 sub-word lines SWL of RY correspond to the 128 sub-word drivers SW formed in the region sandwiched between them.
D is commonly connected. The subarray SBARY arranged at the lower left as described above has four pairs of spare bit lines 4RE in addition to 256 pairs of normal complementary bit lines BL.
D is provided. Therefore, the 260 sense amplifiers SA corresponding to the 260 pairs of complementary bit lines BL are:
130 sub-arrays are divided and arranged above and below the sub-array.

As described above, the fourth sub-array SBARY arranged at the upper left has 256 regular sub-word lines SWL and eight spare sub-word lines R similarly to the right adjacent sub-array SBARY. Similarly, since four spare bit lines are provided in addition to the 256 normal complementary bit line pairs, the sub-word driver can
132 parts are arranged on the left and right sides, respectively.
A is arranged by dividing 130 vertically.

The main word lines MWL are extended as one of them is exemplarily shown as a representative. The column selection line YS is extended in the vertical direction in the figure as one of them is exemplarily shown as a representative. The main word line M
A sub-word line SWL is arranged in parallel with WL, and a complementary bit line BL (shown) is arranged in parallel with the column selection line YS. In this embodiment, although not particularly limited, the above-described four sub-arrays are used as a basic unit in FIG.
In the memory array for 8M bits as described above, eight sets of sub-arrays are formed in the bit line direction, and four sets of sub-arrays are formed in the word line direction. One set of 4 subarrays
Therefore, in the memory array of 8M bits, 8 × 4 × 4 = 128 sub-arrays are provided.
Since eight 8M-bit memory arrays are provided in the entire chip, 128 × 8 = 10 in the entire memory chip.
As many as 24 sub-arrays are formed.

Although not particularly limited, eight sub-word select lines FX0B to FX0B to
FX7B has four sets (8) in the same manner as the main word line MWL.
) Of the sub-arrays. Four sub-word selection lines FX0B to FX3B and F
X4B to FX7B are separately extended on the upper and lower sub-arrays. The reason why one set of sub-word selection lines FX0B to FX7B are allocated to the two sub-arrays and they are extended on the sub-arrays is to reduce the memory chip size.

That is, when the above-mentioned eight sub-word select lines FX0B to FX7B are allocated to each sub-array and are formed in the wiring channel on the sense amplifier area, as many as 16 sub-arrays as in the memory array of FIG. Are arranged in the upper and lower memory arrays in total, so that 8 × 32 = 256 wiring channels are required. On the other hand, in the above-described embodiment, the wiring itself allocates the eight sub-word select lines FX0B to FX7B to the two sub-arrays and arranges them so as to pass over the sub-arrays. It can be formed without providing a special wiring channel.

In the first place, one main word line is provided for eight sub-word lines on the sub-array, and a sub-word selection line is used to select one of the eight sub-word lines. Is necessary. Since one main word line is formed for every eight sub word lines formed in accordance with the pitch of the memory cells, the wiring pitch of the main word lines is gentle. Therefore, it is relatively easy to form the sub-word selection line between the main word lines using the same wiring layer as the main word line.

The sub-word driver of this embodiment selects one sub-word line SWL by using a selection signal supplied through the sub-word selection line FX0B and the like and a selection signal obtained by inverting the selection signal as described later. take.
The sub-word driver employs a configuration in which the sub-word lines SWL of the sub-arrays arranged on the left and right of the sub-word driver are simultaneously selected. Therefore, as described above, for two sub-arrays, 128 × 2 = 2
The four sub-word selection lines are allocated and supplied to as many as 56 sub-word drivers. That is, focusing on the sub-word selection line FX0B, it is necessary to supply a selection signal to as many as 256 ÷ 4 = 64 sub-word drivers.

If the one extending in parallel with the main word line MWL is a first sub-word selection line FX0B,
The six sub-word selection line driving circuits FXD which are provided in the upper left cross area and receive the selection signal from the first sub-word selection line FX0B are arranged in the above-mentioned vertical direction.
A second sub-word line FX0 that supplies a selection signal to the four sub-word drivers is provided. The first sub-word selection line FX0B extends in parallel with the main word line MWL and the sub-word line SWL, while the second sub-word selection line FX0B extends in parallel with the second sub-word selection line FX0B.
Of the sub-word selection line is orthogonal to the column selection line Y
S and the parallel bit line BL. For the eight first sub-word selection lines FX0B to FX7B, the second sub-word selection lines FX0 to FX7 are divided into even numbers FX0, 2, 4, 6 and odd numbers FX1, 3, 5, 7 Then, they are distributed to sub-word drivers SWD provided on the left and right of the sub-array SBARY.

The sub word select line driving circuit FXD is
In the same drawing, as shown by a triangle, two pieces are distributed above and below one cross area. That is, as described above, in the upper left cross area, the sub-word selection line driving circuit arranged on the lower side operates the first sub-word selection line F
Two sub-word selection line driving circuits FXD corresponding to X0B and provided in the cross area of the left middle part correspond to the first sub-word selection lines FX2B and FX4B, and are provided on the upper side provided in the lower left cross area. The arranged sub-word selection line driving circuit operates the first sub-word selection line FX.
6B.

In the upper central cross area, a lower sub word select line driving circuit corresponding to the first sub word select line FX1B is provided, and two sub word select line drivers provided in the central middle cross area are driven. Circuit FXD
Correspond to the first sub-word selection lines FX3B and FX5B, and the upper sub-word selection line drive circuit provided in the cross area at the lower center corresponds to the first sub-word selection line FX7B. In the upper right cross area, the lower sub word select line drive circuit corresponds to the first sub word select line FX0B, and two sub word select line drive circuits provided in the right middle cross area. FXD corresponds to the first sub-word selection lines FX2B and FX4B, and the upper sub-word selection line driving circuit provided in the lower right cross area corresponds to the first sub-word selection line FX6B. As described above, the sub-word driver provided at the end of the memory array drives the sub-word line SWL only on the left side since there is no sub-array on the right side.

In the configuration in which the sub-word selection lines are arranged between the pitches of the main word lines on the sub-array as in this embodiment, a special wiring channel can be made unnecessary.
Even if eight sub-word selection lines are arranged in one sub-array, the memory chip does not become large. However, the sub-word selection line driving circuit F
The area is increased to form the XD, which hinders high integration. That is, in the cross area, a switch circuit IOS provided corresponding to the main input / output line MIO and the sub input / output line LIO as shown by the dotted line in FIG.
This is because there is no area allowance because peripheral circuits such as W, a power MOSFET for driving the sense amplifier, a drive circuit for driving the shared switch MOSFET, and a drive circuit for driving the precharge MOSFET are formed.

As described later, in the sub-word driver, the second sub-word selection lines FX0 to FX6 and the like
In parallel with this, a wiring for passing a selection signal corresponding to the first sub-word selection lines FX0B to FX6B is provided.
Since the load is small as described later, a special driver FXD like the second sub-word selection lines FX0 to FX6 is used.
, The first sub-word select line FX0B
To 6B are directly connected. However, the wiring layer is the second sub-word selection line FX0
The same thing as 6 is used.

Although not particularly limited, the second sub-word selection lines FX0 to FX0 corresponding to even numbers in the cross area
An N-channel type power MOSFET that supplies an internal voltage VDL that is a constant voltage to the sense amplifier as indicated by P in FIG.
T and a clamp voltage VDDC for overdrive as described later with respect to the sense amplifier as indicated by O in O.
P-channel type power MOSFET that supplies LP,
Also, as shown by N in the circle, an N-channel type power MOSFET for supplying the ground potential VSS of the circuit to the sense amplifier is provided.

Among the cross areas, those arranged in the extending direction B of the second sub-word selection lines FX0 to FX6 corresponding to the odd numbers include the precharge and equalization of the bit lines as shown by B in FIG. An N-channel drive MOSFET for turning off the MOSFET,
The circuit ground potential V with respect to the sense amplifier
N-channel type power MOSF for supplying SS
An ET is provided. This N-channel type power MOS
FET is an amplifying MOSFET of an N-channel type MOSFET constituting a sense amplifier from both sides of a sense amplifier row.
Are supplied with a ground potential. That is, for the 128 or 130 sense amplifiers provided in the sense amplifier area, the N-channel type power MOSFET provided in the cross area on the A side and the N-channel power MOSFET provided in the cross area on the B side are provided. The ground potential is supplied by both of the channel type power MOSFETs.

As described above, the sub-word line drive circuit SWD
Selects the sub-word lines of the sub-arrays on both sides with respect to the center. On the other hand, two sense amplifiers are activated corresponding to the selected sub-word lines of the two sub-arrays. That is, when the sub-word line is set to the selected state, the address selection MOSFET is turned on and the charge of the storage capacitor is combined with the bit line charge, so that the sense amplifier is activated to return to the original charge state. This is because a write operation needs to be performed.
For this reason, except for those corresponding to the subarrays at the ends, the power MOSFETs denoted by P, O and N
Is used to activate the sense amplifiers on both sides of it.

On the other hand, a sub-word line drive circuit SW provided on the right side of the sub-array provided at the end of the array
In D, only the sub-word lines of the sub-array are selected.
ET activates only the sense amplifier corresponding to the sub-array. The sense amplifier is of a shared sense type, and among the sub-arrays arranged on both sides of the shared amplifier, the shared switch MOSFE corresponding to the complementary bit line on the side where the sub-word line is not selected.
When T is turned off and disconnected, a read signal of the complementary bit line corresponding to the selected sub-word line is amplified, and a rewrite operation of returning the storage capacitor of the memory cell to the original charge state is performed.

FIG. 4 is a block diagram showing one embodiment of a dynamic RAM according to the present invention. In the drawing, a layout pattern of a well region and elements (MOSFETs) formed therein are shown in the form of a circuit diagram. In this embodiment, the N-type well region DWELL having the above-mentioned deep depth is formed in a lower layer portion on the entire surface of the memory array.
On this DWELL, a white portion is a P-type well region PWELL, a negative back bias voltage VBB is supplied to the sub-array portion, and a sub-word driver SWD
Similarly, a negative back bias voltage VBB is supplied to the P-type well region PWELL of the portion. The hatched portion is an N-type well region NWELL, and a boosted voltage VPP corresponding to the word line selection level is applied. That is, in this embodiment, the N-channel type MOSF
Since the negative back bias voltage VBB is supplied to all the P-type well regions forming the ET, the above-described N-type well region for separation is not required, and high integration can be achieved.

In the PWELL of the sub-array portion, memory cells are arranged at intersections of the complementary bit lines BL and the sub-word lines SWL of the BLB. The complementary bit line BL
And BLB are a shared switch MOSFET controlled by a control signal SHR, and an equalizing signal BL.
A precharge (equalize) circuit that switches the complementary bit lines BL and BLB to the precharge voltage VBLR under the switch control of the EQ, and an N that forms a sense amplifier
Channel type amplification MOSFET and column selection signal Y
Column switch MOSFET controlled by S
Upon receiving T and the sense amplifier activation signal SAN, a power switch MOSFET that supplies the ground potential VSS of the circuit to the N-channel amplification MOSFET is formed. The PWELL of the memory mat section is connected to the bit line B
The P-type well region PWEL in the direction of the extension of L and BLB.
In the NWELL dividing L, a P-channel MOSFET constituting the sense amplifier and a power switch MOSFET for supplying a power supply voltage VCC to the P-channel amplification MOSFET are formed. Thus, the bit lines BL and BLB are divided into left and right with the sense amplifier as a center, thereby adopting a shared sense amplifier system.

The NWELL and PWELL arranged so as to divide the memory mat in the extending direction of the word line SWL include a P-channel MOSFET and an N-channel MOSF constituting a sub-word driver SWD.
ET is formed. The local I / O line LIO is connected to the main I / O line MIO at the cross section of the NWELL.
, A CMOS switch composed of a P-channel MOSFET and an N-channel MOSFET is provided. The main input / output line MIO is provided with a precharge (equalize) circuit composed of a P-channel MOSFET at a cross portion of the NWELL.

The dynamic memory cell is provided between the sub-word line SWL provided in the one sub-array and one of the complementary bit lines BL and / BL. The dynamic memory cell has an address selection MOS
It consists of an FET and a storage capacitor. The gate of the address selection MOSFET is connected to the sub-word line SWL, one source and drain of this MOSFET are connected to the bit line BL, and the other source and drain are connected to the storage capacitor. The other electrode of the storage capacitor is shared and receives a plate voltage. The selection level of the sub-word line SWL is a high voltage VPP higher than the high level of the bit line by the threshold voltage of the address selection MOSFET. When the sense amplifier is operated at the internal step-down voltage VDL, the high level amplified by the sense amplifier and applied to the bit line is set to a level corresponding to the internal voltage VDL. Therefore, the high voltage VPP corresponding to the word line selection level is set to VDL + Vth.

FIG. 5 is a schematic sectional view of one embodiment of the dynamic RAM according to the present invention. In the well structure shown in FIG. 3A, a deep DWELL is formed in a P-type substrate P-SUB, and a P-type well region of a memory array portion is formed in the D-WELL. In addition to the address selection MOSFET of the memory cell, an N-channel MOSFET that forms a direct circuit such as a sense amplifier is also formed. Then, the P-channel MOSFET constituting the direct circuit is formed in the N-type well region NWELL. The ground potential VSS of the circuit is applied to the P-type substrate PSUB, the boost voltage VPP is applied to the deep DWELL, the negative voltage VBB is applied to the P-type well region PWELL, and the N-type well is The boosted voltage VPP is applied to the region NWELL.

In the well structure as described above, (B)
As shown in (1), in a P-channel MOSFET, a p + type source and drain are formed in an N type well region NWELL, and a gate electrode is formed on a semiconductor surface between the source and drain via a gate insulating film. In the well structure as described above, as shown in FIG.
In the FET, an n + -type source and a drain are formed in a P-type well region PWELL, and a gate electrode is formed on a semiconductor surface between the source and the drain via a gate insulating film.
Although not particularly limited, an N-channel type M as shown in FIG.
Of the OSFETs, those that constitute a memory cell have p-type impurities introduced by ion implantation into the semiconductor surface (channel) under the gate to secure a necessary information retention time, and the threshold voltages are compared. Be raised.
That is, the N-channel MOSF constituting the memory cell
An N-channel MOSF formed in the same P-type well region PWELL as ET and constituting a direct portion such as a sense amplifier.
The threshold voltage differs from ET.

As described above, the N-channel type MOSFET
Is in the P-type well region PWELL where it is formed.
Since a back bias voltage such as 1 V is applied, the threshold voltage is lowered by miniaturization of the element. However, the effective threshold voltage is reduced by the substrate effect due to the supply of the back bias voltage VBB as described above. Is raised. As a result, the sub-threshold leakage current can be significantly reduced and the power consumption can be reduced while achieving high integration by miniaturizing the elements. At the same time, in the memory array section, although the sub-array is divided into a large number by the sense amplifier and the sub-word driver, the NWELL for separation is not necessary for each sub-array as in the related art, and the PWELL formed on the same DWELL is used. Since they can be formed collectively, higher integration is possible. Further, since the above-mentioned sub-word selection line is passed over the sub-array, the semiconductor region in which the sense amplifier is formed can also be made small, so that these act synergistically to increase the storage capacity or reduce the storage capacity. If not, the chip size can be reduced.

FIG. 6 is a main block diagram for explaining the relationship between the main word lines and the sub word lines of the sub array. This figure mainly explains the circuit operation, and omits the geometrical arrangement of the sub-word selection lines as described above and collectively shows the sub-word selection lines FX0B to FX7B. In the figure, two main word lines MWL0 and MWL1 are shown as representatives for explaining the sub-word line selection operation. These main word lines MWL0 are selected by a main word driver MWD0. The other main word line MWL1 is similarly selected by a main word driver similar to the above.

The one main word line MWL0 has:
Eight sets of sub-word lines are provided in the extending direction. FIG. 2 exemplarily shows two sets of the sub-word lines as representatives. The sub word line is even 0 to
A total of eight sub-word lines 6 and odd numbers 1 to 7 are alternately arranged in one sub-array. Except for even numbers 0 to 6 adjacent to the main word driver and odd numbers 1 to 7 arranged on the far end side (opposite side of the word driver) of the main word line,
The sub-word driver arranged between the sub-arrays drives the sub-word lines of the left and right sub-arrays centered on the sub-word driver.

As a result, although the sub-array is divided into eight as described above, the sub-word lines corresponding to the two sub-arrays are simultaneously selected by the sub-word driver SWD substantially as described above. The sub-array is divided into four sets. As described above, the sub word line SWL is divided into even numbers 0 to 6 and even numbers 1 to 7,
Sub word drivers S are provided on both sides of each memory block.
In the configuration in which the WDs are arranged, the substantial pitch of the sub-word lines SWL arranged at high density in accordance with the arrangement of the memory cells can be relaxed twice in the sub-word driver SWD.
The sub-word driver SWD and the sub-word line SWL can be efficiently laid out on a semiconductor chip.

In this embodiment, the sub-word driver SWD supplies a selection signal from the main word line MWL to four sub-word lines 0 to 6 (1 to 7) in common. A sub-word select line FXB for selecting one sub-word line from the four sub-word lines is provided. The sub-word selection lines are composed of eight lines FXB0 to FXB7, of which even-numbered FXB0 to FXB6 are supplied to the even-numbered sub-word drivers 0 to 6, and odd-numbered FXB1 to FXB7 are odd-numbered sub-word drivers 1 to 7 of the odd-numbered columns. Supplied to Sub word select line FXB0
FXB7 to FXB7 are formed by a second-layer metal (metal) wiring layer M2 on the sub-array, and the main word lines MW similarly formed by the second-layer metal wiring layer M2.
It comprises a first sub-word selection line extending in parallel with L0 to MWLn and a second sub-word selection line extending in a direction orthogonal thereto. Although not particularly limited, the second sub-word selection line is formed by a third-layer metal wiring layer M3 so as to intersect with the main word line MWL.

The sub-word driver SWD has a main word line M, as shown in FIG.
The input terminal is connected to WL, and the sub-word line S is connected to the output terminal.
A first CM including a P-channel MOSFET Q21 and an N-channel MOSFET Q22 to which WL is connected.
An OS inverter circuit and a switch MOSFET Q23 provided between the sub-word line SWL and the ground potential of the circuit and receiving the sub-word selection signal FXB. In order to connect the gate of this switch MOSFET Q23, a total of eight sub-word selection lines FX and FXB are arranged along a sub-word driver row consisting of 0, 2, 4, and 6, but in FIG. It is represented by one line.

A second CMOS inverter circuit N1 for forming an inverted signal FX of the sub-word selection signal FXB is provided as a sub-word selection line driving circuit FXD, and its output signal is used as an operating voltage terminal of the first CMOS inverter circuit. It is supplied to the source terminal of the P-channel MOSFET Q21. This second CMOS inverter circuit N
Although not particularly limited, 1 is formed in a cross area as shown in FIG. 3 and is commonly used in correspondence with a plurality (64 in the above embodiment) of sub-word drivers SWD.

In the above configuration of the sub-word driver SWD, when the main word line MWL is at the high level such as the boosted voltage VPP corresponding to the word line selection level, the N-channel type of the first CMOS inverter circuit The MOSFET Q22 is turned on, and the sub-word line SWL is set to a low level such as the ground potential of the circuit. At this time, the sub-word selection signal FXB becomes a selection level such as a low level such as the ground potential of the circuit, and the second CMOS as the sub-word selection line driving circuit FXD
Even if the output signal of the inverter circuit N1 is set to the selected level corresponding to the boosted voltage VPP, the main word line M
Depending on the non-selection level of WL, P-channel MOSFET
Since TQ21 is off, the sub word line SW
L is set to a non-selected state due to the ON state of the N-channel MOSFET Q22.

When the main word line MWL is at a low level such as the ground potential of the circuit corresponding to the selected level, the N-channel type MO of the first CMOS inverter circuit is
The SFET Q22 is turned off, and the P-channel type MO
SFET Q21 is turned on. At this time, if the sub-word selection signal FXB is at a low level such as the ground potential of the circuit, the output signal of the second CMOS inverter circuit N1 as the sub-word selection line driving circuit FXD is set to the selection level corresponding to the boosted voltage VPP. , The sub word line SWL is set to a selection level such as VPP. If,
If the sub-word selection signal FXB is at a non-selection level such as the boosted voltage VPP, the second CMOS inverter circuit N
2 becomes low level, and at the same time, N
The channel type MOSFET Q23 is turned on to set the sub-word line SWL to the low level non-selection level.

The main word line MWL and the first sub-word select line FXB arranged in parallel with the main word line MWL are both set to a non-selection level such as VPP as described above. Therefore, even when an insulation failure occurs between the main word line MWL and the first sub-word selection line FXB arranged in parallel when the RAM is in the non-selection state (standby) state, leakage current flows. There is no. As a result, the first sub-word selection line FXB can be formed between the main word lines MWL and arranged on the sub-array, and the DC failure due to the above-described leakage current can be avoided even when the layout density is increased. It will be reliable.

FIG. 7 is a main block diagram for explaining the relationship between the main word lines of the memory array and the sense amplifiers. In FIG.
Two main word lines MWL are shown. This main word line MWL is selected by the main word driver MWD. A sub-word driver SW corresponding to the even-numbered sub-word line adjacent to the main word driver
D is provided.

In the figure, although omitted, a complementary bit line (Pair Bit Line) is provided so as to be orthogonal to a sub-word line arranged in parallel with the main word line MWL. In this embodiment, although not particularly limited, the complementary bit lines are also divided into even columns and odd columns, and the sense amplifiers SA are distributed to the left and right corresponding to the respective sub-arrays (memory cell arrays). The sense amplifier SA is of the shared sense type as described above. In the sense amplifier SA at the end, although substantially one complementary bit line is not provided, the sense amplifier SA is connected to the complementary bit line via a shared switch MOSFET. Connected.

In the configuration in which the sense amplifiers SA are dispersedly arranged on both sides of the memory block as described above, since the complementary bit lines are distributed to the odd columns and the even columns, the pitch of the sense amplifier columns can be reduced. it can. In other words, it is possible to secure element areas for forming the sense amplifiers SA while arranging complementary bit lines at high density. The sub input / output lines are arranged along the arrangement of the sense amplifiers SA. This sub input / output line is connected to the complementary bit line via a column switch. The column switch is composed of a switch MOSFET. The gate of the switch MOSFET is connected to a column selection line YS to which a selection signal of a column decoder COLUMN DECORDER is transmitted.

FIG. 8 is a schematic block diagram showing one embodiment of the indirect peripheral circuit portion of the dynamic RAM according to the present invention. The timing control circuit TG includes a row address strobe signal / RAS supplied from an external terminal,
Column address strobe signal / CAS, write enable signal / WE and output enable signal / OE
In response to this, it determines the operation mode and forms various timing signals necessary for the operation of the internal circuit in response to the determination. In this specification and the drawings, the symbol / is used to mean that the low level is the active level.

Signals R1 and R3 are row-related internal timing signals, and are used for row-related selection operations.
The timing signal φXL is a signal for taking in and holding a row-related address, and is supplied to the row address buffer RAB. That is, the row address buffer RAB
Is controlled by the address signal A0 by the timing signal φXL.
ＡAi are fetched and held in the latch circuit. The timing signal φYL is a signal for taking in and holding the column address, and is supplied to the column address buffer CAB. That is, the column address buffer RAB fetches an address input from the address terminals A0 to Ai in response to the timing signal φYL and causes the latch circuit to hold the address.

The signal φREF is a signal generated in the refresh mode, and is supplied to the multiplexer AMX provided at the input of the row address buffer.
In the refresh mode, control is performed so as to switch to the refresh address signal formed by the refresh address counter circuit RFC. The refresh address counter circuit RFC counts a refresh step pulse φRC formed by the timing control circuit TG to generate a refresh address signal. In this embodiment, an auto refresh and a self refresh as described later are provided. The timing signal φX is a word line selection timing signal, and is supplied to the decoder XIB, and based on the decoded signal of the lower 2 bits of the address signal, there are four types of word line selection timing signals Xi.
B is formed. The timing signal φY is a column selection timing signal, and is supplied to the column predecoder YPD to output the column selection signals AYix, AYjx, AYkx.

The timing signal φW is a control signal for instructing a write operation, and the timing signal φR is a control signal for instructing a read operation. These timing signals φW and φR are supplied to the input / output circuit I / O to activate an input buffer included in the input / output circuit I / O at the time of a write operation, thereby bringing the output buffer into an output high impedance state. On the other hand, at the time of the read operation, the output buffer is activated, and the input buffer is set to the output high impedance state. Timing signal φM
S is a signal that instructs, but is not limited to, a memory array selection operation, is supplied to a row address buffer RAB, and a selection signal MSi is output in synchronization with this timing. Timing signal φSA is a signal for instructing the operation of the sense amplifier. An activation pulse for the sense amplifier is formed based on the timing signal φSA.

In this embodiment, the row-related redundant circuit XR
ED is illustratively shown as a representative. That is, the circuit X-RED includes a storage circuit for storing a defective address and an address comparison circuit. The stored defective address is compared with the internal address signal BXi output from the row address buffer RAB, and when they do not match, the signal XE is set to the high level, and the signal XEB is set to the low level to enable the operation of the normal circuit. When the input internal address signal BXi matches the stored defective address, the signal XE is set to low level to inhibit the operation of selecting the defective main word line of the normal circuit, and the signal XEB is set to high level to set one signal. A selection signal XRiB for selecting a spare main word line is output.

The internal voltage generating circuit VG receives the power supply voltage VDD such as 3.3 V supplied from an external terminal and the ground potential VSS of 0 V, and receives the boosted voltage VPP (+3.8
V), an internal voltage VDL (+2.2 V), a plate voltage (precharge voltage) VPL (1.1 V), and a substrate voltage VBB (-1.0 V). Although not particularly limited, the boosted voltage VPP and the substrate voltage VBB can be calculated by using a charge pump circuit and a control circuit therefor.
P and VBB are formed stably. The above internal voltage VDL
Is formed by internally lowering and stabilizing the power supply voltage VDD using a reference voltage. The plate voltage VPL and the half precharge voltage are obtained by dividing the internal step-down voltage VDL by 1 /.
It is formed by partial pressure.

FIG. 9 is a sectional view of an element structure for explaining a dynamic RAM according to the present invention. In this embodiment, the element structure of the memory cell section as described above is exemplarily shown as a representative. The storage capacitor of the memory cell uses a second polysilicon layer as a storage node SN, and uses an address selection MOSFET.
Is connected to one of the source and drain SD. The storage node SN composed of the second polysilicon layer has a crown structure, and is formed by forming a plate electrode PL composed of a third polysilicon layer via a thin gate insulating film. The gate of the address selection MOSFET is formed integrally with the sub-word line SWL, and is formed of a first polysilicon layer and a tungsten silicide (WS) formed thereon.
i). Address selection MOSFET
The other source and drain are connected to a bit line BL formed of a polysilicon layer and the same tungsten silicide provided above the polysilicon layer. A main word line MWB composed of a second metal layer M2 and a sub-word select line FXB are formed above the memory cell, and a Y select line YS composed of a third metal layer M3 is formed above the main word line MWB. Alternatively, a sub-word selection line FX is formed.

Although not shown in the figure, an N-channel MOSFET and a P-channel MOSFET which constitute a direct peripheral circuit such as the sense amplifier and the sub-word driver SWD are formed in the peripheral portion of the memory cell portion. You. To configure these direct peripheral circuits, a first metal layer is formed although not shown. For example, the above C
The wiring connecting the gates of the N-channel MOSFET and the P-channel MOSFET to form the MOS inverter circuit uses the first metal layer M1. The input terminal of the CMOS inverter circuit and 2
The connection with the main word line MWB composed of the first-layer metal layer M2 is dropped to the first-layer metal layer M1 as a dummy through a through hole, and the gate is connected to the first-layer wiring layer M1 via a contact. Connected to electrodes.

When the Y selection line YS formed of the third metal layer M3 is connected to the gate of the column selection switch MOSFET, or the sub word line selection line FX formed of the metal layer M3 and the P channel of the sub word driver are connected. The connection to the source and the drain of the MOSFET is dropped to the metal layer M2 and the metal layer M1 as the dummy via a through hole, and the column switch MOS is dropped.
It is connected to the gate of the FET and the source and drain of the P-channel MOSFET.

When adopting the element structure as in this embodiment,
As described above, the second metal layer M2 constituting the main word line intersects with the portion of the second metal layer M2 extending in parallel with the second metal layer M2 or the metal layer M2 of the main word line. When a defect occurs in the insulating film between the third word layer M3 and the sub-word selection line, a non-negligible leak current flows. Such a leak current itself is practically no problem if it does not affect the read / write operation of the memory cell, but causes a problem of a current failure in a non-selected state. In the present invention, as described above, the main word line M
Since the WB and the sub-word select line FXB are in the non-selected state at the same potential, the above-described leakage current does not occur.

When a read / write operation of a memory cell is defective due to the generation of a leak current between the main word line MWB and the sub word select line FXB, the memory cell is replaced with a spare main word line. However, the defective main word line MWB remains as it is, resulting in the leakage current continuing to flow to the main word line MWB. The occurrence of the leak current as described above does not affect the reading and writing operations of the memory itself as a result of replacing the main word line MWB with the spare main word line. However, the DC current increases, which leads to deterioration of the performance of the product. In the worst case, the DC failure occurs, so that the defect relief circuit cannot be used. Can be avoided.

FIG. 10 is a schematic circuit diagram of one embodiment of the indirect peripheral circuit used in the dynamic RAM according to the present invention. An indirect peripheral circuit such as an address buffer, a decoder, or a timing generation circuit includes N-channel MOSFETs and P-channel MOSFETs in P-type well regions and N-type well regions formed on a semiconductor substrate.
ET is formed. These MOSFETs are excellent in operation speed due to the low threshold voltage. However, even when the dynamic RAM is placed in a non-operation (standby) state, the current consumption during the non-operation increases due to the sub-threshold leakage current of the N-channel MOSFET or the P-channel MOSFET whose CMOS circuit is turned off. Let me do it.

In this embodiment, in a circuit which is set to the low level (H) during the standby, the source of the P-channel MOSFET which is turned off is the sub power supply line VD
Connected to T. In a circuit that receives the output signal of this circuit, the output signal is set to a low level (L).
As a result, the N-channel MOSFET is turned off, so that its source is connected to the sub power supply line VST. The sub power supply lines VDT and VST are connected to the power supply line VDD via P-channel switch MOSFETs (Sw-MOS), respectively, and are connected to N-channel switches MO.
It is connected to the ground line VSS via an SFET (Sw-MOS), and turns off each switch MOSFET by timing signals φP and φN during standby. The switch MOSFET (Sw-MOS) is not particularly limited, but has an increased effective threshold voltage similarly to the MOSFET formed in the direct peripheral circuit using a triple well structure.

In this configuration, in the circuit of FIG.
The current supply path is cut off by the off state of the switch MOSFET whose effective threshold voltage has been increased by the heavy well structure. Thereby, the sub power supply line VD to which the source of the P-channel MOSFET turned off is connected.
The potential of T falls from the power supply voltage due to the sub-threshold leakage current of the P-channel MOSFET.
That is, as shown in the element structure cross-sectional view shown in FIG.
A potential lower than the power supply voltage VDD applied to the N-type well region NWELL where the P-channel MOSFET is formed is applied to the source, and the effective threshold voltage is increased by the body effect to reduce the sub-threshold leakage current. This causes the potential of the sub power supply line VDT to settle to a constant potential.

Also in the above circuit, the switch M whose effective threshold voltage is increased by the triple well structure is provided.
The current supply path is cut off by the off state of the OSFET.
Thereby, the N-channel type MOSF which is turned off
The potential of the sub power supply line VST to which the source of ET is connected is
The sub-threshold leakage current of the N-channel MOSFET rises from the ground potential. That is, FIG.
As shown in the sectional view of the element structure shown in FIG. 2, a P-type well region NWE in which the N-channel MOSFET is formed
The potential higher than the ground potential VSS applied to the LL is applied to the source, and the effective threshold voltage is increased by the body effect to reduce the sub-threshold leakage current. Calm down.

As a result, in the indirect peripheral circuits other than the memory array section, such as the address buffer, the decoder and the timing generation circuit, the operation can be speeded up by lowering the threshold voltage in the operating state.
In the standby state, the occurrence of a sub-threshold leakage current can be prevented by the input signal and the connection to the corresponding sub-power supply line as described above, so that the current consumption in the standby state can be greatly reduced.

In FIGS. 11 and 12, the switch MOSFET (Sw-MOS) is a DWE shown by a dotted line.
LL formed in the P-type well region PWELL and the N-type well region NWELL.
A negative voltage VBB is applied to WELL, and VPP is applied to the N-type well region NWELL. The indirect direct peripheral circuit may have a triple well structure to reduce the sub-threshold leakage current.

FIG. 13 is a schematic block diagram showing another embodiment of the dynamic RAM according to the present invention. This embodiment is directed to a large storage capacity such as 256 Mbits. That is, one memory array (Array) has a storage capacity such as 16 Mbits,
Four such sets sandwiching the main word driver (Main Word) and the Y driver (Ydec) constitute one set, and are composed of four sets as a whole. One memory array is 16M
4 × 4 × 16 = 256M since it has a bit storage capacity
It has a large storage capacity like a bit. The one memory array (Array) has the same configuration as the one array in FIG. However, since the sub-array is composed of 512 pairs of complementary bit lines, a storage capacity such as 16 Mbits can be obtained by the same sub-array configuration.

The functions and effects obtained from the above embodiment are as follows. That is, (1) a dynamic type memory cell, an amplification MOSFET of a sense amplifier for amplifying a minute voltage according to the information charge of the storage capacitor read from the dynamic type memory cell to the bit line, and a precharge voltage to the bit line. A memory array including a precharge MOSFET to be applied and a column switch MOSFET for selecting a bit line;
ET is formed in a deep N-type well region and formed in a P-type well region to which a negative substrate back bias voltage is applied.
The effective threshold voltage can be increased by forming T in the N-type well region formed in the N-type well region having the deep depth and receiving the boosted voltage corresponding to the word line selection level. Threshold leakage current can be reduced, and the P-type well region in which these direct peripheral circuits are formed does not need to be particularly separated, so that high integration can be achieved.

(2) A pair of complementary bit lines are arranged in parallel as the bit lines, and the amplifying MOS of the sense amplifier is used.
The FET uses a shared method in which a read signal of a memory cell connected to one bit line is amplified using the precharge voltage of the other bit line as a reference voltage, and the precharge MOSFET and the column switch MOSFET are connected via a shared switch MOSFET. By providing the common switch MOSFETs in common for the two sets of complementary bit lines and including these shared switch MOSFETs in the memory array to form the triple well structure, an effect of enabling high integration can be obtained.

(3) The amplifying MOSFETs constituting the sense amplifier operate a plurality of CMOS latch circuits in which the inputs and outputs of two CMOS inverter circuits composed of a P-channel MOSFET and an N-channel MOSFET are cross-connected. By including a power switch circuit composed of a P-channel MOSFET and an N-channel MOSFET that respectively provide a voltage and a ground potential of the circuit in the memory array, all circuits of the memory array can be configured in the entire DWELL, so that high integration is achieved. This has the effect of achieving realization.

(4) The word line is composed of a main word line and a plurality of sub-word lines commonly assigned to the main word line, and an address of the dynamic memory cell is assigned to the sub-word line. The gate of the selection MOSFET is connected, and the sub-word line is
The sub-word driver receiving the signal of the main word line and the signal of the sub-word selection line causes one of the plurality of signals to be output.
One of them is selected, and by including such a sub-word driver in the memory array, it is possible to obtain an effect that high integration, high-speed operation, and high integration can be achieved while suppressing a sub-threshold leakage current.

(5) The memory array is divided into a plurality of sub-arrays by a sub-word driver and a main amplifier, and the sense amplifiers are divided and arranged at both ends of a plurality of complementary bit line arrays of the sub-arrays. A sub-word driver is distributed and arranged at both ends of a plurality of sub-word line columns of the sub-array, and a sub-common input / output line is provided corresponding to the sub-array, and a common input / output line provided corresponding to the plurality of sub-arrays. A switch circuit for connecting an output line is provided at a cross area where the sense amplifier and the sub-word driver intersect at four corners of the sub-array, and connects a common input / output line provided for a plurality of sub-arrays. By including the switch circuit and the cross area in the memory array, a large storage capacity can be obtained. The effect that high integration can be achieved while achieving quantification is obtained.

(6) In the CMOS indirect peripheral circuit provided in the peripheral portion of the memory array, a first circuit in which an input signal is set to a high level when the dynamic RAM is not operating, Is set to a low level, and the first circuit is provided between a first sub power supply line to which a power supply voltage is supplied via a P-channel switch MOSFET and a ground line of the circuit. The second circuit is provided between a power supply voltage and a second sub power supply line to which a ground potential of the circuit is supplied via an N-channel switch MOSFET, and the P-channel type and N-channel type switches The MOSFET is turned on when the dynamic RAM is in the operating state, and is turned off when the dynamic RAM is in the non-operating state, thereby maintaining high speed in the operating state. One advantage is that the sub-threshold leakage current in the indirect peripheral circuit in the non-operating state can be reduced.

Although the invention made by the present inventors has been specifically described based on the embodiments, the invention of the present application is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the configuration of the sub-array or the arrangement of a plurality of memory arrays mounted on a semiconductor chip can employ various embodiments according to the storage capacity and the like. In addition, the configuration of the sub-word driver can employ various embodiments. The portion of the input / output interface is a synchronous dynamic type R which operates in synchronization with a clock signal.
It may be AM, or may conform to the Rambus specification. As for the number of sub-word lines assigned to one main word line, various embodiments such as eight as well as four as described above can be adopted. The present invention can be widely used for a dynamic RAM.

[0083]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, an amplification MOSFET of a sense amplifier for amplifying a minute voltage according to the information charge of the storage capacitor read from the dynamic memory cell to the bit line from the dynamic memory cell, and a precharge for applying a precharge voltage to the bit line MOSF
ET, column switch MOSFET to select bit line
Wherein the N-channel MOSFET of the memory array is formed in a deep N-type well region and formed in a P-type well region to which a negative substrate back bias voltage is applied. By forming the P-channel MOSFET of the array in the N-type well region having the deep depth and forming the N-type well region to which a boosted voltage corresponding to the selected level of the word line is applied.
The effective threshold voltage can be increased, the subthreshold leakage current can be reduced, and the P-type well region in which these direct peripheral circuits are formed does not need to be particularly separated, so that high integration can be achieved.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing one embodiment of a dynamic RAM according to the present invention.

FIG. 2 is a schematic layout diagram for explaining a dynamic RAM according to the present invention.

FIG. 3 is a schematic layout diagram showing one embodiment of a sub-array and its peripheral circuits in a dynamic RAM according to the present invention.

FIG. 4 is a configuration diagram showing one embodiment of a dynamic RAM according to the present invention.

FIG. 5 is a schematic sectional view showing one embodiment of a dynamic RAM according to the present invention.

FIG. 6 is a main block diagram for explaining a relationship between a main word line and a sub word line of the sub array shown in FIG. 3;

FIG. 7 is a main block diagram for explaining a relationship between a main word line and a sense amplifier of the sub-array in FIG. 3;

FIG. 8 is a schematic block diagram showing one embodiment of an indirect peripheral circuit portion of the dynamic RAM according to the present invention.

FIG. 9 is a sectional view of an element structure of a memory cell portion for explaining a dynamic RAM according to the present invention.

FIG. 10 is a schematic circuit diagram showing one embodiment of an indirect peripheral circuit used in a dynamic RAM according to the present invention.

FIG. 11 is a sectional view of an element structure for explaining the circuit of FIG. 10;

FIG. 12 is a sectional view of an element structure for explaining the circuit of FIG. 10;

FIG. 13 is a schematic block diagram showing another embodiment of the dynamic RAM according to the present invention.

FIG. 14 is a schematic sectional view illustrating a conventional triple well structure.

[Explanation of symbols]

10: memory chip, 11: main row decoder area,
12: Main word driver area, 13: Column decoder area, 14: Peripheral circuit, bonding pad area, 1
5: Meseli cell array (sub array), 16: sense amplifier area, 17: sub word driver area, 18: cross area (cross area) SA: sense amplifier, SWD: sub word driver, M
WD: Main word driver, CTRL: Memory array control circuit, MWL0 to MWLn: Main word line, S
WL, SWL0 ... sub-word line, YS ... column select line,
SBARY: sub-array, TG: timing control circuit,
I / O: input / output circuit, RAB: row address buffer,
CAB: column address buffer, AMX: multiplexer, RFC: refresh address counter circuit, X
PD, YPD: Pretecoder circuit, X-DEC: Row system redundant circuit, XIB: Decoder circuit, DWELL: N-type well region of deep depth, PWELL: P-type well region, N
WELL: N-type well region, M1 to M3: metal layer, S
N: storage node; PL: plate electrode; BL: bit line; SD: source / drain; FG: first polysilicon layer.

Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 21/8238 H01L 27/10 681A 27/092 681B (72) Inventor: Shinichi Miyatake 5-2-1, Josuihoncho, Kodaira-shi, Tokyo (72) Inventor Kazuhiko Kajiya 2326 Imai, Ome-shi, Tokyo In-house Device Development Center, Hitachi, Ltd.

Claims (6)

[Claims] 1. An address selection MOSFET having a gate connected to a word line, one source and drain connected to a bit line crossing the word line, and the other source and drain connected to a storage node of a storage capacitor. A dynamic memory cell, and an amplification M of a sense amplifier for amplifying a minute voltage according to the information charge of the storage capacitor read to the bit line.
An OSFET, a precharge MOSFET for applying a precharge voltage to the bit line, and a memory array including a column switch MOSFET for selecting the bit line, wherein the N-channel MOSFET of the memory array has a deep depth. Formed in the n-type well region, formed in the p-type well region to which the negative substrate back bias voltage is applied, the p-channel MOSFET of the memory array is formed in the deep n-type well region, A dynamic RAM formed in an N-type well region to which a boosted voltage corresponding to a word line selection level is applied. 2. The bit line includes a pair of complementary bit lines arranged in parallel, and the amplification MOSFET of the sense amplifier transmits a read signal of a memory cell connected to one bit line to the other bit line. The precharge voltage is amplified as a reference voltage, and the shared switch M
The precharge MOSFET and the column switch MO are provided in common to two sets of complementary bit lines via an OSFET.
2. The dynamic RAM according to claim 1, wherein the SFET is provided in common to the two sets of complementary bit lines via the shared switch MOSFET, and the shared switch MOSFET is also included in the memory array. . 3. An amplifying MOS constituting said sense amplifier.
The FET comprises a CMOS latch circuit in which an input and an output of two CMOS inverter circuits comprising a P-channel MOSFET and an N-channel MOSFET are cross-connected, and a sense amplifier comprises an operating voltage applied to a plurality of the CMOS latch circuits. 3. A dynamic RAM according to claim 1, wherein said dynamic RAM comprises a power switch circuit comprising a P-channel MOSFET and an N-channel MOSFET for respectively providing a ground potential of said circuit and said circuit. 4. The word line comprises a main word line and a plurality of sub-word lines commonly assigned to the main word line, and an address selection MOSFET of the dynamic memory cell is provided for the sub-word line. And the sub-word line is selected from the plurality of sub-word lines by a sub-word driver receiving a signal of the main word line and a signal of a sub-word selection line. 4. The dynamic RAM according to claim 1, wherein the dynamic RAM is included in the RAM. 5. A dynamic type comprising a plurality of word lines having a length divided in an extending direction of a main word line, and a plurality of word lines being arranged in a bit line direction intersecting with the main word line. A sub-word line connected to the gate of an address selection MOSFET of a memory cell, extended in parallel with the main word line,
A first sub-word selection line to which a selection signal for selecting one of a plurality of sub-word lines assigned to one main word line is transmitted; and a first sub-word selection line corresponding to the first sub-word selection line, A second sub-word select line extending orthogonal to the word line; a main word line select signal and a select signal transmitted through the second sub-word select line; A plurality of sub-word drivers, a plurality of sub-word lines, a plurality of sub-word lines, a plurality of sub-arrays including a plurality of complementary bit line pairs, and a plurality of dynamic memory cells provided at intersections thereof. The sub-word drivers are distributed and arranged at both ends of the sub-word line array composed of a plurality of Sense amplifiers are divided and arranged at both ends of a plurality of complementary bit line arrays of the sub-arrays, and the one sub-array is surrounded by the plurality of sub-word driver rows and the plurality of sense amplifier rows. A sub-common input / output line is provided corresponding to the sub-array, and a switch circuit for connecting to a common input / output line provided for the plurality of sub-arrays is provided at four corners of the sub-array, The memory array also includes a cross circuit provided in a cross area where an amplifier and a sub word driver intersect, the switch circuit connecting the plurality of sub arrays, a common input / output line provided corresponding to the plurality of sub arrays, and the cross area. 5. The dynamic RA according to claim 4, wherein
M. 6. The semiconductor device according to claim 6, wherein a peripheral portion of said memory array is a CMOS.
A peripheral circuit having a configuration is provided. The peripheral circuit includes a first circuit in which an input signal is set to a high level when the dynamic RAM is in an inactive state, and a second circuit in which the input signal is set to a low level. The first circuit is a P-channel switch MOSFE
The second circuit is provided between a first sub power supply line to which a power supply voltage is supplied via T and a ground line of the circuit, and the second circuit has a power supply voltage and a ground potential of the circuit via an N-channel switch MOSFET. Second supplied
P-channel type and N-channel type switch MOS
3. The FET according to claim 1, wherein the FET is turned on when the dynamic RAM is in the operating state, and is turned off when the dynamic RAM is not in the operating state.
A dynamic RA according to claim 3, claim 4, or claim 5.
M.