JP4949451B2 - Dynamic RAM and semiconductor device - Google Patents

Description

  The present invention relates to a dynamic RAM (random access memory), a semiconductor device, and a semiconductor device, and is effective when used in a so-called one-intersection system in which dynamic memory cells are arranged at the intersections of word lines and bit lines. Technology.

  As an open bit line type (one-intersection type) dynamic RAM which is considered to be related to the present invention, which will be described later, based on research after the present invention has been made, Japanese Patent Application Laid-Open No. 63-206991 (hereinafter referred to as Prior Art 1). JP-A-64-13290 (hereinafter referred to as Prior Art 2), JP-T-11-501441 (hereinafter referred to as Prior Art 3), JP-A-5-41081 (hereinafter referred to as Prior Art 4). It was found that there was. In the prior arts 1 and 2, the sense amplifiers are alternately arranged in the open bit line type (one-intersection method) so that one sense amplifier is fitted into the pitch of two bit lines. In the prior arts 3 and 4, as in the prior arts 1 and 2, the reference voltage required for the operation of the sense amplifier provided at the end when the sense amplifiers are alternately arranged for efficient use of the chip area is a bit. A circuit that realizes an electrical model substantially identical to the line is provided.

JP 63-206991 A JP-A 64-13290 Japanese National Patent Publication No. 11-501441 JP-A-5-41081

  In the prior arts 3 and 4, stable operation cannot be expected due to the difference in operating conditions between the sense amplifier at the end and the sense amplifier provided with bit lines on both sides due to process variations which increase with the miniaturization of elements. . In the prior arts 1 and 2, no consideration is given to the configuration of the ends when the sense amplifiers are alternately arranged with respect to the bit lines.

  Cost reduction is desired for dynamic RAM (hereinafter simply referred to as DRAM). For this purpose, reduction of the chip size is the most effective. Until now, the memory cell size has been reduced by further miniaturization. However, it is necessary to further reduce the cell size by changing the operation method of the memory array in the future. By changing the operation method of the memory array from two intersections to one intersection, the cell size can be ideally reduced by 75% using the same design rule. In order to make effective use of such a reduction in cell size, in the present inventor, in the above-described one-intersection type memory array, when the sense amplifiers are arranged alternately, they are provided at the end portions. We considered effective use of the memory cell array and reduction of its exclusive area.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a one-intersection dynamic RAM and a semiconductor device in which an operation margin is improved and a chip area per bit is reduced. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. A plurality of memory mats including a plurality of bit lines, a plurality of word lines, a plurality of bit lines and a plurality of memory cells coupled to the plurality of word lines are arranged in the bit line direction, and the bit lines Provided in a region between the memory mats arranged in the direction, and provided with a sense amplifier array including a plurality of latch circuits in which input / output nodes are connected to half bit lines provided in the memory mat. As for the normal memory mat excluding both ends in the bit line direction, the word line of any one of the memory mats is activated, and the end memory mats provided at both ends in the bit line direction are both memory mats. Are activated simultaneously.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. A plurality of memory mats including a plurality of bit lines, a plurality of word lines, a plurality of bit lines and a plurality of memory cells coupled to the plurality of word lines are arranged in the bit line direction, and the bit lines A sense amplifier array including a plurality of latch circuits provided in a region between memory mats arranged in a direction and having input / output nodes connected to half of the bit lines provided in the memory mat; For a normal memory mat excluding both ends in the bit line direction, the word line of any one of the memory mats is activated, and for the end memory mat provided at both ends in the bit line direction, the words of both memory mats are activated. By activating the lines at the same time, the operating margin of the sense amplifier is ensured while the effective use of the end mats occupies per bit. It is possible to reduce the product.

1 is a schematic layout diagram showing an embodiment of a DRAM to which the present invention is applied. 1 is a configuration diagram showing an embodiment for explaining a memory mat of a DRAM according to the present invention; FIG. It is explanatory drawing which shows one Example of the memory cell array in DRAM which concerns on this invention. It is explanatory drawing which shows one Example of the word type control operation of DRAM which concerns on this invention. 1 is a circuit diagram showing one embodiment of a DRAM main word driver MWD according to the present invention; FIG. It is explanatory drawing which shows another Example of the word type control operation | movement of DRAM which concerns on this invention. 1 is a circuit diagram showing an embodiment of a sense amplifier section of a dynamic RAM according to the present invention. FIG. 1 is a circuit diagram showing one embodiment of a row selection circuit of a DRAM according to the present invention; FIG. FIG. 9 is a waveform diagram for explaining the operation of the row selection circuit of FIG. 8; 1 is a block diagram showing an embodiment of an IO system circuit of a DRAM according to the present invention. FIG. 1 is a circuit diagram showing one embodiment of an IO system circuit of a DRAM according to the present invention; FIG. It is a block diagram showing another embodiment of the IO system circuit of the DRAM according to the present invention. 1 is a schematic configuration diagram showing one embodiment of a bit line configuration of an end mat in a DRAM according to the present invention. FIG. FIG. 14 is a waveform diagram for explaining a read selection operation of the folded end mat of FIG. 13. 1 is a circuit diagram showing one embodiment of a sense amplifier control circuit in a DRAM according to the present invention. FIG. 1 is a schematic layout diagram showing an embodiment of a folded end mat in a DRAM according to the present invention; FIG. It is sectional drawing which shows one Example of the folding | turning type | mold end mat of FIG. It is a schematic block diagram showing another embodiment of the bit line configuration of the end mat in the DRAM according to the present invention. It is a schematic block diagram showing another embodiment of the bit line configuration of the end mat in the DRAM according to the present invention. 1 is a schematic layout diagram showing an embodiment of a DRAM to which the present invention is applied. FIG. 21 is an enlarged view of an end mat in the memory bank BANK1 shown in FIG. 20 and a normal mat adjacent thereto. It is a circuit diagram which shows one Example of the FX driver and subword driver based on this invention. FIG. 3 is a layout diagram showing one embodiment of an FX driver and a sub word driver according to the present invention. It is a schematic layout diagram showing another embodiment of the dynamic RAM according to the present invention. 1 is an overall block diagram showing an embodiment of a dynamic RAM according to the present invention.

  FIG. 1 is a schematic layout diagram of an embodiment of a DRAM to which the present invention is applied. In the figure, the main part of each of the circuit blocks constituting the dynamic RAM to which the present invention is applied is shown so that it can be seen from a single crystal silicon by a known semiconductor integrated circuit manufacturing technique. Are formed on one semiconductor substrate.

  In this embodiment, although not particularly limited, the memory array is divided into four as a whole. The central portion 14 is provided with an input / output interface circuit including an address input circuit, a data input / output circuit, and a bonding pad row, a power supply circuit including a booster circuit and a step-down circuit, and the like. . A memory array control circuit (AC) 11 and a main word driver (MWD) 12 are arranged at portions of the central portion 14 in contact with the memory arrays on both sides. The memory array control circuit 11 includes a control circuit and a main amplifier for driving a sub word selection line and a sense amplifier. As described above, in each of the four memory arrays divided into two on the left and right with respect to the longitudinal direction of the semiconductor chip and two on the upper and lower sides, the column decoder area (YDC) is located at the upper and lower central portions with respect to the longitudinal direction. 13 is provided.

  As described above, in each memory array, the main word driver 12 forms a selection signal for a main word line that extends so as to penetrate one memory array corresponding thereto. The main word driver area 12 is also provided with a sub word selection line driver for selecting a sub word, and is extended in parallel with the main word line to form a selection signal for the sub word selection line, as will be described later. The column decoder 13 forms a selection signal for a column selection line that extends so as to penetrate one memory array corresponding to the column decoder 13.

  Each memory array is divided into a plurality of memory cell arrays (hereinafter referred to as memory mats) 15. As shown in the enlarged view, the memory mat 15 is formed surrounded by a sense amplifier region 16 and a sub word driver region 17. An intersection of the sense amplifier region 16 and the sub word driver region 17 is an intersection region (cross area) 18. The sense amplifier provided in the sense amplifier region 16 is constituted by a latch circuit having a CMOS structure, and a so-called one-intersection system or open bit that amplifies a complementary bit line signal extending left and right around the sense amplifier. Line type. Then, they are arranged alternately with respect to the bit line arrangement. As a result, the bit lines provided in the memory mat are divided in half and are alternately distributed to two sense amplifier rows sandwiching the bit lines.

  One memory mat 15 shown as an enlarged view is not particularly limited, but has 512 sub-word lines (word lines) and 1024 complementary bit lines (or data lines) orthogonal thereto. In the one memory array, 32 memory mats 15 are provided in the bit line extending direction and 32 in the bit line direction and 2 for the redundancy. As described later, the number of memory cells in the end memory mat is halved, so that the two end memory mats are used as one memory mat. The end memory mat may be used for reference. In this case, one memory mat is allocated for redundancy.

  Since the memory mat 15 is provided with a pair of complementary bit lines with the sense amplifier 16 as the center, the bit line is substantially divided into 16 by the memory mat 15 when viewed in the extending direction of the bit lines. Four memory mats 15 are provided in the extending direction of the word lines. As a result, when viewed in the extending direction of the word line, the sub word line is divided into four by the memory mat 15.

  Since one memory mat 15 has 1024 bit lines except for the end memory mat, about 4K memory cells are connected in the word line direction and 512 sub word lines are provided. Is connected to 512 × 32 = 16K memory cells. Thus, one memory array has a storage capacity of 4K × 16K = 64 Mbits, and the memory chip 10 as a whole has a storage capacity of 4 × 64 M = 256 Mbits by the four memory arrays. Is done.

  In the present application, the term “MOS” is understood to have originally come to be referred to simply as a metal oxide semiconductor configuration. However, the MOS in the general name in recent years includes those in which the metal in the essential part of the semiconductor device is replaced with a non-metal electrical conductor such as polysilicon, or the oxide is replaced with another insulator. Yes. CMOS has also been understood to have broad technical implications in response to changes in how it pertains to MOS as described above. MOSFETs are not understood in a narrow sense as well, but have become meanings including configurations in a broad sense that can be substantially regarded as insulated gate field effect transistors. The CMOS, MOSFET, and the like of the present invention follow the general names as described above.

  FIG. 2 is a block diagram showing an embodiment for explaining a memory mat of a DRAM according to the present invention. FIG. 2A shows a circuit corresponding to two memory mats MAT0 and MAT1 provided in the hierarchical word line DRAM as shown in FIG. 1, and FIG. 2B shows a layout corresponding to the two memory mats. Has been. In FIG. 2A, a memory cell MC composed of a MOSFET and a cell capacitor CS is connected to all intersections of a bit line BL and a sub word line WL. The bit line BL is connected to a sense amplifier SA, and the word line WL is connected to a sub word driver SWD.

  In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. However, as will be described later, for one main word line, Four sub word lines are arranged in the complementary bit line direction. As shown in FIG. 1, in order to select one sub word line from among the sub word lines that are divided into two in the main word line direction and each of the four is assigned to the complementary bit line direction, A subword selection driver is arranged. This subword selection driver forms a selection signal for selecting one of the four subword selection lines extended in the subword driver arrangement direction (subword driver array SWDA). Although not shown, the main word line MWL extends in parallel with the sub word line WL. Although not shown, the column selection line YS is arranged in parallel with the extending direction of the bit BL so as to be orthogonal thereto.

  The sense amplifier SA of the sense amplifier array SAA provided between the two memory mats MAT0 and MAT1 is connected to a complementary bit line extending on both sides of the two memory mats MAT0 and MAT1. These sense amplifiers SA are not particularly limited in the sense amplifier array SAA, but one sense amplifier SA is arranged for every two bit lines. Therefore, in the sense amplifier array SAA provided between the memory mats MAT0 and MAT1, when there are 1024 bit lines BL as described above, 512 sense amplifiers SA which are half of the bit lines BL are provided.

  In the memory mat MAT0, the remaining 512 bit lines are connected to a sense amplifier SA provided in the sense amplifier array SAA on the opposite side to the memory mat MAT1. In the memory mat MAT1, the remaining 512 bit lines are connected to a sense amplifier SA provided in a sense amplifier array SAA provided on the opposite side to the memory mat MAT0. With such a distributed arrangement on both sides of the sense amplifier SA in the bit line direction, one sense amplifier may be alternately distributed at both ends of the two bit lines. The memory mat and the sense amplifier array can be formed with high density by matching the pitch of the lines BL.

  The same applies to the sub word driver SWD. The 512 sub word lines WL provided in the memory mat MAT0 are divided into 256 pieces and connected to 256 sub word drivers SWD of the sub word driver row SWDA arranged on both sides of the memory mat MAT0. In this embodiment, two sub word drivers SWD are distributedly arranged with two sub word lines WL as one set. That is, the sub word line corresponding to two memory cells having a common connection with the bit line is set as one set, and two sub word drivers are arranged on one end side (upper side in the drawing) of the memory mat MAT0 and adjacent to the above. Two sub word trivers are arranged on the other end side (the lower side of the figure) of the memory mat MAT0, with the same two sub word lines as one set.

  Although not shown, the sub word driver SWD forms a selection signal for sub word lines of memory mats provided on both sides of the sub word driver array SWDA in which the sub word driver SWD is formed. As a result, the sub word drivers SWD can be efficiently distributed and arranged corresponding to the sub word lines formed in accordance with the arrangement pitch of the memory cells, and the sub word line WL can be selected at high speed.

  A memory cell MC is formed at each intersection of the bit line BL and the sub word line WL of the memory cell array (or memory mat) MAT0, MAT1, etc. surrounded by the sub word driver array SWDA and the sense amplifier array SAA as described above. In the memory mat MAT0 in which each memory cell MC is formed, as shown in FIG. 2B, the upper electrode (plate electrode) PL of the storage capacitor CS is common to all the memory cells MC in the memory mats MAT0 and MAT1. It is formed into a planar electrode. The power supply to the plate electrode PL is performed at the boundary between the sub word driver array SWDA and the memory mats MAT0 and MAT1 through the connection portion PLCT from the power supply wiring VPLT wired in the extending direction of the bit line BL. In the figure, the storage node SN is a lower electrode of the storage capacitor CS and indicates a connection portion with the address selection MOSFET.

  In this embodiment, as shown in FIG. 2B, the plate electrodes PL0 and PL1 formed on the memory mats MAT0 and MAT1 existing on both sides of the sense amplifier array SAA are used as the plate layers themselves. They are connected to each other by wiring PLSA. In addition, a large number of wiring lines PLSA are provided so as to penetrate the sense amplifier example SAA so as to greatly reduce the resistance between the two plate electrodes PL0 and PL1. Accordingly, the minute signals read from the memory cells MC selected between the complementary bit lines BL of the memory mats MAT0 and MAT1 are reversed in phase from each other generated in the plate electrodes PL0 and PL1 when amplified by the sense amplifier SA. Noise can be canceled at high speed, and noise generated in the plate electrodes PL0 and PL1 can be greatly reduced.

  FIG. 3 is an explanatory diagram showing one embodiment of the memory cell array in the DRAM according to the present invention. FIG. 3A shows the layout of the memory cell arrays of two memory mats MAT0 and MAT1, and FIG. 3B shows the element cross-sectional structure of the AA ′ portion of FIG. 3A. ing. In the drawing, the layout and cross section of the sense amplifier SA region provided between MAT0 and MAT1 are omitted.

  ACT is an active region of the MOSFET, and SNCT is a contact (connection part) that connects the storage node SN of the memory cell and the source and drain diffusion layers corresponding to the storage node SN of the MOSFET formed in the activation region ACT. BLCT is a contact (connection portion) for connecting the bit line BL and the source / drain diffusion layer corresponding to the input / output terminal of the memory cell corresponding to the bit line BL of the MOSFET formed in the activation region ACT. CP indicates a capacitance insulating film of the storage capacitor. Here, the first metal layer M1 and the bit line BL are the same wiring layer, and the first polysilicon layer FG and the sub word line WL are also configured with the same wiring layer.

  As shown in FIG. 3B, the memory mats MAT0 and MAT1 provided on both sides of the SA are connected by the electrodes themselves constituting the plate electrode PL without cutting the plate electrodes PL of the MAT1 on the sense amplifier SA. The resistance between the plate electrode PL of the mat MAT0 and the plate electrode PL of the memory mat MAT1 can be greatly reduced. The memory cell uses a COB (Capacitor over Bitline) structure. That is, the storage node SN is provided above the bit line BL. As a result, the plate electrode PL can be formed in a single plane without being divided by the connection part BLCT of the bit line BL and the address selection MOSFET in the memory mat MAT. Can be reduced.

  In this embodiment, as shown in FIG. 3B, the plate electrode PL has a laminated structure such as PL (D) and PL (U), which can advantageously reduce the sheet resistance value of the plate electrode PL. It is. As an example, when a high dielectric film such as BST or Ta 2 O 5 is used for the capacitor insulating film CP of the storage capacitor, if Ru is used for the lower electrode (storage node) SN and the upper electrode lower layer PL (D), the storage capacitor The capacity of CS can be increased. Since Ru has a lower sheet resistance value than that of conventionally used poly-Si, the resistance value of the plate electrode PL can be lowered.

  When W is stacked as the plate electrode PL (U) having the above structure, the resistance value of the plate electrode PL can be further reduced. When the resistance value of the plate electrode PL itself is lowered in this way, the speed at which the noise on the plate electrode PL is canceled is increased, and the plate electrode PL noise is reduced. Further, TiN may be used as the plate electrode PL (D). In this case, the same effect as described above can be obtained.

  In the structure of the memory cell as described above, as is apparent from FIG. 3A, the connection portion SNCT that connects the storage node SN and the source and drain diffusion layers of the MOSFET is provided adjacent to the bit line BL. That is, since a parasitic capacitance exists between the storage node of the memory cell and the bit line BL in the longitudinal direction of the cross section, a signal path is formed to transmit the potential change of the bit line BL to the storage node. It would be beneficial to connect the plate electrodes PL to each other by wiring using itself.

  FIG. 4 is an explanatory diagram showing one embodiment of the word-related control operation of the DRAM according to the present invention. In the memory mat configuration, four memory mats arranged in the bit line direction are exemplarily shown as representatives, and both sides in the bit line direction are end memory mats (hereinafter simply referred to as end mats), and the sense amplifier SA. The memory mat sandwiched between the two is a normal memory mat (hereinafter simply referred to as a normal mat). Since the sense amplifiers SA are connected to every other bit line of the memory mat, half of the bit lines are dummy in the end mat. For this reason, when the word line of the end mat is selected, the number of memory cells selected is only half the number of memory cells when the word line of the normal mat is selected.

  The word lines are selected by sub word drivers SWD distributed and arranged above and below the memory mat. The sub word driver SWD receives the main word line selection signal formed by the main word driver MWD provided in common to the memory mat (not shown) arranged in the word line extension direction, and the sub word line selection signal. One sub word line (hereinafter sometimes simply referred to as a word line) is selected from the four sub word lines assigned to one main word line.

  In this embodiment, when the sense amplifiers are distributed on both sides of the bit line of the memory mat and a plurality of such memory mats are provided in the bit line direction, a pair of end mats is always provided at both ends. However, considering the fact that the end mat that can irregularly select only half of the memory cells as described above is effectively used as a data storage area similar to the normal mat, when selecting the word line of the end mat, the end mats on both sides are selected. Select the matte word lines at the same time.

  As exemplarily shown in (a) and (b), when there are four bit lines in each of the normal mats 0 and 1, there are two pieces provided in the sense amplifier block (SA Block) 0. The sense amplifier SA is connected to the two bit lines BLB of the end mat and the two bit lines BLT of the normal mat 0. The two sense amplifiers SA provided in the sense amplifier block 1 are connected to the two bit lines BLB of the normal mat 0 and the two bit lines BLT of the normal mat 1. The two sense amplifiers SA provided in the sense amplifier block 2 are connected to the two bit lines BLB of the normal mat 1 and the two bit lines BLT of the end mat. In the end mat, the bit line not connected to the sense amplifier is a dummy.

  For example, when a word line of normal mat 0 is selected, the word line can select four memory cells crossing four bit lines, and two sense amplifier blocks 0 provided with normal mat 0 sandwiched therebetween. Rewrite (refresh) that the storage information of the four memory cells is amplified by the sense amplifiers 1 and 1 and the storage charge lost in the storage capacitor is returned to the original charge state by the selection operation of the word line. Operation) is performed. That is, in the dynamic memory cell, the address selection MOSFET is turned on by the word line selection operation, the storage capacitor is connected to the bit line, charge sharing is generated between the bit line and the parasitic capacitance, and the bit line is stored. A destructive read operation that causes a minute voltage change corresponding to the charge is performed. Therefore, when a word line is selected, the memory cell selected by the amplification operation of the sense amplifier connected to the bit line intersecting with the word line is selected. Is required to be rewritten.

  On the other hand, when an end mat word line is selected, the end mat word line intersects two bit lines and two dummy lines, and only two memory cells can be selected. . Therefore, when the word line of the end mat is also selected and data is written or read, only half of the data can be input / output, and the usability as a memory is deteriorated. Therefore, as shown in (b), when selecting an end mat word line, the end mat word lines on both sides are always selected. In this way, the number of memory cells selected by one word line selection can be four as in the normal mat. As described above, with respect to the end mat, it is possible to perform the same data writing and reading by the same bit line selection operation as that of the normal mat with a simple configuration in which two word lines are always selected simultaneously.

  In the above configuration, since the end mat can also be effectively used as a part of the storage area, for example, in a miniaturized memory cell, in order to ensure a read margin of the sense amplifier, the bit line of the end mat As compared with the case where the signal is used only for forming a reference voltage for reading the sense amplifier, the chip-occupied area per bit can be reduced while securing the read margin of the sense amplifier.

  FIG. 5 is a circuit diagram showing one embodiment of the main word driver MWD of the DRAM according to the present invention. FIG. 4A shows a main word driver of a normal mat, and FIG. 4B shows a main word driver corresponding to two end mats.

  In (a), the signal RMST <15: 0> is a mat selection signal when 32 memory mats are divided into 16 sets each including two memory mats as shown in FIG. 1, and the signals RF3T and RF6T Is a predecode signal. In the normal mat, the precharge MOSFET Q3 of the selected mat is turned off by the precharge signal RMSXDPT <15: 0>, and one memory mat column (four in the example of FIG. 1) is set by the low level of the signal RMST <15: 0>. In the memory mat), the precharge voltage at the input terminal of the inverter circuit IV1 is discharged through the MOSFETs Q1 and Q2 turned on by the predecode signals RF3T and RF6T. Due to the low level of the input terminal, the selection signal RMWLB for the main word line is set to the low level of the selection level.

  A non-selected word line in the selected mat is turned on when a P-channel feedback MOSFET Q4 provided between the input terminal and the operation power supply terminal is turned on by a low level corresponding to the precharge voltage of the input signal of the inverter circuit IV1. Thus, the precharge voltage corresponding to the non-selection level is maintained. In the non-selected memory mat, the precharge signal RMSXDPT <15: 0> remains at the low non-selection level, and the precharge operation is maintained.

  In (b), the signal RMSSET is an end mat selection signal, and the signals RF3T and RF6T are predecode signals. In the end mat, the precharge MOSFET of the end mat is turned off by the precharge signal RMSXDPET corresponding to the end mat, and the premat MOSFET is turned off in two end mat columns (four memory mats in the example of FIG. 1) by the low level of the signal RMSET. The precharge voltages at the input terminals of the respective inverter circuits are discharged through the MOSFETs turned on by the decode signals RF3T and RF6T. Due to the low level of the input terminal, the selection signal RMWLB for the main word line corresponding to the two end mats is set to the low level of the selection level.

  The non-selected word line in the end mat is a P-channel type provided between the input terminal and the operation power supply terminal by a low level corresponding to the precharge voltage of the input signal of the inverter circuit as in the case of the normal mat. The feedback MOSFET is turned on to maintain the precharge voltage corresponding to the non-selection level. When the word line of the normal mat is selected, in the end mat, the precharge signal RMSXDPET remains at the low level non-selection level, and the precharge operation is maintained.

  In the hierarchical word line system as described above, the sub word line (word line) in the lower layer is selected by the main word line selection operation. The end mat word line selection as described above can be performed by a simple circuit change as created.

  FIG. 6 shows an explanatory diagram of another embodiment of the word-related control operation of the DRAM according to the present invention. In the memory mat configuration, seven memory mats arranged in the bit line direction are exemplarily shown as representatives, and both sides in the bit line direction are ends. Of the normal mats sandwiched between the sense amplifiers SA, the one provided in the center is used as the center mat, and is treated as an end mat. This configuration is usually directed to the case where two mats are selected simultaneously. In other words, as shown in FIG. 1, the 32 memory mats are divided into two groups of 16 memory mats, and the word system selection control in the case where two memory mats are simultaneously selected is also supported.

  When the word lines of the normal mats 0 and 2 are simultaneously selected as shown in (a) to increase the number of read / write bits, the two word lines of the end mat and the word line of the central mat are combined as shown in (b). . That is, the memory cell of the bit line connected to the sense amplifier (sense amplifier block) 2 on the left side of the center mat is combined with the memory cell connected to the left end mat and the bit line, and the sense amplifier (sense) on the right side of the center mat. The memory cell of the bit line connected to the amplifier block 3 is combined with the memory cell connected to the right end mat and the bit line.

  For example, even if two sets of mat configurations shown in FIG. 4 are provided, the number of read / write bits can be increased as described above. However, the number of end mats is four, and the number of activated word lines is increased to four, and the current consumption for selecting the word line is increased. In the end mat, the number of dummy bits increases and the area occupied by each bit increases. In the configuration in which the central mat is arranged as described above and the half bit lines are combined with the bit lines of the end mats on both sides, the generation of the dummy bits can be minimized, so the occupied area is not reduced, and the bit line selection circuit Can also be shared.

  In the above, the definition of the center mat does not necessarily have to be arranged at the center of the plurality of memory mat rows. In FIG. 6, the normal mat 0 adjacent to the left end mat can also be used as the central mat. However, in this case, since the distance between the selection of the left end mat and the selection of the right end mat and the center mat (usually mat 0) selected as a pair differs greatly, writing and reading are performed. The signal transmission path is constrained to the slower one, and the actual operation speed becomes slower. Therefore, it is preferable to use a normal mat physically provided at the center of a plurality of memory mat rows as in the embodiment of FIG.

  FIG. 7 is a circuit diagram showing one embodiment of the sense amplifier portion of the dynamic RAM according to the present invention. The sense amplifier SA is composed of a CMOS latch circuit including N-channel type amplification MOSFETs Q5 and Q6 and P-channel type amplification MOSFETs Q7 and Q8 whose gates and drains are cross-connected to form a latch. The sources of N-channel MOSFETs Q5 and Q6 are connected to a common source line SDN. The sources of P-channel MOSFETs Q7 and Q8 are connected to a common source line SDP. The common source lines SDN and SDP are supplied with operating voltage, circuit ground potential VSS and operating voltage VDL through a power switch MOSFET (not shown). Although not particularly limited, the power switch MOSFETs may be provided in a distributed manner in the sense amplifier unit.

  At the input / output node of the sense amplifier SA, a precharge (consisting of an equalize MOSFET Q11 for short-circuiting the complementary bit lines BLT0 and BLB0, and switch MOSFETs Q9 and Q10 for supplying a half precharge voltage VDL / 2 to the complementary bit lines BLT0 and BLB0 ( (Equalize) circuit is provided. The gates of these MOSFETs Q9 to Q11 are commonly supplied with a precharge (bit line equalize) signal BLEQ. Although not shown, the driver circuit for generating the precharge signal BLEQ is provided with an inverter circuit in the cross area 18 shown in FIG. In other words, at the start of memory access, the MOSFETs Q9 to Q11 constituting the precharge circuit are switched at high speed through inverter circuits distributed in each cross area 18 prior to the word line selection timing. .

  A pair of input / output nodes of the sense amplifier SA is connected to the complementary bit lines BLT0 and BLB0, and is also extended locally along the sense amplifier row via a column (Y) switch circuit composed of MOSFETs Q12 and Q13. Sub) connected to input / output lines LIOT and LIOB. The gates of the MOSFETs Q12 and Q13 are connected to a column selection line YS, and are turned on when the column selection line YS is set to a selection level (high level), and the input / output nodes of the sense amplifier SA and the local input / output line LIOT. And LIOB are connected. The other complementary bit lines BLT1, BLB1, BLT2, and BLB2 shown as examples are also provided with the same sense amplifier, precharge circuit, and column switch circuit.

  As a result, the input / output node of the sense amplifier SA is the memory cell connected to the intersection with the word line of the selected memory mat among the two memory mats (for example, MAT0 and MAT1) provided across the sense amplifier SA. A minute voltage change with respect to the half precharge voltage of the bit line that changes corresponding to the stored charge is amplified using the half precharge voltage of the non-selected bit line on the memory mat side as a reference voltage, and the column select line YS Is selected and transmitted to the local input / output lines LIOT and LIOB through the column switch circuits (Q12 and Q13).

  As shown in FIG. 1, the local input / output lines LIOT and LIOB are extended on the sense amplifier array arranged in the extending direction of the main word line, and a sub-amplifier circuit is provided on the local input / output line as necessary. An amplified signal is transmitted. Then, as will be described later, it is connected to the main input / output lines MIO arranged in the bit line direction and led to the data output circuit or the data input circuit.

  FIG. 8 is a circuit diagram showing one embodiment of a DRAM row selection circuit according to the present invention. In this embodiment, there is shown a partial circuit diagram of a row-related selection circuit when one of the end mat or the normal memory mat is used as a redundant circuit. FIG. 8A shows a row selection circuit in the case of the folded bit line method and the shared sense amplifier method as a reference example, and FIG. 8B corresponds to the redundant memory mat. A circuit diagram of the precharge control signal generating circuit and the main word driver is shown.

  In the shared sense amplifier system as described above, when one of the memory mats provided on both sides of the sense amplifier is used for redundancy, there is a word line or bit line defect on the normal memory mat side. The shared switch control signal SHR and the precharge signal BLEQ corresponding to the redundant memory mat are generated by the mat selection signal RF9T after the repair determination, and the delay control is performed for the switch control of the shared switch MOSFET and the operation end of the precharge circuit. The main word line corresponding to the redundant memory mat is selected by adjusting the time with (delay).

  On the other hand, when the end mat and the center mat of the above embodiment are used as a redundant circuit, a precharge control signal is generated simultaneously with the normal circuit by the normal mat timing signal RACT corresponding to the normal circuit. The redundant mat main word line is selected by using the redundant mat mat selection signal RF9T after the repair determination. In this configuration, since the precharge operation required for bringing the main word line into the selected state has already been completed, the delay circuit (delay) as described above is inserted, and the main A word line selection operation can be performed.

  In the above configuration, if there is no defect in the normal circuit, the word line of the redundant mat is not selected, so there is no problem even if the precharge operation as described above is terminated, and the normal circuit operation is terminated. Since the precharge circuit performs the precharge operation, even if the precharge voltage of the bit line slightly decreases due to a leakage current or the like during the memory access time of the normal circuit, there is no effect on the selection operation of the redundant circuit in the next memory cycle. Do not cause problems.

  FIG. 9 is a waveform diagram for explaining the operation of the row-related selection circuit of FIG. FIG. 9 (a) corresponds to the circuit operation of FIG. 8 (a) as a reference example, and FIG. 9 (b) corresponds to the circuit operation of FIG. 8 (b) according to the present invention.

  As shown in FIG. 9 (a), in the configuration in which the redundancy mat is determined to be redundant (hit) and the shared switch selection signal SHR and the precharge signal BLEQ are set to a low level, the time required for these operations is secured. Therefore, it is necessary to provide the delay circuit as described above to delay the selection timing of the word line SWL. At this time, in the normal mat, the mat itself is not selected in accordance with the redundancy determination (hit), so that the signals SHR, BLEQ, and FXB are kept at the high level, and the sub word line SWL is also not selected.

  On the other hand, in the present invention, as shown in FIG. 9B, the redundancy mat precharge signal BLEQ and subword selection selection corresponding to the clock signal CLK without waiting for the redundancy mat to be redundant (hit). The line FXB is set to the low level, and the sub word line SWL can be immediately selected by the redundancy judgment (hit). The sub word selection line FXB will be described later. In the normal mat, the precharge signal BLEQ and the sub word selection selection line FXB are set to a low level corresponding to the clock signal CLK. Return to level.

  FIG. 10 is a block diagram showing one embodiment of an IO (input / output line) system circuit of a DRAM according to the present invention. In this embodiment, the memory mat is composed of an end mat and two normal mats as in FIG. The local input / output lines LIO <0>, LIO <1>, and LIO <2> are provided in the sense amplifier blocks (SA Blocks) 0, 1, and 2 formed between the memory mats, respectively. It is done.

  In contrast, main input / output lines MIO <0> and MIO <1> are provided in the memory mat arrangement direction, in other words, in the extension direction of the bit lines. Accordingly, when data is input / output in units of 2 bits in the memory mat configuration as described above, the local input / output line LIO <0> is made to correspond to the main input / output line MIO <0>, and the local input / output line is When LIO <1> is associated with the main input / output line MIO <1>, when the word line of the normal mat 1 is selected as shown in (a), the remaining local input / output lines LIO <2> Since the local input / output line LIO <1> is associated with the main input / output line MIO <1>, it is necessary to correspond to the main input / output line MIO <0> in order to avoid data collision.

  However, when two word lines are simultaneously selected in the end mat as described above, the local input / output line LIO <0> corresponding to the left end mat is changed to the main input / output line MIO <0> as described above. Therefore, the local input / output line LIO <2> corresponding to the rightmost mat is connected to the main input line in order to avoid data collision, contrary to the case where the word line of the normal mat 1 is selected. It is necessary to correspond to the output line MIO <1>.

  Therefore, in this embodiment, as described above, the local input / output line LIO <2> provided in the sense amplifier block 2 provided between one end mat and the normal mat is connected to the main input / output line MIO <0>. A change-over switch is provided between the MIO <1> and the signal transmission path is switched so as to correspond to the above in the normal mat access and the end mat access.

  FIG. 11 is a circuit diagram showing one embodiment of an IO (input / output line) system circuit of a DRAM according to the present invention. This figure shows a circuit diagram of the LIO-MIO switch circuit in the embodiment shown in FIG. In this embodiment, a CMOS bus gate type switch is shown, but the same applies to the case of connection by a sub-amplifier or the like.

  When the local input / output line LIO and the main input / output line MIO are selectively connected in a one-to-one correspondence as in LIO <0> in FIG. 10, when the memory mat is not selected, it corresponds to that. The precharge signal BLEQ is set to the high level, the complementary local input / output lines LIOT0 and LIOB0 are maintained at the precharge voltage VBLR by the equalize MOSFET and the precharge MOSFET, and the CMOS switch MOSFETs Q20 to Q23 are turned off.

  When the memory mat is selected, the corresponding precharge signal BLEQ is set to the low level, the equalizing MOSFETs and the precharging MOSFETs of the complementary local input / output lines LIOT0 and LIOB0 are turned off, and the CMOS switch MOSFETs Q20 to Q23 are turned on. Thus, the local input / output lines LIOT0 and LIOB0 are connected to the main input / output lines MIOT0 and MIOB0. This configuration is the same in the switch circuit between the local input / output line LIO <1> and the main input / output line MIO <1>.

  In the case of switching between the main input / output lines MIO <0> and MIO <1> according to the mat selection state as in the LIO <2> of FIG. 10, MOSFETs Q20 to Q23 and Q24 to Q27 constituting the CMOS switch circuit are respectively provided. Provided. When the normal mat is selected, the signal MSB goes low and the switch MOSFETs Q20 to Q23 are turned on to connect the complementary local input / output lines LIOT2 and LIOB2 to the main input / output lines MIOT0 and MIOB0 as described above. . When the end mat is selected, the signal MSEB goes low to turn on the switch MOSFETs Q24 to Q27, and connect the complementary local input / output lines LIOT2 and LIOB2 to the main input / output lines MIOT1 and MIOB2 as described above.

  As described above, a switch is provided between the local input / output line LIO and the main input / output line MIO, a plurality of local input / output lines LIO are allocated to the main input / output line MIO, and only the selected one is the main input / output line. Although the case where the present invention is applied to a hierarchical input / output line connected to an MIO has been described, even if the local input / output line LIO and the main input / output line MIO are directly connected, one end mat is formed as described above. For the local input / output lines corresponding to the above, a switch similar to the above is provided.

  FIG. 12 is a block diagram showing another embodiment of the IO (input / output line) system circuit of the DRAM according to the present invention. In this embodiment, the memory mat is composed of an end mat and two normal mats as in FIG. The local input / output lines LIO <0> to LIO <5> are provided in the sense amplifier blocks (SA Blocks) 0 to 5 formed between the memory mats.

  On the other hand, main input / output lines MIO <0> to MIO <3> are provided in the memory mat arrangement direction, in other words, in the bit line extending direction. In the memory mat configuration as described above, when the memory mat is divided into two sets and data is input / output in units of 4 bits in total by 2 bits from each set, the local input / output line LIO < 1> corresponds to the main input / output line MIO <1>, the local input / output line LIO <2> corresponds to the main input / output line MIO <0>, and the local input / output line LIO <3> in the other set is the main. Corresponding to the input / output line MIO <2>, the local input / output line LIO <4> is made to correspond to the main input / output line MIO <4>.

  In the above case, when the normal mat 0 and 3 word lines are selected as in (a), the local input / output line LIO <1> is made to correspond to the main input / output line MIO <1>, and Since the input / output line LIO <4> is associated with the main input / output line MIO <3>, in order to avoid data collision, the other local input / output line LIO <0> is connected to the main input / output line MIO <3>. 0>, and the local input / output line LIO <5> needs to correspond to the main input / output line MIO <2>.

  On the other hand, when two end mat and center mat word lines are selected as shown in (b), the local input / output line LIO <2> is made to correspond to the main input / output line MIO <0>. Since the local input / output line LIO <3> is associated with the main input / output line MIO <2>, the other local input / output line LIO <0> is connected to the main input / output in order to avoid data collision. The local input / output line LIO <5> needs to correspond to the main input / output line MIO <3>, corresponding to the line MIO <1>.

  In this embodiment, therefore, the local input / output lines LIO <0> and LIO <5> provided in the sense amplifier blocks 0 and 5 provided between the one end mat and the normal mat as described above are connected to the main input. A changeover switch is provided between each of the output lines MIO <0> and MIO <1> and the main input / output lines MIO <2> and MIO <3>, as described above for normal mat access and end mat access. Switching of the signal transmission path is performed in order to respond appropriately.

  FIG. 13 is a schematic diagram showing one embodiment of the bit line configuration of the end mat in the DRAM according to the present invention. FIG. 13A shows an array configuration diagram of simple one-intersection sense amplifiers alternately arranged. As for the end mat, there is an invalid bit line that is not connected to the sense amplifier SA. An end mat similar to the above is also provided on the other end side of the sense amplifier SA corresponding to the memory mat MATn, but is omitted in FIG. Since the invalid bit lines (dummy bit lines) as described above exist, the number of effective memory cells provided in the end mat is half of the normal mat, so that the word lines of the end mats on both sides as described above. Are selected at the same time, and the two are accessed together to perform memory access in the same manner as a normal mat.

  FIG. 13B shows the bit line of the end mat folded. In other words, by utilizing the wiring area of the invalid bit line, the bit line of the end mat is folded and arranged utilizing the wiring area where the invalid bit line exists. By such bit line folding, the length of the end mat in the bit line direction can be shortened to half the length of the normal mat in the bit line direction, so that the area of the end mat can be reduced. Since this area reduction is also performed in the other memory mat, as a result, the area can be reduced by one normal mat.

  When there are a plurality (N) of memory mats in the word line direction, the area of N normal mats as a whole can be reduced. Incidentally, in the dynamic RAM as in the embodiment of FIG. 1, there are four memory arrays in total, and the area corresponding to four normal mats in each memory array can be reduced. The area equivalent to 16 pieces can be reduced.

  FIG. 14 shows a waveform chart of the read selection operation of the folded end mat. When the bit line is folded to reduce the area of the end mat as described above, the read charges from the two memory cells are transmitted to the bit line by the word line selection operation. That is, as shown in (a), the read signal amount of the bit line of the normal mat is doubled as shown in (b).

  Therefore, the overdrive period of the sense amplifier that amplifies the read signal of the bit line of the end mat is shortened compared to the overdrive period set in the sense amplifier when a minute signal of the bit line of the normal mat is amplified. Alternatively, when the read signal of the bit line of the end mat is amplified, the overdrive of the sense amplifier is omitted. By such timing adjustment, the end mat can be read out in substantially the same manner as the normal mat.

  FIG. 15 shows a circuit diagram of an embodiment of the sense amplifier control circuit. When the end mat word line is selected, the two sense amplifier rows operate at a relatively large distance, and the concentration of current required for the amplification operation of the sense amplifier is reduced in the wiring for supplying the operating voltage, resulting in high efficiency. In other words, the current is supplied, in other words, the voltage drop in the power supply line due to the increase in the operating current is reduced, so that the amplification operation of the sense amplifier is accelerated accordingly.

  In addition, when the bit line is folded at the end mat as described above and two memory cells are selected by selecting one word line, the amount of signal read to the bit line is doubled as described above. growing. Therefore, two activation signals are provided to reduce the overdrive period of the sense amplifier when the end mat is selected. The signal RSAET is a sense amplifier activation signal. When the end mat is not selected, a high level of the signal MSWEB causes a delay signal transmitted through two delay circuits (delays) to be transmitted and corresponds to the delay time. An overdrive pulse is generated to turn on the MOSFET Q30 and supply an overpulse such as the power supply voltage VDD to the common source line SDP of the P-channel MOSFET of the sense amplifier.

  On the other hand, when the end mat is selected, the signal MSEB goes low and opens the gate for transmitting the delay output of one delay circuit, so that an overdrive pulse is generated for the delay time, The MOSFET Q30 is turned on. This can prevent the sense amplifier from being overdriven excessively when the end mat is selected. After the elapse of the delay time corresponding to the overdrive, the MOSFET Q30 is turned off and the MOSFET Q31 is turned on to supply the original operating voltage of the sense amplifier such as VDL. The common source line SDN of the N-channel MOSFET is supplied with the circuit ground potential Vss by turning on the MOSFET Q32 by the high level of the activation signal RSAET.

  In the DRAM of this embodiment, the power supply voltage VDD is set to a relatively high voltage such as 3.3V or 2.5V, and the VDL is stepped down to a voltage such as 2.2V or 1.8V. Low voltage. At the start of the amplification operation of the sense amplifier, by using an overdrive voltage such as the voltage VDD higher than the voltage VDL, the complementary bit lines BLT and BLB are set to the high level side corresponding to the storage information of the memory cell. The rise of the bit line to the VDL is made as fast as possible. When the signal amount is large as in the end mat and the overdrive period is long, there is a disadvantage that the high level of the bit line exceeds VDL. Therefore, the timing adjustment as described above is necessary.

  FIG. 16 shows a schematic layout diagram of an embodiment of the folded end mat. FIG. 16A is configured such that a bit line having one end connected to one input / output node of the sense amplifier SA is folded at an intermediate portion in the extending direction. That is, the bit line and the invalid bit line adjacent to the bit line are connected to each other at the intermediate portion, and the other half is omitted. In this embodiment, although not particularly limited, two adjacent bit lines are validated due to the layout of the sense amplifier, invalid bit lines are arranged on both sides thereof, and the invalid bit line portion is used as the upper side. These bit lines constitute the folded portion on the upper side, and the lower bit lines constitute the folded portion on the lower side. The end mat is configured by repeating the above pattern.

  The connection of the folded portion is not particularly limited, but as shown in the sectional view of FIG. 17A, the bit line is the first metal layer M1 as shown in the sectional view of FIG. The first polysilicon layer FG constituting the gate electrode and the word line of the MOSFET and the FG contact connecting the FG and M1 are connected. When the phase shift method, which is one of the microfabrication techniques, is used, the adjacent bit lines are formed in different processes, and therefore need to be connected to each other using the FG and FG contacts.

  FIG. 16B is configured such that a bit line having one end connected to one input / output node of the sense amplifier SA is folded back using every other bit line at the intermediate portion in the extending direction. In other words, a bit line connected to one sense amplifier branches at a connection portion with the sense amplifier, branches so as to be every other bit, and is extended by half the length of a normal mat bit line. . The bit line connected to the sense amplifier adjacent to the sense amplifier is extended to half the length of the bit line of the normal mat without branching from the connection portion, and is bent from there and is sensed between the branched bit lines It is extended toward the side. That is, the branch bit lines and the folded bit lines are arranged alternately. The end mat is configured by repeating the above pattern.

  The connection of the folded portion is not particularly limited. However, as shown in the cross-sectional view of FIG. 17B, the bit line is formed of the first metal layer M1 as shown in the cross-sectional view of FIG. In other words, when the phase shift method, which is one of the above-described microfabrication techniques, is used, bit lines are formed every other line. Therefore, the branch bit line and the folded bit line are formed in each step. It can be formed integrally.

  FIG. 18 is a schematic diagram showing another embodiment of the bit line configuration of the end mat in the DRAM according to the present invention. In this embodiment, the end mat is a folded bit line. Thus, two memory cells are connected in parallel at the intersection of the word line and the bit line. Such an end mat is not particularly limited, but is a redundant mat for relieving a defective word line generated in the normal mat.

  When the end mat as described above is a redundant mat, the number of memory cells connected to the word line is halved, so that the word line is selected in the end mat as described above. The configuration in which the end mat is used as a redundant mat and the two memory cells are arranged at the intersections of the word lines and the bit lines as described above is not limited to simply reducing the area occupied by the end mats. An excellent effect of increasing efficiency can also be achieved.

  When two memory cells are connected in parallel to the bit line as described above, the signal amount can be doubled as described above. That is, in the end mat, it is possible to eliminate almost all the memory cells that become defective due to a short information holding time. Therefore, when switching to the redundant mat, there is a defect that the information holding time is short in the redundant mat. The probability of occurrence and failure of repair can be greatly reduced.

  FIG. 19 is a schematic diagram showing another embodiment of the bit line configuration of the end mat in the DRAM according to the present invention. In this embodiment, the end mat is a folded bit line, which is usually used for mat reference. In this case, the word line is fixed to the ground potential VSS of the circuit or the half precharge voltage VDL / 2 of the bit line. By fixing the potential of the word line as described above, it is possible to reduce noise generated in the end mat during reading.

  FIG. 20 is a schematic layout diagram showing one embodiment of a DRAM to which the present invention is applied. In this embodiment, as in FIG. 1, the memory array is divided into four as a whole, and each constitutes memory banks BANK0 to BANK3. As exemplarily shown as one memory bank BANK1, 33 memory mats and two end mats are provided in the bit line direction (YS), and four memory mats are provided in the word line direction (MWL). A memory mat is arranged.

  An input / output interface circuit including an address input circuit, a data input / output circuit, and a bonding pad row, a power supply circuit including a booster circuit and a step-down circuit, and the like are provided at a central portion in the longitudinal direction of the semiconductor chip. A main word driver MWD is arranged along these central portions, and drives a main word line MWL arranged so as to pass through the four memory mats and reach each sub word driver. A column decoder region YDC is provided at the chip end in the short direction of the semiconductor chip, and penetrates the 33 normal mats and one end mat from there to reach the sense amplifier row corresponding to them. The column selection line YS is driven.

  In this embodiment, the central mat provided at the center of the 33 normal mats arranged in the bit line direction and the end mat are used as the redundant mat MAT. That is, as shown in FIG. 6 or FIG. 12, the memory mat is divided into two sets at the central portion, and one word line is selected in each set of normal mats. When there is a word line defect in the normal mat selected in any group, the two word lines of the center mat and the end mat are selected to repair the word line defect. As described above, when the bit line of the end mat is folded and the redundant cell is constituted by two memory cells, two word lines may be simultaneously selected in the central mat.

  FIG. 21 shows an enlarged view of the end mat and the normal mat adjacent thereto in the memory bank BANK1 shown in FIG. In this embodiment, a hierarchical word line system is adopted, and a word line (sub word line) provided in a memory mat is selected by a combination of a main word line MWL and a sub word selection signal FX. The sub word selection signal FX is an operating voltage of the sub word driver SWD as will be described later, and its voltage level is used as a sub word line selection signal.

  In a dynamic memory cell, information charges are supplied to a storage capacitor through an address selection MOSFET. In order to transmit the high level of the bit line to the storage capacitor, the gate voltage of the MOSFET needs to be higher than the threshold voltage of the MOSFET with respect to the high level of the bit line. In order to reduce the leakage current (subthreshold leakage current) in the off state, the address selection MOSFET has an effective threshold value by forming a thick gate insulating film or supplying a negative back bias voltage to the substrate. The voltage is increased.

  Therefore, the selection level of the sub word line needs to be a boosted voltage VPP that is higher than the threshold voltage of the MOSFET with respect to the high level (VDL or VDD) of the bit line, and corresponds to the boosted voltage VPP. An FX driver for transmitting the sub word line selection signal to each sub word driver SWD is required. The FX driver corresponding to the sub word driver SWD of the normal mat can be provided in an intersection area where the sense amplifier array SA and the sub word driver array SWD intersect. On the other hand, in the open bit configuration, when the sense amplifiers are alternately arranged, the end of the memory bank ends with a memory cell, so that there is no intersection area and the FX driver cannot be provided.

  When the end mat is simply used for reference, the word line need only be set at a fixed level in the end mat as described above, so that a sub word driver is not required, and the above-described problem does not occur. On the other hand, when it is used as a redundant mat as in this embodiment, it is necessary to operate the sub word driver when repairing a defective word line. In this embodiment, a part of the redundant SWD is used as the FX driver area in the end mat. That is, when the end mat is used as a redundant mat, it is not necessary to make use of all the word lines formed there, so that the end word line is a dummy word line and the corresponding sub word driver area is the FX driver area. It is intended to be used.

  In this embodiment, as described above, one main word line MWL is provided for the four sub word lines WL0 to WL3. In order to select one of the four sub word lines, Sub-word selection lines FX0 to FX3, FX0B to FX3B are necessary. In this embodiment, half of the sub word lines provided in one memory mat are selected by the sub word driver array SWDA provided on both sides thereof. That is, as shown in FIG. 2, the sub-word drivers are distributed to both sides of the memory mat for every two word lines in the memory mat, and the staggered arrangement is performed as in the sense amplifier. Therefore, when four sub word lines are selected by one main word line as described above, a sub word selection signal for selecting one sub word line among the four sub word lines is 1 in the memory mat. It is divided into two sets, such as FX0 and FX2 and FX1 and FX3.

  FIG. 22 is a circuit diagram showing one embodiment of the FX driver and the sub word driver according to the present invention. The sub-word driver is composed of a CMOS inverter circuit and an N-channel type MOSFET provided between the output of the CMOS inverter circuit and the ground potential of the circuit. The selection signal MWLB from the main word line is commonly supplied to the input terminals of the two CMOS inverter circuits provided in the sub word driver region. The main word selection signal MWLB is also supplied in common to the input terminals of two CMOS inverter circuits provided in the sub word drive region provided on the other end side of the redundant mat shown in the figure to select four sub word lines. .

  The sub-word line selection signals FX0 and FX2 formed by the FX driver are respectively supplied to the power supply terminals of the two CMOS inverter circuits, that is, the source terminals of the P-channel MOSFETs constituting the CMOS inverter circuit. In these FX drivers, the operating voltage is set to the boosted voltage VPP, and the selection level of the sub word line selection signals FX0 and FX2 is set to the boosted voltage VPP. Input signals FX0B and FX2B supplied to the input terminal of the FX driver are supplied to the gate of an N-channel MOSFET provided between the output of the sub word driver and the ground potential of the circuit. In the FX driver adjacent to the FX driver (not shown), the sub word line selection signals FX1 and FX3 are formed.

  When the main word line selection signal MWLB is at a low level, the P-channel MOSFET of the CMOS inverter circuit is turned on and the N-channel MOSFET is turned off. Accordingly, in the sub word driver SWD in which the sub word line selection signal FX0 or FX2 is set to the selection level VPP by the FX driver, the sub word line SWL0 or SWL2 is set to the VPP level. At this time, in the non-selected one, the sub word line selection signal FX0B or FX2B becomes high level, and the switch MOSFET is turned on to fix the sub word line SWL0 or SWL2 to the circuit ground potential. The sub word line SWL corresponding to the area in which the FX driver is provided is not particularly limited, but is a dummy word line and is not particularly limited, but is set to a non-selection level such as a circuit ground potential.

  FIG. 23 shows a layout diagram of an embodiment of the FX driver and the sub word driver according to the present invention. Since the FX driver forms the operating voltage of a plurality of sub-word drivers, in order to have a large current supply capability, the FX driver is compared with the MOSFET constituting the sub-word driver illustrated in FIG. Are composed of a large-sized N-channel MOSFET (NMOS) and a P-channel MOSFET (PMOS). In order to form the FX driver by the large-sized MOSFET as described above, about 36 word lines formed on the end mat are set as dummy word lines, and the corresponding sub-word driver area is used for the FX driver. Used to form.

  FIG. 24 shows a schematic layout of another embodiment of the dynamic RAM according to the present invention. In this embodiment, although not particularly limited, the memory array is divided into four as a whole. Two memory arrays are provided separately on the upper and lower sides and two on the left and right along the longitudinal direction of the semiconductor chip. Up to this point, the embodiment is the same as the embodiment shown in FIGS.

  In this embodiment, word lines are arranged along the longitudinal direction of the chip, and bit lines are arranged along the short direction of the chip. That is, the directions of the bit lines and the word lines are opposite to those of the embodiments of FIGS. As described above, in each of the memory arrays consisting of a total of four divided into two on the top and bottom along the longitudinal direction of the semiconductor chip and two on the left and right, there is no particular limitation on the intermediate portion with respect to the longitudinal direction. , An X-system predecoder circuit and a relief circuit, a Y-system predecoder circuit and a relief circuit are arranged. A main word driver area MWD is formed along the intermediate portion of the memory array, and each main word line provided to extend downward and upward corresponding to each memory array is driven. The

  In the memory array, a Y decoder YDEC is provided on the chip peripheral side opposite to the chip central portion. The memory array is divided into a plurality of memory mats as described above. Such a memory mat is formed by being surrounded by a sense amplifier region and a sub word driver region arranged so as to sandwich the memory mat. An intersection of the sense amplifier amplifier area and the sub word driver area is an intersection area. The sense amplifiers provided in the sense amplifier region are in the one-intersection method and in a staggered arrangement.

  The selection operation of the Y system is transmitted to the Y decoder YDEC arranged on the peripheral side of the chip through the relief circuit and predecoder provided in the intermediate part of the memory array through the address buffer provided in the center part of the chip. Here, the Y selection signal is formed. A bit line of one memory mat column is selected from the Y selection signal, transmitted to the main amplifier MA provided in the center of the chip on the opposite side, and output through an output circuit provided in the center of the chip. Is done.

  At first glance, this configuration is determined so that the time from when the signal is routed around the chip until the read signal is output becomes longer. However, since it is necessary to input the address signal as it is to the relief circuit, if the relief circuit is arranged at one of the center of the chip, the output time of the predecoder is determined based on the determination result of whether it is a defective address or not. Is done. That is, if the predecoder and the relief circuit are separated from each other, the signal delay at that point causes the actual Y selection operation to be delayed.

  Looking at the signal transmission path for reading in the memory array, in the layout method in which the Y decoder exists in the center portion of the chip, when reading from the complementary bit line of the memory mat on the opposite side of the chip, The time required for traversing the memory array for the Y selection signal to be transmitted, and the read signal from the complementary bit line of the memory mat at the periphery of the chip through the input / output line are the Y selection signal. In the opposite direction, the time required to be transmitted to the main amplifier across the memory array is added.

  In other words, in the worst case, the signal flow slows down so as to reciprocate once in the memory array. However, in the present invention, the main amplifier MA and the Y decoder YDEC are arranged on both sides across the memory array. The sum of the signal transmission path for selecting the mat complementary bit line and the signal transmission path from the selected complementary bit line to the input of the main amplifier MA through the input / output line selects which complementary bit line. At any rate, it becomes a signal transmission path that only traverses the memory array and can be shortened to half that of one round trip as described above.

  In the layout as described above, it is more convenient that the end mats are arranged in the longitudinal direction of the chip near the center of the chip. When the sense amplifiers are arranged in a staggered manner by the one-intersection method as described above, the memory cell ends at the memory array end. That is, in the conventional two-intersection method, since the sense amplifier ends at the end of the memory array, it is necessary to extend the Y selection line to the sense amplifier portion. In order to end with the memory cell, the Y selection line can be terminated with a sense amplifier row provided between the normal mat and the end mat.

  This configuration means that there is no Y selection line in the portion where the end mat is formed. As a result, in the cross-sectional view of FIG. 3, the second metal wiring layer M2 and the third metal wiring layer are used for the Y selection line and the main word line. Either the second layer wiring or the third layer wiring used as the Y selection line on the upper side becomes free. Therefore, the second or third layer wiring corresponding to the Y selection line on the end mat is used as a signal wiring for a peripheral circuit provided in the central portion.

  As the dynamic RAM becomes multifunctional, the main side circuit provided in the center of the chip is not a regular circuit configuration like a memory array, but a random logic circuit, and the signal lines are complicated. Need to be formed. That is, in the dynamic RAM, the wiring is the most crowded area and requires a large number of signal lines. Therefore, the number of wirings in the chip central region can be substantially reduced by using the end mat as the wiring region. Incidentally, in the mat configuration as described above, about 100 signal lines can be formed, and in the peripheral circuit, the number of wirings extending in the end mat arrangement direction is the largest at about 200. The use of the end mat as a wiring region is significant.

  FIG. 25 shows an overall block diagram of an embodiment of the dynamic RAM according to the present invention. The control input signals are a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, and an output enable signal / OE. Here, / corresponds to an overbar of a logical symbol where the low level represents the active level. The X address signal and the Y address signal are input from a common address terminal Add in time series in synchronization with the row address strobe signal / RAS and the column address strobe signal / CAS.

  The X address signal and the Y address signal input through the address buffer are respectively taken into the latch circuits. The X address signal taken into the latch circuit is supplied by the predecoder as described above, and the output signal is supplied to the X decoder to form a selection signal for the word line WL. The read signal as described above appears on the complementary bit lines of the memory array by the word line selection operation, and the amplification operation is performed by the sense amplifier. The Y address signal taken into the latch circuit is supplied to the predecoder as described above, and the output signal is supplied to the Y decoder to form a selection signal for the bit line DL. The X relief circuit and the Y relief circuit compare the storage operation of the defective address with the stored defective address and the captured address signal, and if they match, select the spare word line or bit line to select the X decoder and Y decoder. And the selection operation of the normal word line or the normal bit line is prohibited.

  The stored information amplified by the sense amplifier is selected by a column switch circuit (not shown) and connected to the common input / output line and transmitted to the main amplifier. The main amplifier is not particularly limited, but is an amplifier that also serves as a writing circuit. That is, during the read operation, the read signal read through the Y switch circuit is amplified and output from the external terminal I / O through the output buffer. In the write operation, a write signal input from the external terminal I / O is taken in via the input buffer and transmitted to the common input / output line and the selected bit line via the main amplifier. The write signal is transmitted by the amplification operation, and the charge corresponding to the signal is held in the capacitor of the memory cell.

  The clock generation circuit (main control circuit) performs a memory cell selection operation such as an address signal fetch control timing signal input corresponding to the signals / RAS and / CAS, an operation timing signal of a sense amplifier, and the like. Various necessary timing signals are generated. The internal power supply generation circuit receives operating voltages such as Vcc and Vss supplied from the power supply terminal, and receives the plate voltage, precharge voltage such as Vcc / 2, internal boosted voltage VCH, internal buck voltage VDL, and substrate back bias. Various internal voltages such as the voltage VBB are generated. The refresh counter generates a refresh address signal when the riff mode is set, and is used for an X-system selection operation.

  In this embodiment, an end mat control circuit is provided. In other words, when data is read or written from the end mat, when selecting the end mat, two word lines corresponding to each are selected, and switching of the main amplifier is performed correspondingly. The switching of the IO switch circuit is also performed so as to avoid the collision of data as described above. When the end mat is used as a redundancy circuit, the word line of the end mat is selected by a signal from the X relief circuit, so that the end mat control circuit can be replaced with it.

The effects obtained from the above embodiment are as follows.
(1) A plurality of memory mats including a plurality of bit lines, a plurality of word lines, the plurality of bit lines and a plurality of memory cells coupled to the plurality of word lines are arranged in the bit line direction; Provided in a region between the memory mats arranged in the bit line direction and provided with a sense amplifier array including a plurality of latch circuits in which input / output nodes are connected to half of the bit lines provided in the memory mat. Thus, for the normal memory mat excluding both ends in the bit line direction, the word line of any one of the memory mats is activated, and the end memory mat provided at both ends in the bit line direction is both memory By simultaneously activating the word lines of the mat, while ensuring the operating margin of the sense amplifier, it is possible to use the end mat effectively The effect that the occupied area can be reduced can be obtained.

  (2) In addition to the above, the bit line of the end memory mat is formed using two bit line pitches of the bit line of the normal memory mat, and the length in the bit extension direction is the same as that of the normal memory mat. By making it shorter than the length in the extending direction of the bit line, an effect that the end mat can reduce the occupied area can be obtained.

  (3) In addition to the above, by forming the bit line of the end memory mat so as to be folded back at a distance of more than half of the normal memory mat from the connection portion with the latch circuit of the sense amplifier row, the area occupied by the end mat The signal amount can be increased when the stored information is read out from the end mat while reducing the signal.

  (4) In addition to the above, the bit line of the end memory mat is branched from the connection portion with the latch circuit of the sense amplifier row at an interval twice the bit line pitch, and is half of the bit line of the normal memory mat. It extends linearly from the connecting portion between the two first bit line pairs extending in length and the latch circuit of the sense amplifier row to half the length of the bit line of the normal memory mat, and from there The first and second bit lines are integrally formed when the wiring is formed by the phase shift method by being configured with a combination with the second bit line folded back so as to be sandwiched between the first bit line pair. The effect that it can be obtained.

  (5) In addition to the above, the word line of the end memory mat is connected to the gates of MOSFETs of two memory cells connected to one bit line, thereby reducing the area occupied by the end mat. When the stored information is read from the mat, the signal amount can be increased.

  (6) In addition to the above, a first complementary input / output line along the sense amplifier row, a precharge circuit for supplying a precharge voltage corresponding to an intermediate voltage of the operation voltage of the sense amplifier, and a column selection switch MOSFET, As a result, it is possible to rationally arrange each element necessary for selecting a memory cell.

  (7) In addition to the above, the first complementary input / output lines 1 and 2 are provided in common corresponding to the plurality of memory mats, and the first amplifier provided in the sense amplifier row corresponding to one end memory mat. The complementary input / output line is connected to 1 of the second complementary input / output line, and the bit line of the normal memory mat is selected as the first complementary input / output line provided in the sense amplifier row corresponding to the other end memory mat. When the bit line of the second complementary input / output line is selected, a switch is connected to the second complementary input / output line 2 when the bit line of the second memory input / output line is selected. As a result, it is possible to input and output write and read data while preventing data collision.

  (8) In addition to the above, among the memory mats arranged in the extending direction of the bit lines, the word line is substantially divided into two sets around the central memory mat provided in the center, and the center The effect of being able to input / output data to a larger number of memory cells by combining the bit lines of half of the memory mats and the bit lines of the end memory mat to perform the memory cell selection operation. Can be obtained.

  (9) In addition to the above, when the word line of the end memory mat is selected, timing control is performed so as to slow down the amplification speed of the sense amplifier so that the read operation from the normal mat is matched. The effect that it can be obtained.

  (10) In addition to the above, the word line has a hierarchical configuration of a main word line and a sub word line divided into a plurality in the extending direction of the main word line, and a sub word corresponding to the divided sub word line. A driver is provided, and a plurality of the sub word lines are assigned to the main word line, and the sub word driver receives a signal of the main word line and a signal of the sub word selection line and assigns one of the plurality of sub word lines to the main word line. By selecting, the effect of reducing the number of main word lines can be obtained.

  (11) In addition to the above, by using the memory cell provided in the end memory mat as a redundant memory cell used for repairing a defective memory cell, the repair efficiency of the defective word line is increased by the large signal amount. The effect that it can be obtained.

  (12) In addition to the above, the word line selection preparation operation in the row selection circuit provided corresponding to the end memory mat is the same as the word line selection preparation operation in the row selection circuit provided in the normal memory mat. By performing at the timing, it is possible to increase the memory access speed.

  (13) In addition to the above, a memory cell provided in the end memory mat is used as a redundant memory cell used for repairing a defective memory cell, and a subword selection line driving circuit is formed in a part of the subword driver. By forming the bit line provided in the end memory mat corresponding to the driving circuit as a dummy word line, the area occupied by the end mat selection circuit can be reduced.

  (14) A plurality of memory mats including a plurality of bit lines, a plurality of word lines, the plurality of bit lines and a plurality of memory cells coupled to the plurality of word lines are arranged in the bit line direction; Provided in a region between the memory mats arranged in the bit line direction and provided with a sense amplifier array including a plurality of latch circuits in which input / output nodes are connected to half of the bit lines provided in the memory mat. Thus, for the end memory mats provided at both ends, the bit line used as a fixed voltage for keeping the MOSFET off is used to form a reference voltage, and the bit lines in the bit lines of the normal memory mat are used. Using two pitches, the overall length and the number of connected memory cells are substantially the same as the bit lines of a normal memory mat. By way while achieving securing of the operation margin of the sense amplifier, there is an advantage that it is possible to reduce an area.

  (15) The bit line of the end memory mat is formed so as to be folded back at a half distance of the normal memory mat from the connection portion with the latch circuit of the sense amplifier row, thereby securing an operation margin of the sense amplifier, The effect that the occupied area can be reduced is obtained.

  (16) In addition to the above, the bit line of the end memory mat is branched from the connection portion with the latch circuit of the sense amplifier row at an interval of twice the bit line pitch, and half the bit line of the normal memory mat It extends linearly from the connecting portion between the two first bit line pairs extending in length and the latch circuit of the sense amplifier row to half the length of the bit line of the normal memory mat, and from there The first and second bit lines are integrally formed even when the wiring is formed by the phase shift method by being configured with a combination with the second bit line folded back so as to be sandwiched between the first bit line pair. The effect that it can do is acquired.

  (17) In addition to the above, a plurality of memory mats are provided in the bit line direction and the word line direction to form one memory array, and at least two of the memory arrays are mounted on a semiconductor chip. A column selection circuit for forming the bit line selection signal is provided adjacent to one end memory mat in the memory array corresponding to the end of the semiconductor chip, and transmits the bit line selection signal on the other end memory mat. By using the same wiring layer as the wiring layer as a part of the wiring layer of the peripheral circuit provided in the central part of the semiconductor chip sandwiched between the two memory arrays, the chip central part sandwiched between the two memory arrays. The effect that the wiring can be relaxed is obtained.

  The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the word line may be configured by a two-layer structure with a metal layer in addition to the hierarchical word line system as described above. The input / output interface of the dynamic RAM may be adapted to various types such as DDR SDRAM and SDRAM, and the dynamic RAM may be incorporated in a digital integrated circuit. The present invention can be widely used in a dynamic RAM and a semiconductor device in which sense amplifiers are configured in a staggered configuration with a one-intersection method.

DESCRIPTION OF SYMBOLS 10 ... Memory chip, 11 ... Array control circuit, 12 ... Main word driver, 13 ... Column decoder, 15 ... Memory mat (memory mat), 16 ... Sense amplifier, 17 ... Subword driver, 18 ... Crossing area, SAA ... Sense amplifier Column, SWDA ... subword driver column, MAT1, MAT2 ... memory mat (memory mat), SA ... sense amplifier, SWD ... subword driver, PL0, PL1 ... plate electrode, PLSA ... wiring, MWL ... main word line, WL ... subword line , BL ... bit line, ACT ... active region, TC1, TC2 ... contact part, SN ... storage node, CONT ... contact part, CP ... capacitive insulating film, BLCT ... contact part, M1 to M3 ... metal wiring layer, FX0 to FX7B ... subword selection line, Q1 to Q32 ... MOSFE , IV1, IV2 ... inverter circuit, FXD ... FX driver.

Claims (11)

A plurality of memory mats including a plurality of bit lines, a plurality of word lines, a plurality of memory cells coupled to the plurality of bit lines and the plurality of word lines are arranged in the bit line direction,
Each of the plurality of memory cells includes a capacitor having first and second electrodes, a gate coupled to a corresponding one of the plurality of word lines, one of which is one of the plurality of one bit lines. It consists of a MOSFET which have a drain passage, - coupled to a corresponding one, the other of the source coupled to the first electrode of the capacitor
Sense including a plurality of latch circuits provided in an area between the memory mats arranged in the bit line direction and having input / output nodes connected to half bit lines provided in the memory mat provided therebetween For a normal memory mat including an amplifier row and excluding both ends in the bit line direction, the word line of any one of the memory mats is activated, and the end memory mat provided at both ends in the bit line direction is The bit line used as a fixed voltage for maintaining the MOSFET in the off state is used for forming a reference voltage, and the total length and length of the bit line pitch in the bit line of the normal memory mat are used. The number of memory cells to be connected is usually made to be the same as the bit line of the memory mat. Dynamic RAM and butterflies. In claim 1,
The dynamic RAM, wherein the bit line of the end memory mat is formed so as to be folded back at a distance half of that of the normal memory mat from a connection portion with the latch circuit of the sense amplifier row. In claim 2,
The bit line of the end memory mat is
A first bit line pair consisting of two branches that branch from the connection portion of the sense amplifier row to the latch circuit at an interval of twice the bit line pitch, and are extended by half the length of the bit line of the normal memory mat;
A second bit that extends linearly from the connection with the latch circuit of the sense amplifier row to half the length of a bit line of a normal memory mat and is folded back so as to be sandwiched between the first bit line pair. dynamic RAM, characterized in that formed by a combination of the line. In any of claims 1 to 3,
The plurality of memory mats, sense amplifier arrays, and sub word drivers are provided in a plurality of sets in the bit line direction and the word line direction to constitute one memory array,
At least two of the memory arrays are mounted on a semiconductor chip, and a column selection circuit for forming a selection signal for the bit line is provided adjacent to one end memory mat in the memory array corresponding to the end of the semiconductor chip, The same wiring layer as the wiring layer for transmitting the bit line selection signal on the other end memory mat is used as a part of the wiring layer of the peripheral circuit provided in the central part of the semiconductor chip sandwiched between the two memory arrays. A dynamic RAM characterized by that. A plurality of first bit lines extending in a first direction; a plurality of first word lines; and a plurality of first memory cells coupled to the plurality of first bit lines and the plurality of first word lines. A memory mat,
A second memory mat including a plurality of second bit lines extending in the first direction; and a plurality of first sense amplifiers formed in a region between the first memory mat and the second memory mat;
Each of the plurality of first sense amplifiers is coupled to one corresponding bit line of the plurality of first bit lines and two corresponding bit lines of the plurality of second bit lines, A length of the second bit line in the first direction is shorter than a length of the plurality of first bit lines in the first direction. In claim 5,
The first memory mat further includes a plurality of third bit lines extending in the first direction, a plurality of first word lines, and a plurality of second memory cells coupled to the plurality of third bit lines. ,
The semiconductor device includes a plurality of fourth bit lines extending in the first direction, a plurality of second word lines, a plurality of fourth bit lines, and a plurality of third word lines coupled to the plurality of second word lines. A third memory mat including memory cells;
A plurality of second sense amplifiers formed in a region between the first memory mat and the third memory mat;
Each of the plurality of second sense amplifiers is coupled to a corresponding one of the plurality of third bit lines and a corresponding one of the plurality of fourth bit lines,
The semiconductor device, wherein the plurality of first bit lines and the plurality of third bit lines are alternately arranged in a direction perpendicular to the l-th direction. In claim 6,
Each of the plurality of first memory cells includes a first capacitor having a pair of electrodes, a gate coupled to a corresponding one of the plurality of first word lines, one of which is the plurality of first memories. A first transistor having a source-drain path that is plugged into a corresponding one of the bit lines and the other is coupled to one of the pair of electrodes of the first capacitor;
Each of the plurality of second memory cells includes a second capacitor having a pair of electrodes, a gate coupled to a corresponding one of the plurality of first word lines, and one of the plurality of third memory cells being the plurality of third memory cells. A second transistor having a source-drain path coupled to a corresponding one of the bit lines and the other coupled to one of the pair of electrodes of the second capacitor;
Each of the plurality of third memory cells includes a third capacitor having a pair of electrodes, a gate coupled to a corresponding one of the plurality of second word lines, one of which is the plurality of fourth memory cells. And a third transistor having a source-drain path coupled to a corresponding one of the bit lines and the other coupled to one of the pair of electrodes of the third capacitor. . In claim 5,
The length of the plurality of second bit lines in the first direction is half the length of the plurality of first bit lines in the first direction. A plurality of first bit lines extending in a first direction; a plurality of first word lines; a plurality of first bit lines; and a plurality of first memory cells coupled to the plurality of first word lines. 1 memory mat,
A plurality of second memory cells coupled to intersections of the plurality of second bit lines extending in the first direction, the plurality of second word lines, and the plurality of second bit lines and the plurality of second word lines. A second memory mat including:
A plurality of first sense amplifiers formed in a region between the first memory mat and the second memory mat, and each of the plurality of first sense amplifiers includes one of the plurality of first bit lines. One corresponding bit line and two corresponding bit lines of the plurality of second bit lines,
Each of the plurality of first memory cells includes a first capacitor having a pair of electrodes, a gate coupled to a corresponding one of the plurality of first word lines, one of which is the plurality of first memories. A first transistor having a source-drain path coupled to a corresponding one of the bit lines and the other coupled to one of the pair of electrodes of the first capacitor;
Each of the plurality of second memory cells includes a second capacitor having a pair of electrodes, a gate coupled to a corresponding one of the plurality of second word lines, one of which is the plurality of second memory cells. A second transistor coupled to a corresponding one of the bit lines and the other having a source-drain path coupled to one of the pair of electrodes of the second capacitor;
The length of the plurality of second bit lines in the first direction is shorter than the length of the plurality of first bit lines in the first direction. In claim 9,
The first memory mat further includes a plurality of third bit lines extending in the first direction, a plurality of third memory cells coupled to the plurality of first word lines and the plurality of third bit lines,
The semiconductor device includes a plurality of fourth bit lines extending in the first direction, a plurality of third word lines, a plurality of fourth bit lines, and a plurality of fourth word lines coupled to the plurality of third word lines. A third memory mat including memory cells;
A plurality of second sense amplifiers formed in a region between the first memory mat and the third memory mat;
Each of the plurality of second sense amplifiers is coupled to a corresponding one of the plurality of third bit lines and a corresponding one of the plurality of fourth bit lines,
Each of the plurality of third memory cells includes a third capacitor having a pair of electrodes, a gate coupled to a corresponding one of the plurality of first word lines, one of which is the plurality of third capacitors. A third transistor coupled to a corresponding one of the bit lines and the other having a source-drain path coupled to one of the pair of electrodes of the third capacitor ;
Each of the plurality of fourth memory cells includes a fourth capacitor having a pair of electrodes, a gate coupled to a corresponding one of the plurality of third word lines, one of which is the plurality of fourth memory cells. A fourth transistor having a source-drain path coupled to a corresponding one of the bit lines and the other coupled to one of the pair of electrodes of the fourth capacitor;
The plurality of first bit lines and the plurality of third bit lines are alternately arranged in a direction perpendicular to the first direction. In claim 9,
The length of the plurality of second bit lines in the first direction is half the length of the plurality of first bit lines in the first direction.

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