JP4487227B2 - Dynamic RAM - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a dynamic RAM (Random Access Memory), and relates to a technique that is effective when used in a so-called one-intersection system in which dynamic memory cells are arranged at the intersections of word lines and bit lines. .
[0002]
[Prior art]
As a result of the investigation after the present invention is considered, it is considered to be related to the present invention which will be described later, Japanese Patent Application Laid-Open No. 59-2365 (hereinafter referred to as Prior Art 1), Japanese Patent Application Laid-Open No. 60-19595 ( Hereinafter, it has been found that there is JP-A-60-211871 (hereinafter referred to as Prior Art 3).
[0003]
Prior arts 1 to 3 relate to a voltage supply technique for a plate electrode in an open bit line type (one-intersection system) using an information storage capacitor using a MOS capacitor. In the prior art 1, the first wiring crossing in the direction orthogonal to the bit line and connected at a plurality of locations in order to equalize the accurate potential distribution of the counter electrode of the information storage capacitor, and the first wiring A second wiring connected to each other and a third wiring connecting the central portion of the second wiring to the power supply line of the peripheral circuit are provided. In the prior art 2 publication, a resistor is provided between two plate electrodes provided across a sense amplifier, and the plate electrode corresponds to a change in substrate voltage when information stored in a memory cell is read out to a bit line. Slows the change in potential. In the prior art 3, the plate electrode and the wiring for supplying voltage to the plate electrode are formed of a high melting point, low resistance metal or a silicide of the metal and silicon, or a plurality of wires are formed on the plate electrode. A metal wiring layer is provided.
[0004]
[Problems to be solved by the invention]
Cost reduction is desired for dynamic RAM (hereinafter simply referred to as DRAM). For this purpose, reduction of the chip size is the most effective. Until now, the memory cell size has been reduced by further miniaturization. However, it is necessary to further reduce the cell size by changing the operation method of the memory array in the future. By changing the operation method of the memory array from two intersections to one intersection, the cell size can be ideally reduced by 75% using the same design rule. However, the one-intersection type memory array has a problem that the array noise on the bit line or the like is larger than that of the two-intersection type memory array. If this is not solved, it is difficult to apply the product.
[0005]
Therefore, the noise generated when the memory cell used in the conventional two-intersection method is used as it is to constitute a one-intersection memory array is examined. Parasiticity between the bit line and the substrate (well) is studied. It has been found that the noise on the bit line increases with the capacitance.
[0006]
Deterioration of the operation margin of the memory array due to substrate noise will be described with reference to FIG. In the one-intersection array shown in (a), in the worst case, all but one bit line of the selected mat is amplified to low level (L), and all bit lines of the mat on the reference side are all high. Amplified to (H). At this time, there is a danger that the bit line outputting only one high level signal in the selected mat will be amplified by receiving noise from the substrate.
[0007]
As an example, let us consider a case where the word line WL0 is activated, a high level signal appears only on the bit line BL1T, and a low level signal is read on the other bit lines BL0T, BL2T, and the like. Further, it is assumed that a high level signal generated on the bit line BL1T is small due to a leak of the memory cell. When the sense amplifier is activated, the bit lines BL0T / B, BL2T / B, etc. from which signals are increasing are amplified quickly. On the other hand, the bit line BL1T / B with few signals is slowly amplified. At this time, negative noise is generated in the substrate (well region) SUB0 of the selection side mat from the bit lines BL0T, BL2T, etc. via the parasitic capacitance CBLSUB. Conversely, positive noise is generated from the bit lines BL0B, BL2B, etc. on the substrate (well region) SUB1 of the adjacent mat.
[0008]
Conversely, when these noises return to the bit line BL1T / B from which the opposite signal is output from the substrates SUB0 and SUB1 via the parasitic capacitance CBLSUB, the signal amount is decreased and the potential of the bit line is reversed by mistake. is there. Therefore, in a memory array in which noise from such a substrate (well region) is not taken into consideration, there is a high risk that information is erroneously read when the amount of signal charge stored in the memory cell decreases. This leads to deterioration of refresh characteristics and causes a significant decrease in the yield of DRAM.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to provide a one-intersection dynamic RAM in which an operation margin is improved. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. A dynamic memory cell comprising a MOSFET and a capacitor, wherein the gate of the MOSFET is a selection terminal, one source and drain are input / output terminals, and the other source and drain are connected to the storage node of the capacitor. A plurality of word lines connected to the selection terminals of the plurality of dynamic memory cells, and a plurality of word lines connected to the input / output terminals of the plurality of dynamic memory cells. A plurality of complementary bit line pairs arranged to extend in opposite directions to each other, and a plurality of latch circuits arranged on one end side of the complementary bit line pair to amplify a voltage difference between the complementary bit lines, respectively. A plurality of memory mats including a sense amplifier array consisting ofIn the memory mat, a semiconductor layer for supplying a bias voltage to a semiconductor region in which the memory cell is formed is provided in parallel with the sense amplifier row at one or a plurality of locations where the bit line is equally divided in the extending direction of the bit line. The semiconductor layer is provided with a plurality of contact portions for supplying the bias voltage.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 10 is a schematic layout diagram of an embodiment of a dynamic RAM to which the present invention is applied. In the figure, the main part of each of the circuit blocks constituting the dynamic RAM to which the present invention is applied is shown so that it can be seen from a single crystal silicon by a known semiconductor integrated circuit manufacturing technique. Are formed on one semiconductor substrate.
[0012]
In this embodiment, although not particularly limited, the memory array is divided into four as a whole. The central portion 14 is provided with an input / output interface circuit including an address input circuit, a data input / output circuit, and a bonding pad row, a power supply circuit including a booster circuit and a step-down circuit, and the like. . A memory array control circuit (AC) 11 and a main word driver (MWD) 12 are arranged at portions of the central portion 14 in contact with the memory arrays on both sides. The memory array control circuit 11 includes a control circuit and a main amplifier for driving a sub word selection line and a sense amplifier. As described above, in each of the four memory arrays divided into two on the left and right with respect to the longitudinal direction of the semiconductor chip and two on the upper and lower sides, the column decoder area (YDC) is located at the upper and lower central portions with respect to the longitudinal direction 13 is provided.
[0013]
As described above, in each memory array, the main word driver 12 forms a selection signal for a main word line that extends so as to penetrate one memory array corresponding thereto. The main word driver area 12 is also provided with a sub word selection line driver for selecting a sub word, and is extended in parallel with the main word line to form a selection signal for the sub word selection line, as will be described later. The column decoder 13 forms a selection signal for a column selection line that extends so as to penetrate one memory array corresponding to the column decoder 13.
[0014]
Each memory array is divided into a plurality of memory cell arrays (hereinafter referred to as subarrays) 15. As shown in the enlarged view, the subarray 15 is formed by being surrounded by a sense amplifier region 16 and a subword driver region 17. An intersection of the sense amplifier region 16 and the sub word driver region 17 is an intersection region (cross area) 18. The sense amplifier provided in the sense amplifier region 16 is constituted by a latch circuit having a CMOS structure, and is a so-called one-intersection system that amplifies a complementary bit line signal extending left and right around the sense amplifier. .
[0015]
One memory cell array (subarray) 15 shown as an enlarged view is not particularly limited, but has 512 subword lines and 1024 complementary bit lines (or data lines) orthogonal thereto. In the one memory array, 32 subarrays 15 are provided in the bit line extending direction for regular use and 32 for reference in the bit line direction and two for reference. Since the subarray 15 is provided with a pair of complementary bit lines with the sense amplifier 16 as the center, the bit lines are substantially divided into 16 by the subarray 15 when viewed in the extending direction of the bit lines. Further, four subarrays 15 are provided in the extending direction of the word lines. As a result, when viewed in the extending direction of the word lines, the sub word lines are divided into four by the sub array 15.
[0016]
Since one subarray 15 is provided with 1024 bit lines, about 4K memory cells are connected in the word line direction and 512 subword lines are provided, so that 512 × 32 = 16K minutes in the bit line direction. Memory cells are connected. Thus, one memory array has a storage capacity of 4K × 16K = 64 Mbits, and the memory chip 10 as a whole has a storage capacity of 4 × 64 M = 256 Mbits by the four memory arrays. Is done.
[0017]
In the present application, the term “MOS” is understood to have originally come to be referred to simply as a metal oxide semiconductor configuration. However, the MOS in the general name in recent years includes those in which the metal in the essential part of the semiconductor device is replaced with a non-metal electrical conductor such as polysilicon, or the oxide is replaced with another insulator. Yes. CMOS has also been understood to have broad technical implications in response to changes in how it pertains to MOS as described above. MOSFETs are not understood in a narrow sense as well, but have become meanings including configurations in a broad sense that can be substantially regarded as insulated gate field effect transistors. The CMOS, MOSFET, and the like of the present invention follow the general names.
[0018]
FIG. 2 is a circuit diagram showing one embodiment of a one-intersection DRAM array according to the present invention. A memory cell composed of a MOS transistor and a cell capacitor CS is connected to every intersection of the bit line BL and the word line WL. A sense amplifier SA is connected to the bit line BL, and a sub word driver SWD is connected to the word line WL1. Memory cells are arranged in an array in an area (hereinafter referred to as a memory cell array or memory mat) MCA surrounded by the sub word driver array SWDA and the sense amplifier array SAA. For example, when one word line WL in the memory array MCA0 is activated, the sense amplifier SA in the sense amplifier array SAA1 uses the bit line of the memory cell array MCA1 on the opposite side for reference. Amplifies the bit line signal.
[0019]
In this embodiment, the memory cell array MCA is divided into two equal parts in the bit line direction like MCA1a and MCA1b. In the drawing, memory cells are exemplarily shown for one memory cell array MCA1a, and the other memory cell array MCA1b is shown by a black box. Between the two memory cell arrays MCA1a and MCA1b, a semiconductor layer for contact (hereinafter referred to as a substrate contact column) CNTA1m is provided in parallel with the sense amplifier array SAA, that is, in parallel with the word line. The memory mat provided on the left side of the sense amplifier array SAA1 is also divided into two like the two memory cell arrays MCA0a and MCA0b as described above, and the same substrate contact array CNTA0m is provided.
[0020]
The sense amplifiers SA of the sense amplifier array SAA1 provided between the two memory cell array subarrays MCA0 and MCA1 are connected to complementary bit lines extending to both sides of the two memory cell arrays MCA0 and MCA1. In these sense amplifiers SA, one sense amplifier SA is arranged for every two bit lines in the sense amplifier array SAA1. Accordingly, in the sense amplifier array SAA1 provided between the memory cell arrays MCA0 and MCA1, when there are 1024 bit lines BL as described above, 512 sense amplifiers SA which are half of the bit lines BL are provided.
[0021]
In one memory cell array MCA0, the remaining 512 bit lines are connected to a sense amplifier SA provided in the sense amplifier array SAA0 on the opposite side to the memory cell array MCA1. In the other memory cell array MCA1, the remaining 512 bit lines are connected to a sense amplifier SA provided in a sense amplifier array SAA2 provided on the opposite side to the memory cell array MCA0. With such a distributed arrangement of the sense amplifier SA on both sides in the bit line direction, it is only necessary to form one sense amplifier for two bit lines, so that the pitch between the sense amplifier SA and the bit line BL is increased. Memory cell arrays and sense amplifier arrays can be formed with high density.
[0022]
The same applies to the sub word driver SWD. The 512 sub-word lines WL provided in the memory cell array MCA0 are divided into 256 pieces and connected to 256 sub-word drivers SWD of the sub-word driver column SWDA arranged on both sides of the sub-array MCA0. In this embodiment, two sub word drivers SWD are distributedly arranged with two sub word lines WL as one set. Sub-word lines corresponding to two memory cells are set as one set, two sub-word drivers are arranged on one end side (the upper side in the figure) of the memory cell array MCT0, and two similar sub-word lines adjacent thereto are set as one set. Two sub word trivers are arranged on the other end side (lower side of the figure) of the memory cell array MCA0.
[0023]
Although not shown, the sub word driver SWD forms a selection signal for sub word lines of sub arrays provided on both sides of the sub word driver array SWDA in which the sub word driver SWD is formed. As a result, the sub word drivers SWD can be efficiently distributed and arranged corresponding to the sub word lines formed in accordance with the arrangement pitch of the memory cells, and the sub word line WL can be selected at high speed.
[0024]
FIG. 1 shows a block diagram of an embodiment of a one-intersection DRAM array according to the present invention. FIG. 1A shows a block configuration for explaining the connection between a P-type well (PWEL) serving as a substrate of a cell transistor of a memory cell array and a substrate power supply wiring VBB. The array configuration is a one-intersection system as described in FIG. The power supply to the substrate (well region) PWEL0 of the memory cells of the divided memory cell arrays MCA0a and MCA0b divided into two in the bit line direction by the substrate contact column CNTA0m is supplied to the sense amplifier arrays SAA0 and SAA0 existing on both sides of the memory cell array MCA0. The substrate contact lines CNTA0a and CNTA0b provided in the SAA1 and the substrate contact lines CNTA0m existing between the divided memory cell arrays MCA0a and MCA0b are each made from the substrate power supply wiring VBB by a plurality of contacts CONT.
[0025]
Similarly, power is supplied to the substrate (well region) PWEL1 of the memory cell corresponding to the memory cell array MCA1, and the substrate contact columns CNTA1a and CNTA1b and the divided memories provided in the sense amplifier arrays SAA1 and SAA2 existing on both sides of the memory cell array MCA1. This is performed from the substrate power supply wiring VBB by a plurality of contacts CONT provided in each of the substrate contact columns CNTA1m existing between the cell arrays MCA1a and MCA1b.
[0026]
When the length of the divided memory cell array MCA0a in the bit line direction and the length of the divided memory cell array MCA1a in the bit line direction are approximately equal to about one half of the bit line length, the distance between the portion farthest from the power supply unit and the power supply unit is Since the length is shortened, the effect of reducing the substrate resistance is increased. The same applies to the memory cell array MCA1.
[0027]
A cross-sectional structure taken along line A-A 'in FIG. 1A is shown in FIG. The substrate power supply wiring VBB wired in the direction of the word line WL is wired by the second-layer metal wiring M2, once dropped to the first-layer metal wiring M1 through the through hole TC1, and then further well by way of the contact CONT. Connected to region PWEL. At this time, in order to obtain a good ohmic contact, a contact semiconductor layer (active region) having a high concentration such as P + is provided at the connection portion of the well region PWEL. The active region of the memory cell, that is, the source and drain of the MOS transistor is N-type (N +), but the active region CNTA of the power feeding unit is made high-concentration P-type (P +) as described above.
[0028]
Since there is a well region NWEL in the sense amplifier array SAA for forming a P-channel type MOSFET or the like constituting a CMOS latch circuit described later, a deep NWEL (DWEL) is formed using a triple well structure. When arranged below the SAA and the memory cell array MCA, the well region PWEL serving as the substrate of the memory cell is separated on both sides of the sense amplifier array SAA. Therefore, the substrate resistance and the substrate noise can be reduced by making the well region PWEL contact on both sides and the center of the well region NWEL.
[0029]
The substrate power supply wiring VBB is wired on the sub word driver SWDA or the memory cell array MCA using the wiring layer M3 of the same layer as the column selection line YS in the horizontal direction in FIG. 1A, and the main word line in the vertical direction. Wiring is performed on the sense amplifier array SAA, the substrate contact array CNTA, or the array using the wiring layer M2 that is the same layer as the line MWL. It is beneficial to reduce the resistance of the substrate power supply wiring VBB by connecting these vertical and horizontal wirings on the array to form a mesh. In addition, the resistance between the well regions PWEL0 and PWEL1 can be lowered by adopting such a net-like wiring system. Therefore, it is possible to cancel the noise generated on the substrate at the time of sensing the bit line BL at a high speed, reduce the noise, and greatly increase the operation margin of the one-intersection DRAM eye.
[0030]
FIG. 3 is a circuit diagram showing one embodiment of the sense amplifier portion of the dynamic RAM according to the present invention. The sense amplifier SA is composed of a CMOS latch circuit including N-channel type amplification MOSFETs Q5 and Q6 and P-channel type amplification MOSFETs Q7 and Q8 whose gates and drains are cross-connected to form a latch. The sources of N-channel MOSFETs Q5 and Q6 are connected to a common source line CSN. The sources of P-channel MOSFETs Q7 and Q8 are connected to a common source line CSP.
[0031]
Power switch MOSFETs Q3 and Q4 are connected to the common source lines CSN and CSP, respectively. Although not particularly limited, the common potential source line CSN connected to the sources of the N-channel type amplification MOSFETs Q5 and Q6 is connected to the ground potential supply line VSSA by the N-channel type power switch MOSFET Q3 distributed in the sense amplifier region. Is given. The common source line CSP to which the sources of the P-channel type amplification MOSFETs Q7 and Q8 are connected is provided with an N-channel type power MOSFET Q4 to receive the operating voltage VDD.
[0032]
A sense amplifier activation signal SAN is supplied to the gates of the N-channel type power MOSFETs Q3 and Q4. Although not particularly limited, the high level of SAN is a signal of the boosted voltage VPP level. That is, the boosted voltage VPP is boosted above the threshold voltage of the MOSFET Q4 with respect to the power supply voltage VDD. The N-channel MOSFET Q4 is sufficiently turned on, and the potential of the common source line CSP is set to the same level. The power supply voltage VDD can be set.
[0033]
At the input / output node of the sense amplifier SA, an equalize MOSFET Q11 for short-circuiting complementary bit lines BL0T and BL0B, and a precharge (equalize) comprising switch MOSFETs Q9 and Q10 for supplying a half precharge voltage VBLR to the complementary bit lines BL0T and BL0B. A circuit is provided. The gates of these MOSFETs Q9 to Q11 are commonly supplied with a precharge (bit line equalize) signal BLEQ. Although not shown, the driver circuit for generating the precharge signal BLEQ is provided with an inverter circuit in the cross area 18 shown in FIG. In other words, at the start of memory access, the MOSFETs Q9 to Q11 constituting the precharge circuit are switched at high speed through inverter circuits distributed in each cross area 18 prior to the word line selection timing. .
[0034]
A pair of input / output nodes of the sense amplifier SA is connected to the complementary bit lines BL0T and BL0B, and is extended locally along the sense amplifier row via a column (Y) switch circuit composed of MOSFETs Q1 and Q2. Sub) connected to input / output lines SIO, SIO0T and SIO0BB. The gates of the MOSFETs Q1 and Q2 are connected to a column selection line YS, and are turned on when the column selection line YS is set to a selection level (high level), and the input / output nodes of the sense amplifier SA and the local input / output line SIO0T. And SIO0B are connected. Adjacent bit lines are also connected to the local input / output lines SIO1T and SIO1B through the same switch circuit that is switch-controlled by the same column selection line YS.
[0035]
Thereby, the input / output node of the sense amplifier SA is stored in the memory charge of the memory cell connected to the intersection of the selected mat and the word line of the two mats (for example, MAT0 and MAT1) provided therebetween. A minute voltage change with respect to the corresponding half-precharge voltage of the bit line is amplified using the half-precharge voltage of the non-selected bit line on the mat side as a reference voltage, and selected by the column selection line YS. Is transferred to the local input / output lines SIO0T, SIO0B and SIO1T, SIO1B through the column switch circuits (Q1 and Q2) and the like.
[0036]
As shown in FIG. 10, the local input / output lines SIO0T and SIO0B and SIO1T and SIO1B are extended on the sense amplifier array SAA1 arranged in the extension direction of the main word line, and the signal amplified through the sub-amplifier circuit is Through a main input / output line extending in the same direction, it is transmitted to a main amplifier provided in the main word driver MWD section, and, for example, in one memory array divided into four on the memory chip, the subarray is divided. Corresponding to the number, it is output in parallel in units of 16 bits. Each of the memory arrays divided into four is configured as a memory bank as described later.
[0037]
4 and 5 show layout diagrams of one embodiment of the sense amplifier SA shown in FIG. 4 shows a layout of a contact layer TC1 connecting the first and second metal layers M1 and M2, and a layout below the metal layer M1, and FIG. 5 shows a layout above the contact unit TC1. Is shown. 3 to 5, CCP is a cross-coupled P-channel MOSFET (Q7 and Q8), CSD is a common source driver (Q3 and Q4), and CCN is a cross-coupled N-channel MOSFET (Q5 and Q5). Q6), PC is a precharge circuit (Q9 to Q11), YG is a Y gate circuit (Q1 and Q2), which correspond to FIGS. 3 to 5, respectively.
[0038]
As shown in FIG. 5, the plate electrode PL is wired from the second metal wiring layer M2 above the plate electrode PL so as to avoid the region where the contact TC1 to the lower layer than the plate electrode PL passes. In this embodiment, although not particularly limited, the plate electrodes PL0 and PL1 of the mats MAT0 and MAT1 are connected to each other by wiring made of the same conductor layer as the plate electrodes PL0 and PL1. A large number of such PL wirings can be provided in the SAA at a ratio of about one to the pitch of four bit lines BL. Incidentally, when one mat is composed of 1024 bit lines, the number of the PL wirings is as many as 256 in parallel, so that the resistance of the wiring connecting the two plate electrodes provided across the sense amplifier array SAA1 Since the value can be reduced, the complementary noise generated in both plate electrodes PL0 and PL1 can be canceled and greatly reduced.
[0039]
As shown in FIG. 4, the two well regions PWEL corresponding to the memory cell arrays provided on both sides so as to sandwich the sense amplifier array SAA1 are respectively fed by the substrate contact arrays CNTA0b and CNTA1a at both ends of the sense amplifier array SAA1. . As a result, even if the substrate contact columns CNTA0m and CNTA1m as described above are not provided in the central portion of the memory cell array as shown in FIG. 1, the distance between the farthest point from the power supply of the memory array substrate and the substrate power supply portion is reduced. Since the bit line length can be shortened to about one half and the substrate resistance can be reduced, noise generated on the substrate can be greatly reduced.
[0040]
The substrate power supply wiring VBB is not particularly limited, but is wired on the sub word driver column SWDA and the memory cell array MCA using the same wiring layer M3 as the column selection line YS, and in the vertical direction and on the same layer as the main word line MWL. The wiring layer M2 is used to wire the sense amplifier array SAA and the memory cell array. On the memory cell array, these vertical and horizontal wirings are connected to the PWEL via the substrate contact part CNTATC2 provided in the memory cell array of the sense amplifier row, and the resistance value of the power supply line for supplying the substrate bias voltage can be lowered. It is. By adopting such a wiring system, the resistance between the P-type well regions PWEL0 and PWEL1 corresponding to the memory cell arrays MCA0 and MCA1 can be lowered.
[0041]
FIG. 6 shows a configuration diagram of an embodiment of the substrate controller row CNTA0m at the boundary between the divided memory cell arrays MCA0a and MCA0b. 6A shows a layout, and FIG. 6B shows a cross-sectional structure. FIG. 6B shows a cross-sectional structure of the A-A ′ portion in the layout of FIG. In the figure, ACT is an active region of a MOS transistor, SN is a storage node of a memory cell, SNCT is a contact connecting SN and ACT, BLCT is a contact connecting BL and ACT, CP is a capacitor insulating film, and PL is a plate. Show.
[0042]
In this embodiment, the memory cell uses a COB (Capacitor over Bitline) structure. That is, the storage node SN is provided above the bit line BL. As a result, the plate electrode PL can be formed in a single plane without being divided by the connection part BLCT of the bit line BL and the address selection MOSFET in the memory cell array MCA. Can be reduced.
[0043]
In this embodiment, the plate electrode PL has a laminated structure, which can advantageously reduce the sheet resistance value of the plate electrode PL. As an example, when a high dielectric film such as BST or Ta 2 O 5 is used for the capacitor insulating film CP of the storage capacitor, if Ru is used for the lower electrode (storage node) SN and the upper electrode lower layer PL, the capacitance of the storage capacitor CS Can be increased. Since Ru has a lower sheet resistance value than that of conventionally used poly-Si, the resistance value of the plate electrode PL can be lowered. When W is laminated on this structure as the upper layer of the plate electrode PL, the resistance value of the plate electrode PL can be further lowered. In this way, it contributes to the stabilization of the plate voltage that lowers the resistance value of the plate electrode PL itself.
[0044]
In the figure, the first metal wiring layer M1 and the bit line BL are the same wiring layer. The active region of the memory cell is N-type (N +), but the active region of the power feeding unit is P-type (P +). The substrate power supply wiring VBB is wired in the second-layer metal wiring layer M2, once dropped into the first-layer metal wiring layer M1 through the through hole TC1, and further, P + of P + formed in the well region PWEL through the contact CONT Connected to the semiconductor layer. Therefore, although the pitch of the first-layer metal wiring layer M1 is dense in the power feeding portion, in the memory cell layout shown in FIG. 6A, the bit line pitch is about 3F with the minimum processing dimension being F. If one substrate contact is arranged for two or more bit lines, the pitch of the first metal wiring layer M1 can be made 2F or more.
[0045]
When the phase shift method is used for lithography of the first-layer metal wiring M1, the phase in the substrate contact column portion is alternately assigned 0 ° and 180 °, and the adjacent bit lines BL in the memory cell array MCA are adjacent to each other. By assigning the same phase of 0 ° or 180 ° to, resolution of a fine pitch becomes possible. At this time, since the bit line BL pitch is about 3F, exposure can be performed in the same phase.
[0046]
FIG. 7 is a circuit diagram showing one embodiment of a sub word driver of the dynamic RAM according to the present invention. In this embodiment, one main word line MWL is provided for the eight sub word lines WL0 to WL7, and the sub word selection line FX0 is used to select one of the eight sub word lines. -FX7 and FX0B-FX7B are required. In this embodiment, half of the bit lines provided in one subarray are selected by the subword driver array SWDA provided on both sides thereof. For this reason, on one subword driver column shown in the figure, subword selection lines FX1, 2, 5,... For selecting four subword lines which are half of the eight subword lines. 6 and FX1B, 2B, 5B, and 6B are extended.
[0047]
Sub word selection lines FX0 for selecting four sub word lines, the other half of the eight sub word lines, are arranged on a sub word driver column provided on the opposite side across the sub array (not shown). Eight of 3, 4, 7 and FX0B, 3B, 4B, 7B are extended. Sub word drivers corresponding to sub word lines WL1 and WL2, WL2 and WL4, and WL5 and WL6, each of which is a set of two, are alternately provided. The sub word line WL0 is a set of adjacent group (different main word lines) sub word lines WL7, and two sub word drivers are provided.
[0048]
One sub-word driver SWD1 includes a CMOS inverter circuit composed of an N-channel MOSFET Q12 and a P-channel MOSFET Q13, and an N-channel MOSFET Q14 provided in parallel with the N-channel MOSFET Q12. The sources of the N-channel MOSFETs Q12 and Q14 are connected to a power supply line VSSWL corresponding to the non-select level VSS (0 V) of the sub word line. A power supply line VPP for supplying a boosted voltage is provided in the N well region where the P channel type MOSFET Q13 is formed. As described above, in the configuration in which VSS is supplied to the PWEL in which the N-channel MOSFET of the sub word driver SWD1 is formed, the PWEL in which the memory cell is formed is electrically separated using the DWEL.
[0049]
The gates of MOSFETs Q12 and Q13 constituting the CMOS inverter circuit of the sub word driver SWD1 are connected to the main word line MWL in common with the gates of similar MOSFETs of the remaining three sub word drivers. The source of the P-channel MOSFET Q13 constituting the four CMOS inverter circuits is connected to the corresponding sub word selection line FX1, and the gate of the MOSFET Q14 provided in the sub word driver SWD1 is supplied with the sub word selection line FX1B. Is done. The remaining three sub word drivers SWD2, SWD5, and SWD6 are connected to the sub word selection lines FX2 and FX2B, FX5 and FX5B, and FX6 and FX6B, respectively.
[0050]
When the sub word line WL1 is selected, the main word line MWL is set to the low level. Then, the sub word selection line FX1 corresponding to the sub word line WL1 is set to a high level like the boosted voltage VPP. As a result, the P-channel MOSFET Q13 of the sub word driver SWD1 is turned on to transmit the selection level VPP of the sub word selection line FX1 to the sub word line WL1. At this time, in the sub word driver SWD1, the MOSFET Q14 is turned off by the low level of the sub word selection line FX1B.
[0051]
In the other sub word drivers SDW2, SWD5, and SWD6 in which the main word line MWL is selected at the low level, the P-channel MOSFET is turned on, but the high level of the sub word line selection lines FX2B, FX5B, and FX6B The N-channel MOSFET is turned on, and the sub word lines WL2, WL5 and WL6 are set to the non-select level VSS. In the non-selected sub word driver in which the main word line MWL is set to the high level, the N channel MOSFET of the CMOS inverter circuit is turned on by the high level of the main word line MWL, and each sub word line is set to the non-selected level. VSS.
[0052]
In this way, a pair of sub word lines corresponding to two sub arrays are selected by three MOSFETs, so that it is matched with the pitch of the sub word lines WL arranged at high density provided in the one-intersection type memory array (sub array). Thus, a subword driver can be formed, and it is possible to arrange subword drivers adapted to the one-intersection method, which can ideally reduce the cell size by 75% using the same design rule as the two-intersection method.
[0053]
As described above, when the sub word drivers are distributed and arranged in two combinations on both sides of the mat MAT for every two sub word lines WL, the P channel type MOSFETs constituting the two sub word drivers are arranged in the same N type well region. Thus, the N-channel MOSFET can be formed in the same P-type well region. As a result, the sub-word driver can be highly integrated. In the sense amplifier as described above, the two bit lines BL are similarly distributed and arranged in combinations of two on both sides of the mat MAT.
[0054]
FIG. 8 is a block diagram showing another embodiment of the memory cell array portion of the DRAM according to the present invention. In the figure, the connection between a P-type well (PWEL) serving as a substrate of a memory cell transistor and a substrate power supply wiring VBB is described. The layout of each block is the layout layout of each actual circuit on a semiconductor substrate. It is drawn corresponding to. The same applies to FIG. 1A.
[0055]
The memory cell array configuration is the one-intersection system of FIG. Power is supplied to the well region PWEL0, which is a substrate of memory cells of the divided memory cell arrays MCA0a, MCA0b, and MCA0c. The substrate contact line CNTA0m1 existing between the cell arrays MCA0a and MCA0b and the substrate contact line CNTA0m2 existing between the divided memory cell arrays MCA0b and MCA0c are performed from the substrate power supply wiring VBB.
[0056]
This embodiment is different from the embodiment of FIG. 1 in that two substrate contact columns are provided in a memory cell array (or memory mat). When the length of the divided memory cell arrays MCA0a, MCA0b, and MCA0c in the bit line direction is substantially equal to about one third of the bit line length, the distance between the portion farthest from the power supply unit of the substrate bias voltage and the power supply unit is the bit line length. Therefore, the effect of reducing substrate resistance can be increased. The same applies to the other memory cell array (memory mat) MCA1 provided with the sense amplifier array SAA1 interposed therebetween.
[0057]
FIG. 9 is a timing chart for explaining an example of the operation of the DRAM according to the present invention. A row address for row (ROW) a is input from the address ADD terminal, and an activation command ACT is input from the control terminal CMD. The precharge signal PC is deactivated in response to the input of the activation command ACT, the precharge of the bit line BL is completed, and the word line WLa is activated in response to the input of the row address. Due to the activation of the word line WLa, the potential of the bit line of the selected memory mat is a minute voltage corresponding to the precharge voltage of the bit line of the non-selected memory mat corresponding to the storage charge of the selected memory cell. Can be changed.
[0058]
After a read signal from the memory cell is generated on the bit line BL, the sense amplifier activation signal SAN / SAP is driven and amplified by the sense amplifier. In this state, information of a plurality of memory cells corresponding to the word line WLa is held in the plurality of sense amplifiers provided in the sense amplifier column, and when a read command READ is input to the column (COL) x. The column selection signal YSx is activated, and the data in the row a and the column x is read from the sense amplifier to the input / output terminal DQ via the input / output line MIO.
[0059]
FIG. 11 is an overall block diagram of an embodiment of a DRAM to which the present invention is applied. The DRAM of this embodiment is directed to a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory; hereinafter simply referred to as DDR SDRAM). Although the DDR SDRAM of this embodiment is not particularly limited, four memory arrays 200A to 200D are provided corresponding to four memory banks. The memory arrays 200A to 200D respectively corresponding to the four memory banks 0 to 3 are provided with dynamic memory cells arranged in a matrix, and according to the figure, the selection terminals of the memory cells arranged in the same column are the word for each column. Data input / output terminals of memory cells coupled to a line (not shown) and arranged in the same row are coupled to a complementary data line (not shown) for each row.
[0060]
One word line (not shown) of the memory array 200A is driven to a selected level according to the decoding result of the row address signal by the row decoder (Row DEC) 201A. Complementary data lines (not shown) of the memory array 200A are coupled to I / O lines of a sense amplifier (Sense AMP) 202A and a column selection circuit (Column DEC) 203A. The sense amplifier 202A is an amplifier circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from the memory cell. In this case, the column selection circuit 203A includes a switch circuit for selecting the complementary data lines individually and conducting them to the complementary I / O lines. The column switch circuit is selectively operated according to the decoding result of the column address signal by the column decoder 203A.
[0061]
Similarly, the memory arrays 200B to 200D are also provided with row decoders 201B to 201D, sense amplifiers 203B to 203D, and column selection circuits 203B to 203D. The complementary I / O line is shared by each memory bank, and is connected to an output terminal of a data input circuit (Din Buffer) 210 having a write buffer and an input terminal of a data output circuit (Dout Buffer) 211 including a main amplifier. Connected. The terminal DQ is not particularly limited, but is a data input / output terminal that inputs or outputs 16-bit data D0 to D15. A DQS buffer (DQS buffer) 215 forms a data strobe signal of data output from the terminal DQ during a read operation.
[0062]
Address signals A0 to A14 supplied from address input terminals are temporarily held in an address buffer 204, and among the address signals input in time series, a row address signal is a row address buffer (Row Address buffer). The column address signal is held in a column address buffer 206. A refresh counter 208 generates a row address at the time of automatic refresh (automatic refresh) and self refresh (self refresh).
[0063]
For example, when having a storage capacity of 256 Mbits, an address terminal for inputting an address signal A14 is provided as a column address signal when memory access is performed in units of 2 bits. In the x4 bit configuration, the address signal A11 is valid, in the x8 bit configuration, the address signal A10 is valid, and in the x16 bit configuration, the address signal A9 is valid. In the case of a storage capacity of 64 Mbits, the address signal A10 is valid in the x4 bit configuration, the address signal A9 is valid in the x8 bit configuration, and in the x16 bit configuration as shown in the figure. Up to the address signal A8 is valid.
[0064]
The output of the column address buffer 206 is supplied as preset data of a column address counter 207, and the column address counter 207 is a column as the preset data in a burst mode specified by a command to be described later. An address signal or a value obtained by sequentially incrementing the column address signal is output to the column decoders 203A to 203D.
[0065]
A mode register (Mode Register) 213 holds various operation mode information. Of the row decoders 201A to 201D, only those corresponding to the bank designated by the bank select circuit 212 operate, and the word line is selected. The control circuit (Control Logic) 209 is not particularly limited, but includes a clock signal CLK, / CLK (the symbol / means that a signal to which this is attached is a low enable signal), a clock enable signal CKE, and a chip select signal. External control signals such as / CS, column address strobe signal / CAS, row address strobe signal / RAS, and write enable signal / WE, and address signals via / DM and DQS and mode register 213 are supplied. An internal timing signal for controlling the operation mode of the DDR SDRAM and the operation of the circuit block is formed based on a change in signal level, timing, and the like, and each has an input buffer corresponding to the signal.
[0066]
Clock signals CLK and / CLK are input to DLL circuit 214 via a clock buffer, and an internal clock is generated. The internal clock is not particularly limited, but is used as an input signal for the data output circuit 211 and the DQS buffer 215. The clock signal via the clock buffer is supplied to the data input circuit 210 and a clock terminal supplied to the column address counter 207.
[0067]
Other external input signals are made significant in synchronization with the rising edge of the internal clock signal. The chip select signal / CS instructs the start of the command input cycle according to its low level. When the chip select signal / CS is at a high level (chip non-selected state) or other inputs are meaningless. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state. Each of the signals / RAS, / CAS, / WE has a function different from that of a corresponding signal in a normal DRAM, and is a significant signal when defining a command cycle to be described later.
[0068]
The clock enable signal CKE is a signal that indicates the validity of the next clock signal. The rising edge of the next clock signal CLK is valid if the signal CKE is high level, and invalid when the signal CKE is low level. In the read mode, when the external control signal / OE for controlling the output enable for the data output circuit 211 is provided, the signal / OE is also supplied to the control circuit 209. When the signal is at a high level, for example. The data output circuit 211 is set to a high output impedance state.
[0069]
The row address signal is defined by the levels of A0 to A11 in a later-described row address strobe / bank active command cycle synchronized with the rising edge of the clock signal CLK (internal clock signal).
[0070]
The address signals A12 and A13 are regarded as bank selection signals in the row address strobe / bank active command cycle. That is, one of the four memory banks 0 to 3 is selected by a combination of A12 and A13. The selection control of the memory bank is not particularly limited, but only the row decoder on the selected memory bank side is activated, all the column switch circuits on the non-selected memory bank side are not selected, the data input circuit 210 and the data only on the selected memory bank side This can be done by processing such as connection to an output circuit.
[0071]
When the column address signal is 256 M bits and × 16 bits as described above, a read or write command synchronized with the rising edge of the clock signal CLK (internal clock) (column address / read command, column address described later) Write command) Defined by the levels of A0 to A9 in the cycle. The column address thus defined is used as a burst access start address.
[0072]
Next, main operation modes of the SDRAM indicated by the command will be described.
(1) Mode register set command (Mo)
This is a command for setting the mode register 30, and is designated by / CS, / RAS, / CAS, / WE = low level, and data to be set (register set data) is given via A0 to A11. . The register set data is not particularly limited, but is set to burst length, CAS latency, write mode, or the like. Although not particularly limited, the settable burst length is 2, 4, 8, the settable CAS latency is 2,2.5, and the settable write mode is burst write and single write. .
[0073]
The CAS latency indicates how many cycles of the internal clock signal are spent from the fall of / CAS to the output operation of the output buffer 211 in a read operation instructed by a column address read command to be described later. . An internal operation time for reading data is required until the read data is determined, and is used for setting it according to the use frequency of the internal clock signal. In other words, the CAS latency is set to a relatively large value when an internal clock signal with a high frequency is used, and the CAS latency is set to a relatively small value when an internal clock signal with a low frequency is used. To do.
[0074]
(2) Row address strobe / bank active command (Ac)
This is a command for validating the instruction of the row address strobe and the selection of the memory bank by A12 and A13, and is indicated by / CS, / RAS = low level, / CAS, / WE = high level, and at this time, A0 to A9. The address supplied to A is taken as a row address signal, and the signals supplied to A12 and A13 are taken as memory bank selection signals. The capturing operation is performed in synchronization with the rising edge of the internal clock signal as described above. For example, when the command is designated, the word line in the memory bank designated by the command is selected, and the memory cells connected to the word line are respectively conducted to the corresponding complementary data lines.
[0075]
(3) Column address / read command (Re)
This command is a command necessary for starting a burst read operation, and a command for giving an instruction of a column address strobe, which is indicated by / CS, / CAS = low level, / RAS, / WE = high level, At this time, the column address supplied to A0 to A9 (in the case of x16 bit configuration) is taken in as a column address signal. The column address signal thus fetched is supplied to the column address counter 207 as a burst start address.
[0076]
In the burst read operation instructed thereby, the memory bank and the word line in the row address strobe / bank active command cycle are selected before that, and the memory cell of the selected word line receives the internal clock signal. Are sequentially selected according to the address signal output from the column address counter 207 and read continuously. The number of data continuously read out is the number specified by the burst length. Data read from the output buffer 211 is started after waiting for the number of cycles of the internal clock signal defined by the CAS latency.
[0077]
(4) Column address / write command (Wr)
This command is instructed by / CS, / CAS, / WE = low level, / RAS = high level, and at this time, the address supplied to A0 to A9 is taken in as a column address signal. The column address signal thus fetched is supplied to the column address counter 207 as a burst start address in burst write. The procedure of the burst write operation instructed thereby is performed in the same manner as the burst read operation. However, there is no CAS latency in the write operation, and the capture of the write data is started one clock after the column address / write command cycle.
[0078]
(5) Precharge command (Pr)
This is a command for starting a precharge operation for the memory bank selected by A12 and A13, and is designated by / CS, / RAS, / WE = low level and / CAS = high level.
[0079]
(6) Auto refresh command
This command is required to start auto-refresh, and is designated by / CS, / RAS, / CAS = low level and / WE, CKE = high level.
[0080]
(7) No operation command (Nop)
This is a command for instructing that no substantial operation is performed, and is designated by / CS = low level, / RAS, / CAS, / WE high level.
[0081]
In a DDR SDRAM, when a burst operation is performed in one memory bank, if another memory bank is specified in the middle and a row address strobe / bank active command is supplied, The row address operation in another memory bank can be performed without affecting the operation in the memory bank.
[0082]
Therefore, for example, when data D0 to D15 do not collide at a 16-bit data input / output terminal, during execution of a command that has not been processed, the command being executed is different from the memory bank to be processed. It is possible to start the internal operation in advance by issuing a precharge command and a row address strobe / bank active command.
[0083]
The detailed read operation of the DDR SDRAM is as follows. Chip select / CS, / RAS, / CAS, and write enable / WE signals are input in synchronization with the CLK signal. At the same time as / RAS = 0, a row address and a bank selection signal are input and held in the row address buffer 205 and the bank select circuit 212, respectively. The row decoder 210 of the bank designated by the bank select circuit 212 decodes the row address signal, and the data of the entire row is output from the memory cell array 200 as a minute signal. The output minute signal is amplified and held by the sense amplifier 202. The specified bank becomes active.
[0084]
After 3 CLK from the row address input, a column address and a bank selection signal are input simultaneously with CAS = 0, and are held in the column address buffer 206 and the bank select circuit 212, respectively. If the designated bank is active, the held column address is output from the column address counter 207, and the column decoder 203 selects a column. The selected data is output from the sense amplifier 202. The data output at this time is two sets (8 bits in the x4 bit configuration, 32 bits in the x16 bit configuration).
[0085]
The data output from the sense amplifier 202 is output from the data output circuit 211 to the outside of the chip via the data bus DataBus. The output timing is synchronized with both rising and falling edges of QCLK output from the DLL 214. At this time, as described above, the two sets of data are converted from parallel to serial to become one set × 2 data. Simultaneously with the data output, a data strobe signal DQS is output from the DQS buffer 215. When the burst length stored in the mode register 213 is 4 or more, the column address counter 207 automatically increments the address and reads the next column data.
[0086]
The role of the DLL 214 is to generate an operation clock for the data output circuit 211 and the DQS buffer 215. The data output circuit 211 and the DQS buffer 215 take time until the data signal and the data strobe signal are actually output after the internal clock signal generated by the DLL 214 is input. For this reason, the phase of the internal clock signal is advanced from that of the external CLK by using an appropriate replica circuit, so that the phase of the data signal or the data strobe signal is matched with that of the external clock CLK. Therefore, the DQS buffer is set to an output high impedance state during a time other than the data output operation as described above.
[0087]
During the write operation, since the DQS buffer 215 of the DDR SDRAM is in an output high impedance state, a data strobe signal DQS is input to the terminal DQS from a data processor such as a macro processor, and the terminal DQ is synchronized with it. Written data is input. The data input circuit 210 receives the write data input from the terminal DQ serially as described above by the clock signal formed based on the data strobe signal input from the terminal DQS, and synchronizes with the clock signal CLK. Then, the data is converted into parallel data, transmitted to the selected memory bank via the data bus DataBus, and written to the selected memory cell in the memory bank.
[0088]
By applying the present invention to the DDR SDRAM as described above, a semiconductor memory capable of high-speed writing and reading can be configured while reducing the size of the memory chip.
[0089]
The effects obtained from the above embodiment are as follows.
(1) A plurality of dynamic memory cells comprising MOSFETs and capacitors, a plurality of word lines respectively connected to the selection terminals of the plurality of memory cells, and input / output terminals of the plurality of memory cells A plurality of complementary bit line pairs connected to each other and arranged to extend in opposite directions around one end, and arranged on one end side of the complementary bit line pair, the voltage difference between the complementary bit lines is determined. A plurality of memory mats each including a plurality of sense amplifier arrays each including a plurality of latch circuits to be amplified are provided, and a bias voltage is supplied to a semiconductor region in which the memory cells are formed in all the plurality of sense amplifier arrays. By providing a plurality of contact portions, a bias voltage is supplied from both sides of each memory mat. Substrate bias voltage is an advantage of being able to improve the operating margin is stabilized.
[0090]
(2) In addition to the above, a pre-charge that extends a complementary input / output line along the sense amplifier row and supplies an intermediate voltage of the operation voltage of the sense amplifier to the complementary bit line pair is supplied to the sense amplifier row. A switching MOSFET provided between the complementary bit line pair and the complementary input / output line, the MOSFET having the same conductivity type as that of the memory cell, and receiving the Y selection signal at the gate and the circuit; What is formed in the amplifier row can be provided with a contact portion for supplying a bias voltage without forming a special semiconductor region by forming it in the same semiconductor region as the semiconductor region in which the memory cell is formed. An effect is obtained.
[0091]
(3) In addition to the above, a semiconductor layer for supplying the bias voltage to a semiconductor region in which the memory cells are formed at one or more locations so that the memory mat is equally divided into bit lines in the extending direction of the bit lines Is provided in parallel with the sense amplifier row, and a plurality of contact portions for supplying the bias voltage to the semiconductor layer are provided, so that the distance between the portion farthest from the power supply portion and the power supply portion can be further shortened. Therefore, the effect that the operation margin can be greatly improved can be obtained.
[0092]
(4) In addition to the above, the word line is composed of a main word line and a sub word line divided into a plurality in the extending direction of the main word line, and a sub word driver corresponding to the divided sub word line A plurality of such sub word lines are assigned to the main word line, and one sub word line is selected by a signal of the main word line and a sub word selection line, and is surrounded by the sense amplifier row and the sub word driver. By providing one memory mat corresponding to the area, it is possible to obtain an effect that it is possible to secure a signal amount necessary for a high-speed memory cell selection operation and a sense amplifier operation while increasing the storage capacity.
[0093]
(5) In addition to the above, the voltage wiring for supplying the bias voltage is extended along each of the sense amplifier row, the sub word driver, and the semiconductor layer, and is connected to each other at each intersection to form a mesh. As a result, the resistance value in the power supply wiring can be reduced, and the bias voltage applied to the substrate can be stabilized.
[0094]
The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the substrate (P-type well) on which a pair of memory cell arrays provided between the sense amplifier rows is formed has a slit structure that appropriately penetrates the sense amplifier rows and is also connected to each other by such semiconductor regions. You may add the structure to do. The input / output interface of the dynamic RAM is not limited to the DDR SDRAM as described above, and various embodiments such as an SDRAM can be adopted. The present invention can be widely used in a single intersection type dynamic RAM.
[0095]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. A plurality of dynamic memory cells comprising MOSFETs and capacitors, a plurality of word lines connected to the selection terminals of the plurality of memory cells, and a plurality of input / output terminals of the memory cells, respectively. A plurality of complementary bit line pairs arranged so as to extend in opposite directions with respect to one end, and arranged on one end side of the complementary bit line pair to amplify a voltage difference between the complementary bit lines, respectively. A plurality of memory mats including a plurality of sense amplifier arrays each including a plurality of latch circuits, and a contact portion for supplying a bias voltage to a semiconductor region in which the memory cells are formed in all of the plurality of sense amplifier arrays. By providing a plurality, a bias voltage is supplied from both sides of each memory mat. Ass voltage it is possible to improve the operating margin is stabilized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a one-intersection DRAM array according to the present invention.
FIG. 2 is a circuit diagram showing one embodiment of a one-intersection DRAM array according to the present invention.
FIG. 3 is a circuit diagram showing one embodiment of a sense amplifier section of a dynamic RAM according to the present invention.
FIG. 4 is a layout diagram of a lower layer showing an embodiment of a sense amplifier portion of a dynamic RAM according to the present invention.
FIG. 5 is a layout diagram of an upper layer showing an embodiment of a sense amplifier portion of a dynamic RAM according to the present invention.
6 is a partial cross-sectional structure diagram in FIG. 5;
FIG. 7 is a circuit diagram showing one embodiment of a dynamic RAM sub-word driver according to the present invention;
FIG. 8 is a block diagram showing another embodiment of the memory cell array portion of the DRAM according to the present invention.
FIG. 9 is a timing chart showing an example of the operation of the DRAM according to the present invention.
FIG. 10 is a schematic layout diagram showing one embodiment of a dynamic RAM to which the present invention is applied.
FIG. 11 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.
FIG. 12 is an explanatory diagram of a one-intersection type memory array studied by the inventors of the present application and noise generated in the memory array;
[Explanation of symbols]
SAA1-3 ... sense amplifier array, SWDA ... subword driver array, MCA0-2 ... memory cell array (memory mat), PWEL0,1 ... P-type well region (substrate), CNTA0-1 ... contact array, MCA0a-MCA1b ... divided array , SA ... sense amplifier, SWD ... sub word driver, PL ... plate electrode, PLSA ... wiring, MWL ... main word line, WL ... sub word line, BL ... bit line, ACT ... active region, TC1, TC2 ... through hole, SN ... Storage node, CONT ... Contact part, CP ... Capacity insulating film, BLCT ... Contact part, M1 to M3 ... Metal wiring layer, FX0 to FX7B ... Subword selection line,
Q1-Q11 ... MOSFET,
DESCRIPTION OF SYMBOLS 10 ... Memory chip, 11 ... Array control circuit, 12 ... Main word driver, 13 ... Column decoder, 15 ... Subarray (memory mat), 16 ... Sense amplifier, 17 ... Subword driver, 18 ... Crossing area,
200A to D ... Memory array, 201A to D ... Row decoder, 202A to D ... Sense amplifier, 203A to D ... Column decoder, 204 ... Address buffer, 205 ... Row address buffer, 206 ... Column address buffer, 207 ... Column address counter 208 ... Refresh counter 209 ... Control circuit 210 ... Data input circuit 211 ... Data output circuit 212 ... Bank select circuit 213 ... Mode register 214 ... DLL 214 ... DQS buffer

Claims (4)

A dynamic memory cell comprising a MOSFET and a capacitor, wherein the gate of the MOSFET is a selection terminal, one source and drain are input / output terminals, and the other source and drain are connected to the storage node of the capacitor. Multiple
A plurality of word lines respectively connected to the selection terminals of the plurality of dynamic type memory cells;
A plurality of complementary bit line pairs connected to the input / output terminals of the plurality of dynamic memory cells, and arranged to extend in opposite directions around one end, and one end of the complementary bit line pair A plurality of memory mats including a plurality of sense amplifier arrays each including a plurality of latch circuits disposed on the side and amplifying the voltage difference between the complementary bit lines,
In the memory mat, a semiconductor layer for supplying a bias voltage to a semiconductor region in which the memory cell is formed is provided in parallel with the sense amplifier row at one or a plurality of locations where the bit line is equally divided in the extending direction of the bit line. A dynamic RAM comprising a plurality of contact portions for supplying the bias voltage to the semiconductor layer . In claim 1,
A complementary input / output line extending along the sense amplifier array;
The sense amplifier row includes a precharge circuit that supplies an intermediate voltage of the operation voltage of the sense amplifier to the complementary bit line pair, a Y selection signal received at a gate, and the complementary bit line pair and the complementary input / output line. Including a switch MOSFET provided therebetween,
A MOSFET of the same conductivity type as the MOSFET of the memory cell, which is formed in the sense amplifier row, is formed in the same semiconductor region as the semiconductor region in which the memory cell is formed. RAM. In either claim 1 or claim 2 ,
The word line is composed of a main word line and a sub word line divided into a plurality in the extending direction of the main word line,
A sub word driver is provided corresponding to the divided sub word line,
A plurality of the sub word lines are assigned to the main word line,
The sub word driver selects one of the plurality of sub word lines in response to the signal of the main word line and the signal of the sub word selection line,
A dynamic RAM characterized in that a memory cell corresponding to one memory mat is formed in an area surrounded by the sense amplifier array and the sub word driver. In claim 3 ,
The voltage wiring for supplying the bias voltage is extended along each of the sense amplifier row, the sub-word driver, and the semiconductor layer, and has a mesh shape connected to each other at each intersection. A characteristic dynamic RAM.

Images