JP2010211892A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device that achieves a high-speed access operation. <P>SOLUTION: In the semiconductor memory device composed of a memory cell array including a plurality of regular memory cells and a plurality of sense amplifier circuits, the memory cell array has regular memory cells MC to be used for write and read operation of desired data and a smoothing capacitor (specifically, dummy cells DMC to be used for smoothing capacitor) for reducing power source noise. A word line of the dummy cell DMC is activated at the same timing as that of a word line of the regular memory cell MC. A pre-charge level of a data line is VDD, a part of the dummy cells DMC may be used as a memory cell for generating a reference level. In this case, word lines of the regular memory cell MC is inactivated prior to the word lines of the dummy cell DMC. Further, a circuit for short-circuiting adjacent data lines may be added. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly, to a technology effective when applied to a high-speed, highly integrated semiconductor memory device and a differential amplification operation portion of a semiconductor device in which a logic circuit and a semiconductor memory device are integrated.

  A large number of dynamic random access memories (hereinafter referred to as DRAMs), which is one of semiconductor memory devices, are mounted on various electronic devices that we use daily. In addition, with recent needs for lower power consumption and higher performance of equipment, there is a strong demand for higher performance such as lower power consumption, higher speed, and larger capacity in DRAMs.

  One of the most effective means for realizing a high-performance DRAM is miniaturization of memory cells. The memory cell can be made smaller by miniaturization. As a result, the length of the word line and data line connected to the memory cell is shortened. That is, since the parasitic capacitance of the word line and the data line can be reduced, low voltage operation is possible, and low power consumption can be realized. Further, since the memory cell becomes small, the capacity of the memory can be increased, and the performance of the device can be improved. Thus, miniaturization greatly contributes to higher performance of DRAM.

  However, as the miniaturization progresses to 50 nm and 32 nm nodes, various side effects appear in addition to the effect of higher performance as described above. The side effect is an increase in the variation of the threshold voltage of the transistor due to miniaturization. This variation in threshold voltage causes malfunction of the DRAM, so it is desirable to keep it as small as possible. In particular, the variation in the threshold voltage difference between the pair transistors of the sense amplifier circuit becomes a noise source in a sense operation that amplifies a minute signal, and causes a read error. The sense amplifier circuit also has the following side effects as the voltage of the DRAM array is lowered. That is, the driving power of the sense amplifier circuit is reduced as the voltage is lowered.

  Hereinafter, the reason why the driving force is reduced will be described. In DRAM, the half precharge method is common. That is, the applied voltage of the sense amplifier circuit is VDD / 2 which is 1/2 of the array voltage VDD. For this reason, when the voltage is lowered, the driving power (the voltage applied between the gate and the source) of the sense amplifier circuit is greatly reduced. In particular, when a threshold voltage difference occurs between the pair transistors of the sense amplifier circuit, the sense operation speed is significantly degraded. That is, the sense time for amplifying a minute read signal amount becomes longer, and the access speed of the DRAM becomes slower. As described above, there are problems such as a read malfunction due to miniaturization and low voltage, and a slow access speed.

  As a method for solving the above problem, there is a VDD precharge method in which the precharge level of the data line is changed from VDD / 2 to VDD. When VDD is precharged, the effective variation of the threshold voltage, which is one of noise sources in the sensing operation, can be reduced. The reason is as follows. In the case of VDD precharge, discharging one of the data line pair to the ground level corresponds to the sense operation. That is, the data line is sensed (discharged) by the NMOS transistor. In other words, the threshold voltage variation to be considered in the sense amplifier circuit is only the NMOS pair transistor that mainly contributes to the sensing operation.

  On the other hand, in the conventional half precharge method, since both the NMOS transistor and the PMOS transistor drive the data line pair to the ground level and the VDD level, respectively, the threshold voltage variation to be considered in the sensing operation contributes to the sensing operation. It becomes both an NMOS transistor and a PMOS transistor. That is, the effective variation of the threshold voltage that becomes a noise source of the sense amplifier circuit is larger in the half precharge method and smaller in the VDD precharge. That is, since the variation in effective threshold voltage is reduced, a read malfunction can be prevented. When the VDD precharge method is used, the voltage applied between the gate and source of the sense amplifier circuit, that is, the NMOS transistor, becomes large. As a result, driving force is improved and high speed sensing operation can be expected.

  By adopting the VDD precharge method in this way, there is a possibility that problems due to miniaturization and low voltage can be prevented or eliminated. However, when the VDD precharge method is used, the following new problem arises. That is an increase in array noise generated by the read operation of the memory cell data. Here, the array noise is a transient fluctuation of various power supply voltage levels supplied and connected to the DRAM array. This array noise becomes a noise source of the sensing operation as well as the variation in threshold voltage. Therefore, as described above, this increasing array noise may cancel the effect that the sensing operation is led by the NMOS and the effective threshold voltage can be reduced. In other words, an increase in array noise due to VDD precharge may cause a malfunction in the read operation, which in turn may reduce the chip yield.

  The reason why the array noise, that is, the transient fluctuation of the power supply voltage in the VDD precharge method is larger than that in the half precharge method is as follows. In the VDD precharge, when the VSS level is charged in the storage node, the storage node rises from the VSS level to the level of (A), VDD−Vsig0 (VDD · CS / (CS + CD)). When the storage node rises, the voltage level of the plate electrode, which is the counter electrode of the memory cell capacitor, rises transiently. On the other hand, in the conventional half precharge method, when the storage node is charged with the VSS level, the storage node is changed from the VSS level to the level (B), VDD / 2−Vsig1 (VDD / 2 · CS / (CS + CD)), Rise to the level. The level (A) is clearly larger at the levels (A) and (B).

  If the VDD level is charged in the storage node, the fluctuation of the storage node is small during VDD precharge, and the transient fluctuation of the power supply voltage level when the word line is activated is small. However, the worst case is when the storage node is charged with VSS. In this case, the VDD precharge has a larger fluctuation. In addition, when a small amount of read signal read out to the data line is amplified or when the amplified data line pair is precharged, the VDD precharge is more preferable than the conventional half precharge. The level fluctuation is large. That is, since a large amount of charge is required for charging / discharging, the transient fluctuation of the power supply voltage level generally increases. In other words, since the VDD precharge has a larger array noise than the conventional half precharge, there is a high possibility that a read malfunction occurs and the yield of the chip may be reduced.

  As an example of recent attempts to solve the problem of such array noise (transient fluctuation of power supply voltage), for example, Patent Document 1 discloses an example in which a memory cell array is used as a smoothing capacitor. In Patent Document 1, the ground voltage VSS is applied to the plate electrode side of the memory cell, and the power supply voltage VDD is applied to the bit line side. A boosted power supply VPP is applied to the word lines of the memory cell array. In this way, the memory cell capacity can be used as a smoothing capacity for the power supply voltage VDD and the ground voltage VSS. As a result, power noise when amplifying the data line pair is suppressed, and high-speed sensing operation can be expected. For example, Patent Document 2 discloses an example in which a dummy cell is separately provided and the word line is activated at the time of rewriting to reduce the power supply noise of the plate electrode. This may prevent a read malfunction immediately after rewriting.

JP 2003-332532 A JP 2002-184173 A

  However, as a result of examination of the inventors of Patent Document 1 and Patent Document 2, it has been found that there are the following problems.

  In Patent Document 1, as shown in FIG. 6 of Patent Document 1, it is necessary to make the data line length for operating the memory array equal to the data line length of the memory cell array used as a smoothing capacitor. The reason for this is to balance the load capacity of the sense amplifier circuit and to perform stable reading and amplification operations. Therefore, there is a problem that the data line length of the memory array portion used as the smoothing capacitor becomes long and the chip area becomes large.

  Further, in Patent Document 2, plate noise generated at the time of rewriting can be reduced. However, since the data line of the dummy cell shares the data line of a normal memory cell, it can be used between various power sources (for example, VDD power source and VSS power source). It cannot be used for smooth capacity. That is, there is a problem that power supply noise generated by the sensing operation cannot be reduced.

  Therefore, an object of the present invention is to reduce array noise related to a read operation and realize a high-speed access operation.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, a typical outline is a semiconductor memory device including a memory cell array including a plurality of normal memory cells and a plurality of sense amplifier circuits. In the memory cell array, normal memory cells used for writing and reading operations of desired data are stored. And a smoothing capacitor for reducing power supply noise (specifically, a memory cell used for the smoothing capacitor).

  The word line of the memory cell used for the smoothing capacitor is activated at the same timing as the word line of the normal memory cell.

  Further, the precharge level of the data line may be set to VDD, and a part of the memory cell used as a smoothing capacitor may be used as a memory cell for generating a reference level. In this case, the deactivation of the word line of the normal memory cell is performed prior to the deactivation of the word line of the memory cell having the smoothing capacity. This can reduce array noise while minimizing the increase in area.

  Further, a circuit for short-circuiting adjacent data lines may be added. In this case, since the data lines on which the reference level is generated are short-circuited, the reference signal level can be stabilized even when the array noise increases.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, the effect obtained by the representative one can realize a high-speed access operation.

1 is a diagram illustrating an example of a sense amplifier circuit and a memory cell array of a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating an example of operation waveforms of the sense amplifier circuit of FIG. 1. FIG. 6 is a diagram showing another example of operation waveforms of the sense amplifier circuit of FIG. 1. FIG. 2 is a diagram illustrating an example of a planar layout of a sense amplifier circuit and a memory cell array in FIG. 1. FIG. 2 is a diagram showing an example of a bird's eye view of the sense amplifier circuit and the memory cell array in FIG. 1. In the sense amplifier circuit of FIG. 1, it is a figure which shows Embodiment 2 which added the pre-charge power supply (VDL) in addition to the common source (CSN) power supply voltage which adds a smoothing capacitor. FIG. 2 is a diagram illustrating an example in which a dummy cell power supply level (VDLP) is added to a common source (CSN) power supply voltage to which a smoothing capacitor is added in the sense amplifier circuit of FIG. 1. FIG. 2 is a diagram illustrating an example in which a common source (CSP) power supply (VDL) is added to a common source (CSN) power supply voltage to which a smoothing capacitor is added in the sense amplifier circuit of FIG. 1. In the sense amplifier circuit of FIG. 1, it is a figure which shows Embodiment 3 which set the precharge voltage of the data line to the power supply (VDL / 2). FIG. 10 is a diagram illustrating an example in which a common source (CSP) power supply (VDL) is added to a common source (CSN) power supply voltage to which a smoothing capacitor is added in the sense amplifier circuit of FIG. 9. FIG. 10 is a diagram illustrating an example in which the common source (CSN) power supply voltage to which a smoothing capacitor is added is changed from the ground level (VSSA) to a negative voltage (VBBSA) in the sense amplifier circuit of FIG. 9. In the sense amplifier circuit of FIG. 9, the common source (CSN) power supply voltage for adding a smoothing capacitor is changed from the ground level (VSSA) to the negative voltage (VBBSA), and is also smoothed to the common source (CSP) power supply (VDL). It is a figure which shows the example which added the capacity | capacitance. In the sense amplifier circuit of FIG. 1, when outputting a read signal, it is a figure which shows Embodiment 4 which activated the short circuit signal and electrically connected several adjacent data lines. It is a figure which shows an example of the operation waveform of the sense amplifier circuit of FIG. It is a figure which shows an example of a structure which combined the overdrive precharge circuit with the sense amplifier circuit of FIG. FIG. 16 is a diagram illustrating an example of operation waveforms of the sense amplifier circuit of FIG. 15. In the sense amplifier circuit of FIG. 1, it is a figure which shows the example which added the control signal which short-circuits a data line, without using a part of dummy cell as a smoothing capacitor. FIG. 18 is a diagram illustrating an example of a connection relationship between a short circuit signal and a data line in the sense amplifier circuit of FIG. 17. FIG. 2 is a diagram illustrating an example of a configuration of a word line of a normal memory cell, a sub word line of a dummy cell, a sub word control line, and a sub word selection line in the sense amplifier circuit of FIG. FIG. 19 is a diagram illustrating an example of the sub-word driver implemented. FIG. 19 is a diagram illustrating an example of a cross area implemented. It is a figure which shows an example of the block of the whole DRAM chip to which the sense amplifier circuit of this invention is applied. It is a figure which shows an example of a structure of the control circuit part and memory bank of a DRAM chip to which the sense amplifier circuit of this invention is applied. FIG. 24 is a diagram illustrating an example of a sense amplifier, sub-array, and cross-area circuit applied to FIG. 23. FIG. 25 is a diagram showing an example ((a) (b) (c) (d)) of a memory cell layout in the subarray applied to FIG. 24. FIG. 25 is a diagram illustrating an example of a cross section of a subarray and a sense amplifier array applied to FIG. 24.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. About this code | symbol, when the provision object corresponds to the same member like a signal line and a signal name, a power supply, a voltage, a level, etc., the same code | symbol may be attached | subjected.

  The transistors constituting each block shown in this embodiment are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by an integrated circuit technology such as a known CMOS (complementary MOS transistor). It is formed. That is, after the step of forming the well, the element isolation region, and the oxide film, the step includes forming the gate electrode and the first and second semiconductor regions for forming the source / drain regions.

  The circuit symbol of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) indicates that the gate is not circled, or the substrate that does not have an arrow represents an N-type MOSFET (NMOS), and the gate is circled or Differentiated from P-type MOSFETs (PMOS) with arrows. Hereinafter, the MOSFET is simply referred to as a MOS or a MOS transistor.

  Note that in this specification, the MOSFET is not limited to a field effect transistor including an oxide film provided between a metal gate and a semiconductor layer, but a MISFET (Metal Insulator Semiconductor Field Transistor) including an insulating film. And so on.

(Embodiment 1)
A semiconductor memory device according to the first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 shows a sense amplifier circuit SA according to the first embodiment of the present invention (SA7 is shown as an example), a plurality of memory cells (normal memory cells) MC connected thereto, and a plurality of dummy cells (used for smoothing capacitors). FIG. 2 is a diagram showing a smoothing memory cell) DMC. The sense amplifier circuit SA includes an amplifier circuit AMP7 for data line amplification, an equalize circuit EQ for data line equalization, a precharge circuit PC for data line precharge, a dummy write circuit DW for writing dummy cells DMC, and a column switch line Yi. Composed.

  Further, in FIG. 1, only three sense amplifier circuits (SA5 to SA7 connected to the data lines DLT5 to DLT7 / DLB5 to DLB7) are shown, and the others are omitted because the drawing becomes complicated. The word lines (sub word lines) of the memory cells MC used for writing and reading desired data are described as SWLU0, SWLU1, SWLD0, and SWLD1, and the word lines (sub word lines) of the dummy cells DMC are DWLU0, DWLU1, DWLD0, and DWLD1. It is described. The control signal of the equalizing circuit EQ is DLEQ, the control signal of the precharge circuit PC is DLPR, the source of the precharge circuit PC is the precharge power supply VDL, the control signal of the dummy write circuit DW is DMW, and the source of the dummy write circuit DW is the dummy cell Power supply VDLP, local input / output lines are LIOT <3: 0>, LIOB <3: 0>, NMOS side source line of amplifier circuit AMP is common source line CSN, PMOS side source line is common source line CSP, common source CSN control The signal is described as SAN1T, the common source CSP control signal as SAP1B, the common source CSN power supply as VSSA, and the common source CSP power supply as VDL.

  The unselected (Un-selected) MAT side data lines DLT40, DLT50, and DLT60 are connected to the data line contacts of the memory cells connected to the word lines SWLD0 and SWLD1, and are connected to the word lines DWLD0 and DWLD1. It is not connected to the data line contact of the memory cell. That is, as shown in FIG. 1, the data lines DLT40, DLT50, and DLT60 are cut on the dummy cell DMC, and a part of the cut data line is used to connect the data line contact of the dummy cell DMC and the common source power supply VSSA. (VSSAL4, VSSAL5, VSSAL6 in the figure). With such a configuration, a part of the dummy cell DMC can be used as a smoothing capacitor for the common source CSN power supply VSSA and the plate power supply (VPLT) of the plate electrode PL. As shown in FIG. 1, the data line between the data lines DLT5 and DLT6 on the selected (Selected) MAT side is similarly cut off and connected to the common source power supply VSSA. Some symbols and the like in the drawing are omitted because the drawing becomes complicated.

  FIG. 2 shows an example of operation waveforms of a memory cell array using the sense amplifier circuit of FIG. In the precharge period PRE, the precharge control signal DLPR and the equalize control signal DLEQ are asserted high, and the data line pair (DLT7 / DLB7 in the example in the figure) and the common source lines CSN and CSP are precharged to VDL.

  Next, in the activation period ACT, the word line SWLU0 on the selected MAT side is asserted high, and a read signal is output to the data line DLT7. In the example of FIG. 2, an example in which an “L” signal is read from the memory cell is illustrated. Simultaneously with the activation of the word line SWLU0, the word line DWLD0 on the non-selected MAT side is activated, and the reference level signal is output to the data line DLB7. A dummy cell power source VDLP is previously written in the dummy cell DMC. Therefore, simultaneously with the activation of the word line DWLD0, a signal having a level intermediate between the potential level output to the DLT 7 and the precharge level VDL is output to the data line DLB7. At this time, the storage node of the memory cell rises from the “L” level to the level of the data line DLT7. Therefore, in the conventional method, the potential of the plate electrode, which is the counter electrode of the memory cell, rises transiently as shown in the waveform of the plate power supply VPLT (illustrated by a broken line) immediately after activation of the word line in FIG. This transient fluctuation of the power supply level prevents stable read operation as array noise.

  However, in the example of FIG. 1 of the present embodiment, when the word line DWLD0 is activated, the common source CSN power supplies VSSAL4 to VSSAL6 are electrically short-circuited to the storage node via the memory cell transistors, and the memory cell capacitance plate It becomes a counter electrode of an electrode. That is, one out of every two memory cells connected to the word line DWLD0 is used as a smoothing capacitor for the common source CSN power supply VSSA and the plate power supply VPLT. With such a configuration, transient fluctuations (illustrated by broken lines) of the plate power supply VPLT immediately after activation of the word line in FIG. 2 are suppressed. That is, the coupling noise to the data line pair caused by the transient fluctuation of the plate power supply VPLT is reduced, and a stable read signal amount can be secured. This smoothing capacitor has the effect of reducing array noise during the amplification operation of the data line pair in addition to the effect of stable output of the read signal amount.

  The reason for this will be described below. The amplification operation of the data line pair is a discharge operation of the data line (for example, DLT7). Therefore, when the majority of the selected memory cells are “L” read, the majority of the storage nodes are at the “L” level, so that the plate electrode which is the counter electrode of the memory cell is transiently initialized by coupling. The potential drops from the VDLP (VDL / 2) to the “L” side. On the other hand, since the charge stored in the data line flows into the common source CSN power supply VSSA, VSSA (ground level) rises transiently. In the conventional VDD precharge method, this transient fluctuation of the power supply level (shown by broken lines (VPLT, VSSA) in FIG. 2) becomes array noise, which hinders high-speed sensing operation.

  However, in this embodiment, since a part of the dummy cell is used as a smoothing capacitor, the transient fluctuation of the power supply potential as shown by the broken line in FIG. 2 can be reduced as shown by the solid line. As a result, an increase in the source power supply VSSA of the NMOS cross-coupled circuit of the amplifier circuit AMP can be suppressed, and the data line discharge operation can be speeded up. That is, the sensing operation can be speeded up.

  Since the read operation and the write operation when using the sense amplifier circuit SA of the present embodiment are the same as those when using the conventional sense amplifier circuit, the read period READ and the write period WRITE in FIG. As shown, a read operation and a write operation can be performed by the same driving method. In addition, the addition of a special circuit method or device structure is not necessary for the column system operation, so there is no possibility of reducing the yield of the chip.

  Next, the precharge period PRE after the write period WRITE will be described. Immediately after the start of the precharge period PRE, the word line SWLU0 of the selected memory cell MC is first deactivated. Next, the equalize circuit EQ and the dummy cell write control signal DMW are activated. Thereby, dummy cell power supply VDLP can be written in dummy cell DMC. Note that current consumption can be reduced by activating the equalize circuit EQ. When the dummy cell power supply level VDLP is written in the dummy cell DMC, the word line DWLD0 and the dummy cell write control signal DMW are deactivated. Thereafter, the precharge control signal DLPR is activated to precharge the data line pair to the precharge level VDL. Note that the common source CSP control signal may be activated during precharge. This is because, when the common source CSP control signal is activated, the precharge of the common source lines CSN and CSP and the data line pair can be accelerated. The above is the operation method of the sense amplifier circuit of this embodiment.

  The configuration of the present embodiment is not limited to FIGS. 1 and 2. It goes without saying that various changes can be made without departing from the spirit of the present idea.

  For example, as shown in the operation waveform of FIG. 3, the word line DWLU0 of the dummy cell on the selected MAT side may be activated during the activation period ACT. In the example of FIG. 2, when the word line SWLU0 of the selected memory cell MC is deactivated in the precharge period PRE immediately after the write period WRITE, the non-selected MAT side rather than the load capacity of the data line on the selected MAT side. The load capacity of the data line becomes larger. This is because the load capacity of the data line appears to be larger by the cell capacity CS of the dummy cell DMC because the word line DWLD0 of the dummy cell DMC on the non-selected MAT side is activated. If the load capacity of the data line pair becomes unbalanced, the equalization level of the data line equalization operation in the dummy cell write operation immediately before the data line precharge may deviate from VDLP. As a result, the level of the data line pair must be set to VDLP by the dummy write circuit DW, which may increase current consumption.

  On the other hand, as shown in FIG. 3, if the word line DWLU0 of the dummy cell DMC on the selected MAT side is activated during the activation period ACT, the load capacity of the data line pair can be made equal during the precharge period PRE. That is, the unbalance of the data line load capacity as described above is eliminated, and the data line can be equalized at high speed. Since the equalize level can be set to VDLP, the current consumption of the dummy write circuit DW can be reduced. Thus, since the dummy cell power supply level VDLP can be written to the dummy cell DMC at high speed, the time required for the precharge period PRE can be shortened, and the speed of the DRAM chip can be increased.

  In the example of FIG. 1, one of two dummy cells DMC connected to a word line, for example, DWLD0, is used as a smoothing capacitor. However, the number of memory cells used as the smoothing capacitor is not particularly limited to this. Needless to say, a smoothing capacity sufficient for reducing power supply noise can be ensured, and one of four may be sufficient. Further, the types of transistors (NMOS transistor, PMOS transistor, gate insulating film is thin or thick) constituting the equalize circuit EQ, precharge circuit PC, and dummy write circuit DW are not particularly limited.

  For example, the equalizer circuit EQ may be a thick film NMOS transistor. In this case, a boosted power supply VPP (for example, 3 V) is applied to the control signal DLEQ of the equalizer circuit EQ. For this reason, the drive current of the equalize circuit EQ may be larger than when the equalize circuit EQ is configured by a thin film NMOS transistor, but the on-current of the thick film NMOS transistor is larger than that of the thin film NMOS transistor, and the data Line equalization time can be shortened. Similarly, the precharge circuit PC or the dummy write circuit DW can be variously modified such as a thick film NMOS transistor, a thin film PMOS transistor, or a thin film NMOS transistor.

  As for the threshold voltage, a standard threshold voltage, a low threshold voltage, or the like may be applied and used in combination with any of the above transistor types in accordance with the purpose. Although not specifically described, it goes without saying that various transistors and various threshold voltages may be used in combination for the amplifier circuit AMP and the column switch line Yi. Further, although an open type memory cell array configuration is described in this embodiment mode, it goes without saying that a folded type memory cell array may be applied.

  Next, with reference to FIG. 4 and FIG. 5, a plan layout view and its bird's-eye view on the non-selected MAT side including the data lines of this embodiment will be described. Symbols in the figure that are not described up to FIG. 3 are the shape dummy cell array DMCA, dummy cell arrays DMCL, DMCR, diffusion layer ACT of normal memory cells, diffusion layer DACT of dummy cells, and diffusion of memory cells used for smoothing capacitors. Layer CACT, storage node contact SNCNT, data line contact DLCNT, common source CSN power supply VSSAL, VSSAR, sense amplifier circuits SAA5, SAA6, data line DLT50, DLB50, DLT60, DLB60, ground power supply level VSS, word lines SWLDm, SWLDn, DWL0 , DWL1.

  As shown in FIGS. 4 and 5, the feature of the present embodiment is that a part of the data line on the non-selected MAT side, for example, DLT 60 is cut to be VSSAL6. That is, a part of the cut data line and the common source CSN power supply VSSAL are connected by the contact CNT, and the plate electrode PL and the common source power supply VSSAL6 are used as a counter electrode of the memory cell capacitor CS via the memory cell transistor. In this way, a part of the dummy cell array DMCL can be used as a smoothing capacitor for the plate power supply VPLT and the common source CSN power supply VSSA, and array noise related to the read operation can be reduced.

(Embodiment 2)
A semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIGS.

  Although the example of the plate power supply VPLT and the common source CSN power supply VSSA has been described as the target of power supply noise to be smoothed in the first embodiment, the dummy cell DMC may be used for smoothing other power supply voltages.

  FIG. 6 shows an example in which a common source CSN power supply VSSA and a data line precharge power supply VDL are connected as a counter electrode of a memory cell capacity of a dummy cell DMC used as a smoothing capacity. The difference from FIG. 1 is that, among the dummy cells DMC, the counter electrodes of the memory cells used as smoothing capacitors are all the common source CSN power supply VSSA, but a part thereof is the precharge power supply VDL. The other element circuits in the sense amplifier circuit are the same as those in FIG. Needless to say, as described in FIG. 1, it goes without saying that various modifications can be made without departing from the spirit of the invention.

  With the configuration shown in FIG. 6, a necessary and sufficient smoothing capacitor is added to the precharge power supply VDL. That is, it is possible to reduce the transient fluctuation of the precharge power supply VDL that occurs at the time of precharge and to shorten the precharge period.

  Next, FIG. 7 will be described. 7 differs from FIG. 6 in that FIG. 6 uses the precharge power supply VDL as the counter electrode of the plate electrode PL of the dummy cell DMC used as a smoothing capacitor, whereas in FIG. 7, the dummy cell power supply VDLP is opposed to the plate electrode PL. This is the point of the electrode. With the configuration as shown in FIG. 7, a necessary and sufficient smoothing capacity is added to the dummy cell power source VDLP. That is, when the dummy cell power source VDLP is written in the dummy cell DMC, the transient fluctuation of the dummy cell power source VDLP is reduced, so that the writing speed to the dummy cell DMC is increased.

  Next, FIG. 8 will be described. 8 differs from FIG. 6 in that FIG. 6 uses a pre-charge power supply VDL as a counter electrode of the plate electrode PL of the dummy cell DMC used as a smoothing capacitor, whereas in FIG. 8, the common source CSP power supply VDL is used as the plate electrode PL. It is a point made into the counter electrode. With the configuration shown in FIG. 8, a necessary and sufficient smoothing capacity is added to the common source CSP power supply VDL. That is, since the transient fluctuation of the common source CSP power supply VDL generated when the data line pair is amplified is reduced, the data line amplification speed can be increased.

  Needless to say, the configuration described so far can be variously modified without departing from the gist of the invention. For example, the precharge level of the data line may be set to the ground voltage level VSS. In this case, if the plate electrode PL and the data line are set to the high level VDL (the power level of the common source CSP) as the counter electrode of the smoothing capacitor, the transient fluctuation of the power supply voltage at the time of reading can be reduced and the access speed is increased. Can be realized. Although not specifically explained, when the precharge level of the data line is VSS, the method of using the plate electrode PL and the high level VDL of the data line as the counter electrode is, for example, a change of the VSSAL (VSSAR) wiring additionally arranged in FIG. In addition, a VDLL (VDLR) wiring may be provided as a counter electrode of the plate electrode PL. Needless to say, as the counter electrode of the smoothing capacitor, a part of the high level VDL of the data line may be set to another power supply level, for example, the precharge level VSS of the data line or the dummy cell power supply level VDLP. In this way, by using a power supply level that causes a transient fluctuation due to a read operation as the counter electrode of the plate, the fluctuation can be reduced and the access speed can be increased.

(Embodiment 3)
A semiconductor memory device according to the third embodiment of the present invention will be described with reference to FIGS.

  In the first and second embodiments, in the VDD (VDL) precharge method in which the data line is precharged to high level during the precharge period PRE, transient fluctuations of various power supply levels caused by the read operation are reduced. Therefore, although the smoothing capacity method using the dummy cell DMC has been described, the smoothing capacity method of the present embodiment may be applied to a conventional half (VDD / 2) precharge method.

  FIG. 9 shows an example in which a dummy cell DMC is used as a smoothing capacitor for various power supply voltages in a VDD / 2 precharge type sense amplifier circuit. The sense amplifier circuit of FIG. 9 is different from the first and second embodiments in that there is no dummy write circuit DW. The other parts are the same as in the first embodiment.

  FIG. 9 shows an example in which the plate power supply VPLT and the common source CSN power supply VSSA are connected to the counter electrode of the memory cell capacity of the dummy cell DMC used as the smoothing capacity. With such a configuration, a necessary and sufficient smoothing capacity can be added to the common source CSN power supply VSSA. Since the precharge level of the data line is a half level VDLP, the applied voltage between the gate and the source of the NMOS transistor in the amplifier circuit AMP is lower than the VDD precharge, so that the driving power of the amplifier circuit AMP is reduced. There is a case. Even in such a case, a transient fluctuation of the common source CSN power supply during sensing can be suppressed by adding a smoothing capacitor to a part of the power supply related to the amplification of the data line as in this embodiment. That is, since array noise is reduced, the data line amplification speed can be increased.

  Next, FIG. 10 will be described. 9 is different from FIG. 9 in that FIG. 9 is connected to the common source CSN power supply VSSA as the counter electrode of the plate electrode PL of the dummy cell DMC used as a smoothing capacitor, whereas in FIG. A part of the dummy cell DMC connected to the CSN power supply VSSA is a common source CSP power supply VDL. With such a configuration, a smoothing capacitor can be added to the common source CSP power source VDL as well as the common source CSN power source VSSA. As a result, when the data line is amplified, transient fluctuations of the common source CSN power supply VSSA and the common source CSP power supply VDL can be suppressed. That is, since the array noise related to the sensing operation is reduced, the data line amplification speed can be increased.

  Next, FIG. 11 will be described. 11 differs from FIG. 9 in that FIG. 9 is connected to the common source CSN power supply VSSA as the counter electrode of the plate electrode PL of the dummy cell DMC used as a smoothing capacitor, whereas in FIG. 11, the substrate of the sense amplifier circuit is used. The voltage VBBSA is connected. A control line for driving the common source line CSN to the VSSA level is SAN2T, and a control line SAN1T for driving the common source line CSN to the substrate voltage VBBSA is added thereto. The substrate voltage VBBSA is generally a negative voltage lower than the ground voltage VSS.

  When amplifying the data line, it is desirable to first activate the control line SAN1T and drive the common source line CSN to the substrate voltage VBBSA. This is because the voltage applied between the gate and the source of the NMOS transistor in the amplifier circuit can be sufficiently secured, and the amplification speed of the data line can be increased. After sufficiently amplifying the data line, the common source CSN control line SAN2T is activated almost simultaneously with the deactivation of the common source CSN control line SAN1T, and the L side level of the data line is set to the ground level. Further, since the plate power source VPLT and the common source CSN power source, that is, the substrate voltage VBBSA, are connected as the counter electrode of the dummy cell DMC used as a smoothing capacitor, the transient fluctuation of the common source CSN power source VBBSA is caused when the data line is amplified. Can be suppressed. In other words, since array noise related to the sensing operation is reduced, the data line amplification speed can be increased.

  Next, FIG. 12 will be described. The difference between FIG. 12 and FIG. 11 is that in FIG. 11, the substrate voltage VBBSA of the sense amplifier circuit is connected as the counter electrode of the plate electrode PL of the dummy cell DMC used as a smoothing capacitor, whereas in FIG. A part of the dummy cell DMC connected to the common source CSN power source VBBSA is a common source CSP power source VDL. By adopting such a configuration, a smoothing capacitor can be added to the common source CSP power source VDL as well as the common source CSN power source VBBSA. As a result, when the data line is amplified, transient fluctuations of the common source CSN power supply VBBSA and the common source CSP power supply VDL can be suppressed. That is, since the array noise related to the sensing operation is reduced, the data line amplification speed can be increased.

(Embodiment 4)
A semiconductor memory device according to a fourth embodiment of the present invention will be described with reference to FIGS.

  The example of FIG. 13 is obtained by adding a configuration in which adjacent data lines are electrically short-circuited immediately after activation of the word line to FIG. 1 of the first embodiment. With this configuration, the reference signal level output to the data line on the non-selected MAT side can be stabilized when the VDD precharge method is used. In the example of FIG. 13, when the short circuit signal SRTU is activated, the data lines DLT5, DLT6, DLT7, and DLT8 are electrically connected. Similarly, when the short circuit signal SRTD is activated, the data lines DLB4, DLB5, DLB6, DLB7 are electrically connected.

  The activation timing will be described using the operation waveform of FIG. The difference from the operation waveform of FIG. 2 is that the short circuit signal is activated almost simultaneously with the activation of the word line. Almost simultaneously with the activation of the word line SWLU0 on the selected MAT side and the word line DSWLD0 on the non-selected MAT side, the short circuit signal SRTD located near the non-selected MAT side is activated. Reference signal levels for amplifying the data lines are output to all the data lines on the non-selected MAT side. Since the data lines DLB4, DLB5, DLB6, DLB7 on the non-selected MAT side are connected by the short circuit signal SRTD, the load capacity of the shorted data line from which the reference signal level is output increases. As a result, it becomes difficult to receive coupling noise due to a transient fluctuation of the power supply voltage. That is, since the array noise can be effectively reduced, the reference signal level can be stabilized. This method not only can reduce array noise, but also can reduce variations in the reference signal level due to manufacturing errors. That is, even when there is a variation in the memory cell capacitance CS or the parasitic capacitance of the data line, the variation can be averaged by activating the short circuit signal SRTD. As described above, by combining the smoothing capacity method of the first embodiment and the method of short-circuiting the data lines, there is an effect that the array noise can be further reduced.

  The present embodiment can be variously modified as will be described below. The example of FIG. 15 is obtained by adding a common source CSP control line to the method of FIG. 13 in order to reduce the time required for the precharge period PRE immediately after the write period WRITE. That is, the control line for driving the common source line CSP to the VDL level is SAP1B, and the control line SAP2B for driving the common source line CSP to the VDD level is added thereto.

  The driving method of FIG. 15 will be described using the operation waveforms of FIG. The difference between the operation waveforms in FIG. 16 and FIG. 14 is only the precharge period PRE immediately after the write period WRITE. Therefore, the description of FIG. 16 is only the precharge period PRE, and the rest is omitted. In FIG. 16, after the dummy cell power source VDLP is written in the dummy cell DMC during the precharge period PRE, the common source CSP control line SAP2B is first activated. By activating the common source CSP control line SAP2B, the common source line CSP is driven to the power supply voltage VDD. In this example, the transistor that drives the common source line CSP is a PMOS transistor. The power supply voltage VDD is higher than the common source CSP power supply VDL. Therefore, the PMOS driving power of the common source CSP driving transistor is increased, and the data line can be precharged to the power supply voltage VDD level at high speed. After the data line is precharged to the power supply voltage VDD, the common source CSP control line SAP2B is deactivated almost simultaneously with the common source CSP control in order to reset it to VDL, which is the precharge level of the original data line. Activate line SAP1B. In this way, by controlling the precharge level of the data line to be set from the power supply voltage VDD to the original precharge level VDL, the precharge period can be increased as compared with the example of FIG. The above is the driving method of the example of FIG.

  In the above, an example in which the dummy cell DMC is used as a smoothing capacitor for various power supply voltages has been shown. However, when the power supply wiring can be sufficiently secured and the transient fluctuation of the power supply voltage is small, a part of the dummy cell DMC is smoothed. It is not necessary to use it as a capacity. For example, as shown in FIG. 17, control signals SRTU and SRTD for short-circuiting data lines may be added. If the array noise can be reduced with only the necessary minimum circuit change, the chip area can be reduced, and both high integration and stable read operation can be achieved. The unit of the data line electrically connected using the short circuit signals SRTU and SRTD is preferably equal to the unit of the data line to which the column switch line Yi is connected.

  FIG. 18 is a diagram illustrating the relationship between the short-circuit signals SRTU and SRTD and the data lines DLT4, DLT5, DLT6, DLT7, DLB4, DLB5, DLB6, and DLB7 connected thereto. With the configuration as shown in FIG. 18, for example, when the column switch line Yi is defective, the column repair circuit switches between the defective column switch line Yi and the redundant column switch line. At this time, if the unit of the short circuit signal and the data line connected thereto is the same as that of the data line connected to the column switch line Yi, the conventional relief circuit method can be used, so that the circuit need not be changed. . Further, for example, when the failure mode in which the column switch line Yi is fixed at the high level is entered, the data line is fixed at the precharge level VDD of the local input / output line. In such a case, for example, when the data line DLB3 (not shown) adjacent to the data line DLB4 is electrically connected by the short circuit signal SRTD, the reference signal level may be lost. However, this problem can be solved with the configuration shown in FIG. That is, there is an effect of improving the yield of chips.

(Common form of Embodiments 1 to 4)
A common form of the semiconductor memory device according to the first to fourth embodiments of the present invention will be described with reference to FIGS.

  19 shows control lines FXB0, FXB1, FXB2, FXB3, FXT0, FXT1, FXT2, and FXT3 for driving the sub word lines of the normal memory cells MC and the sub word lines of the dummy cells DMC in the configurations of the first to fourth embodiments. The structure is shown. Symbols in the figure are subword driver arrays SWDA_U and SWDA_D, sense amplifier arrays SAA-L and SAA-R, a cross area IS located at the intersection of the subword driver array and the sense amplifier array, an inverter INV in the cross area IS, and a memory Cell arrays MCA0 to MCA7. Since the drawing becomes complicated, main word lines, dummy main word lines, sub word lines, sense amplifier circuit control signals, etc. are omitted.

  First, an address is decoded by a row decoder RDEC (not shown), and the main word line and subword selection line FXB1 of the selected MAT are activated. As a result, a desired sub word line in the selected MAT is activated. On the other hand, in order to activate the dummy cell DMC, the dummy main word line and the sub word control line FXB2 arranged on the non-selected MAT on both sides of the selected MAT are simultaneously activated. As a result, the sub-word line of the dummy cell DMC on the non-selected MAT side is activated. The dummy cell DMC can be activated by using the control method described above using the control line configuration of FIG. If the method of FIG. 19 is used, the conventional configuration can be used for the gate layout and the diffusion layer layout of the sub-word driver array. That is, since the scale of the layout change is small, the design becomes easy.

  FIG. 20 is a circuit diagram showing an example of the configuration of the sub word driver array. The sub word driver array SWDA is composed of a plurality of sub word drivers SWD, and the sub word driver array SWDA is arranged around the memory cell array MCA (MCA1, 2). The sub word driver SWD drives the sub word line WL in the memory cell array MCA arranged on both sides. Since the sub word driver arrays SWDA are alternately arranged with respect to the memory cell array MCA, every other sub word line WL in the memory cell array MCA is connected to the upper and lower sub word drivers SWD.

  The sub word driver SWD is composed of two N channel MOS transistors and one P channel MOS transistor. One N-channel MOS transistor has a gate connected to the main word line MWLB (MWLB0, 1), a drain connected to the sub word line WL (WL0, 2, 4, 6), and a source connected to the negative voltage VKK. . The other N-channel MOS transistor has a gate connected to a complementary sub word control line FXB (FXB0, 2), a drain connected to a word line WL, and a source connected to a negative voltage VKK. Here, VKK is a voltage lower than VSS generated by the negative voltage generation circuit. In the P-channel MOS transistor, the main word line MWLB is connected to the gate, the word line WL is connected to the drain, and the sub word driver selection line FXT (FXT0, 2) is connected to the source. Two sub word driver selection lines FXT0, 2 are wired on one sub word driver array SWDA, and one of the two sub word drivers SWD selected by one main word line MWLB is selected to be 1 The sub word line WL is activated.

  FIG. 21 is a circuit diagram showing an example of the configuration of the cross area IS. The cross area IS includes a precharge driver DLEQD for a precharge timing signal, a local input / output line precharge circuit REQ, a read / write gate RGC, a common source driver CSD for driving a common source line CSN and CSP, and a common source line precharge. A circuit CSEQ and an FX line driver FXD are arranged.

  The local input / output line precharge circuit REQ precharges the local input / output line LIOT / B to the voltage VDL when the common source equalize signal CSEQT is at an inactive VSS level. The read / write gate RGC is connected to the local input / output line LIOT / B when the common source equalize signal CSEQT is at the active state voltage VCL (the same as or lower than the external VDD level is used as the peripheral circuit power supply voltage). And a main input / output line MIOT / B.

  The common source driver CSD drives the common source line CSN to the ground voltage VSS when the common source CSN control signal SAN1T is in the active state, and the P side when the common source CSP control signal SAP1B is in the active state (VSS level). This is a circuit for driving the common source line CSP to the voltage VDL ('H' level of the bit line).

  The common source line precharge circuit CSEQ is a circuit that precharges the P-side and N-side common source lines CSP and CSN to VDL when the common source equalize signal is deactivated. The precharge driver DLEQD receives the precharge control signal DLPR and complementary signals DLPRB and DLEQB of the equalize control signal DLEQ, and outputs an inverted signal thereof. The FX line driver FXD receives the sub word control line FXB0 and outputs the complementary signal to the sub word selection line FXT0 (FX line).

  FIG. 22 is a block diagram when a DRAM chip is designed using the sense amplifier circuit of the present embodiment. Symbols shown in the figure are an address buffer ADDRESS BUFFER, a column address buffer COLUMN ADDRESS BUFFER, a column address counter COLUMN ADDRESS COUNTER, a row address buffer ROW ADDRESS BUFFER, a refresh counter REFRESH COUNTER, a bank select BANK SELECT decoder, a mode register STR ROW DEC, column decoder COLUMN DEC, main sense amplifier SENSE AMP, memory cell array MEMORY CELL ARRAY (memory banks BANK0, 1, 2, 3), data input buffer Din BUFFER, data output buffer Dout BUFFER, data buffer D QS BUFFER, delay locked loop DLL, control logic CONTROL LOGIC, clock CLK, / CLK, clock enable signal CKE, chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS, write enable signal / WE, The data write signal DW, the data strobe signal DQS, and the data DQ.

  Note that the control method of these circuits and signals is the same as that of a known SDRAM / DDR SDRAM and the description thereof is omitted here. By applying the sense amplifier circuit of this embodiment, a DRAM having features such as low power consumption, high speed operation, and high reliability can be realized. The block configuration is not particularly limited to FIG. The number of memory cell arrays MEMORY CELL ARRAY may be increased, and various modifications are possible without departing from the gist of the present embodiment.

  FIG. 23 shows a configuration example of the entire chip in the sense amplifier circuit of the present embodiment. The semiconductor memory device shown in FIG. 23 is a DRAM. The overall configuration of the memory chip CHIP includes, for example, a control circuit CTL, an input / output circuit DQCTL, a memory bank BANK, a test circuit DFT, a power supply voltage generation circuit VOLGEN, a data control circuit DCTL, a row decoder array RDECA, a column decoder array CDECA, It can be roughly divided into main amplifiers Main Amp. A clock, an address, and a control signal are input to the control circuit CTL from outside the memory chip CHIP, and an operation mode of the memory chip CHIP is determined, an address is predecoded, and the like. The input / output circuit DQCTL includes an input / output buffer and the like, and receives write data from the outside of the memory chip CHIP and outputs read data to the outside of the memory chip CHIP.

  In the memory bank BANK, for example, as shown in FIG. 24, subarrays SARY arranged in a plurality of arrays are arranged, and around them, sense amplifier arrays SAA-L, SAA-R, subword driver arrays SWDA_U, SWDA_D, A cross area IS is arranged. On the outer periphery of the memory bank BANK, a column decoder CDEC and a main amplifier Main Amp are arranged in parallel with the sense amplifier array SAA, and a row decoder RDEC and an array control circuit (not shown) are arranged in parallel with the sub word driver array SWDA. Be placed.

  FIG. 25 is a diagram showing a planar layout of the subarray SARY (SARY0) in FIG. 24 and the sense amplifier arrays SAA-R and SAA-L connected thereto. The access transistor is composed of a sub word line WL and a diffusion layer ACT, and the memory cell capacitor CS is composed of a storage node SN and a plate electrode PL. The other symbols are a cell contact CCNT for connecting the diffusion layer ACT to wirings and contacts above it, a data line contact DLCNT for connecting the data lines DLT and DLB and the diffusion layer ACT, and a landing pad LPAD. Here, the landing pad LPAD is a contact connecting the storage node SN and the storage node contact SNCNT, and the position of the memory cell capacitor CS can be optimized, so that the surface area of the memory cell capacitor CS can be increased. Of course, the landing pad LPAD may not be used if the memory cell capacity CS can be sufficiently secured. In that case, since process steps can be reduced, costs can be reduced.

  Further, as shown in FIG. 25, the layout of the memory cell MC can be variously modified. FIG. 25A shows a so-called folded data line structure, which has an advantage that miniaturization is easy because the diffusion layer ACT is a simple rectangle. FIG. 25B shows a pseudo folded data line structure. The difference from (a) is that the diffusion layer ACT is laid out obliquely with respect to the sub word line WL. For this reason, since the channel width can be effectively increased, there is an advantage that the ON current of the access transistor can be increased. Therefore, when combined with the sense amplifier circuit of this embodiment, a semiconductor memory device capable of higher speed operation can be realized. FIGS. 25C and 25D show an open data line structure. Compared to the folded data line structure, there is an advantage that the cell area can be reduced. In FIG. 25C, since the data line pitch is wide, the data line parasitic capacitance can be reduced. Therefore, by combining with the sense amplifier circuit of this embodiment, a semiconductor memory device that is more highly integrated and capable of low voltage operation can be realized. In FIG. 25D, the cell area can be further reduced as compared with FIG. 25C, and a highly integrated semiconductor memory device can be realized by combining with the sense amplifier circuit of this embodiment.

  Of course, the memory cell layout applicable to the sense amplifier circuit of this embodiment is not limited to this. For example, in the open data line structure of FIG. 25D, the diffusion layer ACT laid out obliquely with respect to the sub word line WL may be laid out so as to be orthogonal to each other as shown in FIG. In that case, since the shape is rectangular, there is an advantage that miniaturization is easy. Furthermore, it is possible to apply the element isolation by sharing the diffusion layer ACT of the left and right adjacent cells of the sub word line WLA and always applying the low level VSS to the sub word line WLA. In this case, since it is not necessary to form an element isolation region made of an insulator in a direction parallel to the data line, process steps can be reduced and costs can be reduced. As described above, it goes without saying that the memory cell structure applicable to the sense amplifier circuit of the present embodiment can be variously modified without departing from the gist thereof.

  FIG. 26 is a diagram showing a part of a cross-sectional view of the subarray SARY0 and the sense amplifier arrays SAA-R and SAA-L shown in FIG. 25 cut along the line A-A 'in FIG. Symbols in the figure are a second-layer metal wiring layer M2, a third-layer metal wiring layer M3, a P-well substrate PW, an N-well substrate NW, a deep N-well substrate DNWELL, and a P-type substrate PSUB. Since these forming methods are the same as those of a general semiconductor memory device, particularly a so-called general-purpose DRAM, detailed description thereof is omitted here.

  Further, the structure of the memory cell capacitor CS is not limited to the structure shown in the figure. Needless to say, various modifications are possible including, for example, a crown type capacitor. Further, the number of wiring layers is not particularly limited. The DRAM chip of this embodiment may be formed using a fourth metal wiring layer. In this case, since the fourth layer wiring can be used for the global input / output lines and the power supply wiring, the pitch of the second and third wiring layers can be relaxed, and a higher performance DRAM chip can be realized.

  In the above embodiment, the case where a general planar transistor is used as the memory cell transistor has been described. However, the present invention is not limited to this. A DRAM chip may be configured by applying a so-called three-dimensional memory cell transistor. In this way, it is possible to provide a high-performance DRAM that can achieve both improvement in retention time and increase in access time.

  As described above, the sense amplifier circuit of this embodiment can be modified in various ways according to the purpose such as low voltage operation, high speed operation, and high integration.

  The present invention relates to a semiconductor device, and is particularly applicable to a high-speed, highly integrated semiconductor memory device and a differential amplification operation portion of a semiconductor device in which a logic circuit and a semiconductor memory device are integrated.

  SA, SA5, SA6, SA7, SAA5, SAA6 ... sense amplifier circuit, AMP4, AMP5, AMP6, AMP7 ... amplifier circuit, SAA-R, SAA-L ... sense amplifier array, MCA0, MCA1, MCA2, MCA3, MCA4, MCA5 , MCA6, MCA7 ... memory cell array, SARY, SARY0 ... subarray, CSN, CSP ... common source line, SAN1T, SAN2T ... common source CSN control line, SAP1B, SAP2B ... common source CSP control line, VSSA, VSSAL, VSSSAR, VSSAL5 VSSAL6, VSSAR4, VSSAR5, VSSAR6 ... common source CSN power supply, MC ... memory cell, DMC ... dummy cell, DMCL, DMCR ... dummy cell array, DMCA ... shape dummy cell array, D CT ... dummy cell diffusion layer, CACT ... smoothing capacitor memory cell diffusion layer, Selected MAT ... selected MAT, Un-selected MAT, Un-selected MAT0 ... unselected MAT, SWLU0, SWLU1, SWLD0, SWLD1, DWLU0, DWLU1, DWLD0, DWLD1, DWL0, DWL1, SWLDm, SWLDn, WL, WL0, WL2, WL4, WL6, WLA ... sub-word lines, Yi, Yi + 1, Yi + 2 ... column switch lines, LIOT, LIOB, LIOT <3: 0>, LIOB <3: 0> ... Local input / output line, DLT5, DLT6, DLT7, DLT8, DLB4, DLB5, DLB6, DLB7, DLT40, DLT50, DLT60, DLB50, DLB60 ... data line, SRTU, SR D ... Short circuit signal, VPLT ... Plate power supply, VDLP ... Precharge voltage or dummy cell power supply, VDL ... Precharge power supply or common source CSP power supply or data line high level, VBBSA ... Substrate voltage or common source CSN power supply, DLEQ, DLEQB ... Equalize control signal, EQ ... Equalize circuit, DLPR, DLPRB ... Precharge control signal, PC ... Precharge circuit, DMW ... Dummy write control signal, DW ... Dummy write circuit, VSS ... Ground voltage, VDD ... Power supply voltage, VKK ... Word Negative voltage during line standby, SWD ... subword driver, SWDA, SWDA_U, SWDA_D ... subword driver array, FXB0, FXB1, FXB2, FXB3 ... subword control lines, FXT0, FXT1, FXT2, FXT3 ... subword Mode selection line, MWLB0, MWLB1 ... main word line, MIOT, MIOB ... main input / output line, INV ... inverter, DLEQD ... precharge driver, CSD ... common source driver, REQ ... local input / output line precharge circuit, RGC ... Read / write gate, CSEQ ... common source line precharge circuit, FXD ... FX line driver, CSEQT ... common source equalize signal, IS ... cross area, ACT ... diffusion layer, SN ... storage node, PL ... plate electrode, LPAD ... landing pad SNCNT ... storage node contact, DLCNT ... data line contact, CCNT ... cell contact, LCNT ... diffusion layer contact, M2 ... second metal wiring layer, M3 ... third metal wiring layer, PW ... P well substrate, NW ... N-well substrate, D WELL ... Deep N well substrate, PSUB ... P-type substrate, VBB ... Substrate potential, Thick film NMOS ... Thick film NMOS transistor, Thin film NMOS ... Thin film NMOS transistor, ADDRESS BUFFER ... Address buffer, COLUMN ADDRESS BUFFER ... Column address buffer, COLUMN ADDRESS COUNTER ... column address counter, ROW ADDRESS BUFFER ... row address buffer, REFRESH COUNTER ... refresh counter, BANK SELECT ... bank select, MODE RESISTER ... mode register, ROW DEC ... row decoder, COLUMN DEC ... column decoder, SENSE AMP ... main sense Amplifier, EMORY CELL ARRAY ... memory cell array, Din BUFFER ... data input buffer, Dout BUFFER ... data output buffer, DQS BUFFER ... data buffer, DLL ... delay locked loop, CONTROL LOGIC ... control logic, CLK, /CLK...clock, CKE ... Clock enable signal, /CS...Chip select signal, /RAS...Row address strobe signal, /CAS...Column address strobe signal, /WE...Write enable signal, DW ... Data write signal, DQS ... Data strobe signal, DQ ... Data, CHIP ... Memory chip, RDEC ... Row decoder, CTL ... Control circuit, RDECA ... Row decoder array, CDECA ... Column decoder array, CDEC ... Mudekoda, BANK ... the memory bank, Main Amp ... the main amplifier, DFT ... test circuit, VOLGEN ... power supply voltage generation circuit, DCTL ... data control circuit, DQCTL ... input and output circuit.

Claims (15)

A memory cell array including a plurality of word lines, a plurality of data lines, and a plurality of normal memory cells arranged at intersections of the plurality of word lines and the plurality of data lines;
A plurality of sense amplifier circuits connected to each of a plurality of data line pairs composed of the plurality of data lines;
The sense amplifier circuit includes a first circuit that precharges the data line to a high level that is the same voltage level as the level written to the normal memory cell before reading a signal from the normal memory cell;
The memory cell array has a plurality of smoothing capacitors used for smoothing the power supply voltage in addition to the plurality of regular memory cells.
Each voltage of the counter electrode of each of the plurality of smoothing capacitors is a voltage applied to a plate electrode of the normal memory cell and a ground level voltage used for the sense amplifier circuit. The semiconductor device according to claim 1,
The plurality of smoothing capacitors are composed of a plurality of smoothing memory cells arranged at intersections of two word lines and the plurality of data lines,
Each voltage of the counter electrode of each of the plurality of smoothing memory cells is a voltage applied to the plate electrode of the normal memory cell and a ground level voltage used in the sense amplifier circuit,
The word line of the smoothing memory cell is activated when data is read from the normal memory cell,
The smoothing memory cell is disposed between the sense amplifier circuit and the normal memory cell,
The data line connected to the smoothing memory cell is shared with the data line of the normal memory cell,
A part of the plurality of common data lines is physically cut and connected to a power supply voltage level applied to the smoothing capacitor. The semiconductor device according to claim 2,
Each voltage of the counter electrode of some of the plurality of smoothing memory cells is a voltage applied to the plate electrode of the normal memory cell and a voltage for precharging the data line. A semiconductor device characterized by the above. The semiconductor device according to claim 2,
A part of the plurality of smoothing memory cells is a reference memory cell that outputs a reference signal level when the data line is amplified. The semiconductor device according to claim 4.
The word lines of the smoothing memory cell and the reference memory cell are common,
The activation timing of the word line is the same as the activation timing of the word line of the normal memory cell. The semiconductor device according to claim 4.
The word lines of the smoothing memory cell and the reference memory cell are common,
2. The semiconductor device according to claim 1, wherein the deactivation timing of the word line is later than the deactivation timing of the word line of the normal memory cell. The semiconductor device according to claim 4.
The semiconductor device according to claim 1, wherein a voltage level written to the reference memory cell is a half level of a high level of the normal memory cell. The semiconductor device according to claim 7.
When writing the half level of the high level to the reference memory cell, one additional word line connected to the data line side from which the read signal is output is activated,
A semiconductor device characterized in that parasitic capacitances connected to complementary data lines are made equivalent. The semiconductor device according to claim 8.
The semiconductor device according to claim 1, wherein the timing of the additionally activated word line is after the data line is amplified. A memory cell array including a plurality of word lines, a plurality of data lines, and a plurality of normal memory cells arranged at intersections of the plurality of word lines and the plurality of data lines;
A plurality of sense amplifier circuits connected to each of a plurality of data line pairs composed of the plurality of data lines;
The sense amplifier circuit includes a first circuit that precharges the data line to a voltage level that is ½ of a level to be written to the normal memory cell before reading a signal from the normal memory cell;
The memory cell array has a plurality of smoothing memory cells used for smoothing the power supply voltage in addition to the plurality of regular memory cells,
Each voltage of the counter electrode of each of the plurality of smoothing memory cells is a voltage applied to a plate electrode of the normal memory cell and a ground level voltage used in the sense amplifier circuit. apparatus. The semiconductor device according to claim 10.
The voltages of the counter electrodes of some of the plurality of smoothing memory cells are the voltage applied to the plate electrode of the normal memory cell and the high level voltage written to the normal memory cell. A semiconductor device characterized by having the same voltage as The semiconductor device according to claim 10.
The voltages of the counter electrodes of some of the plurality of smoothing memory cells are the voltage applied to the plate electrode of the normal memory cell and the negative voltage applied to the substrate of the sense amplifier circuit. A semiconductor device having the same voltage as a voltage level. A memory cell array including a plurality of word lines, a plurality of data lines, and a plurality of normal memory cells arranged at intersections of the plurality of word lines and the plurality of data lines;
A plurality of sense amplifier circuits connected to each of a plurality of data line pairs composed of the plurality of data lines;
The sense amplifier circuit includes a first circuit that precharges the data line to a high level that is the same voltage level as the level written to the normal memory cell before reading a signal from the normal memory cell;
The memory cell array has a reference memory cell for outputting a reference signal level necessary for amplifying the data line in addition to the plurality of normal memory cells,
The voltage level written to the reference memory cell is a half level of the high level written to the normal memory cell,
A second circuit that electrically short-circuits the data lines connected to the reference memory cell;
Almost simultaneously with the activation of the reference memory cell, the second circuit is activated, and the level of the data line connected to the reference memory cell is made uniform,
A column selection line provided for selecting the sense amplifier circuit;
The number of the plurality of data lines that are electrically short-circuited is the same as the number of the plurality of sense amplifier circuits connected to each column selection line. The semiconductor device according to claim 13.
The standby voltage level of the signal for short-circuiting is a ground level,
Almost simultaneously with the activation of the word lines of the plurality of reference memory cells, the signal for short-circuiting is activated,
The semiconductor device is driven to the ground level again immediately before amplifying the data line. The semiconductor device according to claim 13.
The semiconductor device according to claim 1, wherein the half level of the high level written into the reference memory cell is generated by short-circuiting complementary data lines holding the high level and the low level.

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