KR100597910B1 - Semiconductor memory - Google Patents

Abstract

The direct sense amplifier of the present invention inserts and separates a MOS transistor controlled by a column select line wired in the bit line direction between the MOS transistor serving as a differential pair where the bit line is connected to the gate and the RLIO line, and also acts as a differential pair. The source of the MOS transistor is connected to a common source line wired in the word line direction. During the read operation, the direct sense amplifier is activated only on the selection mat by the column select line and the common source line, thereby greatly reducing the power consumption during the read operation. In addition, the parasitic capacitance of the MOS transistor acting as a differential pair is separated from the local IO line, thereby reducing the load capacity of the local IO line and increasing the read speed. In addition, the data pattern dependency of the load capacity of the local IO line in the read operation is reduced, and the test after manufacture is facilitated.

Direct Sense Amplifiers, Semiconductor Storage, RAM, Memory Arrays, MOS Transistors

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random access memory, and more particularly to a memory for transferring a signal read from a memory cell to a bit line from a gate input amplifier to a peripheral circuit at high speed.

In Japanese Patent Laid-Open No. 11-306762 (hereinafter referred to as "document"), a column sense amplifier CSA is provided on each bit line BL / BLB, as shown in FIG. / GBLB) is described. In this configuration, the column-sense amplifier can be selectively activated by the block-adaptive sense amplifier activation signal S and the Y address signal YB, and power consumption can be reduced.

Prior to the present application, the inventors of the present invention have studied a control method in the case of detecting a so-called direct sense amplifier, which is an amplifier that receives a potential of a bit line of a DRAM differentially at a gate. When the amplifier control method of the above-mentioned document is used for a direct sense amplifier of DRAM, it was found that the following points should be considered. First, large MOS transistors MN20 and MN21, whose bit lines are connected to the gate and act as differential pairs, are directly connected to global bit lines (corresponding to local IO lines to which the output of the direct sense amplifier is connected in DRAM). As a result, the load capacity of the global bit line (local IO line) increases. In DRAM, a large number of direct sense amplifiers of about 32 to 128 are usually connected to the local IO line. In addition, the gate width of the MN20 and MN21 should be 4 µm or more, because the local IO line also has a long distance between the main IO line in front of it and a large load and a long gate length of the MOS transistors used as differential pairs to reduce the threshold offset. There is a need. Therefore, in the configuration in which all of the differential pairs of the non-selected direct sense amplifiers are seen, as in the CSA of FIG. 23, the load capacity of the local IO line is large, and high-speed operation is difficult.

Secondly, the bit line precharge level of the DRAM is VDL / 2, which is half the power supply voltage or the level VDL that stepped down the power supply voltage. Therefore, if a negative signal is generated on the BL and the level of the BL is lower than VDL / 2, the MN21 is cut off and the channel capacity of the MN21 is not seen from the local IO line, but the positive on the BL is positive. When the signal is generated and the level of the BL is higher than VDL / 2, the MN21 conducts and the channel capacity is visible. Therefore, the capacity of the local IO line is greatly changed in accordance with the data pattern on the bit line. That is, there is a problem in that the operating speed is greatly changed depending on the operating conditions, and the test after manufacture is complicated.

Accordingly, a first problem to be solved by the present invention is to configure a direct sense amplifier in a random access memory such as DRAM, SRAM, etc. to selectively activate the load capacity of the local IO line at that time, further reducing the data pattern. To reduce dependencies. Moreover, the 2nd subject of this invention is reducing noise in the direct sense amplifier at the time of performing a high speed operation, and expanding an operation margin. Further, a third object of the present invention is to double the number of bits read from one memory array without increasing the chip size.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Representative configurations of the present invention are as follows.

That is, a word line extending in a first direction, first and second bit lines extending in a second direction crossing the first direction, a memory cell connected to the word line and the bit line pair, and read from the memory cell First and second regions each having an amplifying circuit for amplifying the outputted information, first and second IO lines receiving information read from the amplifying circuit, a source line for controlling the amplifying circuit, and the first region; And a column select line connected in common to a second region and extending in the second direction, wherein the amplifying circuit includes first to fourth MOS transistors, and the first MOS transistor includes: A gate is connected to the first bit line, a gate of the second MOS transistor is connected to the second bit line, a source of the first and second MOS transistors is connected to the source line, Drains of three MOS transistors are connected to the first IO line, drains of the fourth MOS transistors are connected to the second IO line, and gates of the third and fourth MOS transistors respectively included in the amplifying circuit are: A common connection to the column select line, a drain of the first MOS transistor is connected to a source of the third MOS transistor, a drain of the second MOS transistor is connected to a source of the fourth MOS transistor, and a first In the state, the potentials of the first and second IO lines included in the first region are higher than the potentials of the source lines included in the first region, and the first and second IO lines and source lines included in the second region are It is characterized by being on a coin.

1 is a diagram of a memory array and sense amplifier of the present invention.

Fig. 2 is a block diagram of a chip structure and a memory block of the semiconductor memory device of the present invention.

3 is a layout of the memory array and its cross-sectional view.

4 is a circuit diagram of a sub word driver and a sub word driver array.

5 is a circuit diagram of a cross area.

6 is a circuit diagram of a main amplifier.

7 is a block diagram of a data bus at read time.

8 is an operational waveform diagram at the time of reading.

9 is a view of the continuation of the operation waveform at the time of reading;

10 is a block diagram of a data path at the time of writing.

11 is an operational waveform diagram at the time of writing.

12 is a view of the continuation of the operation waveform at the time of writing.

13 is a circuit diagram of a second sense amplifier.

14 is a circuit diagram of a third sense amplifier.

15 is a circuit diagram of a fourth sense amplifier.

16 is an operational waveform diagram of a third sense amplifier.

17 is a circuit diagram of a second main amplifier.

18 is a circuit diagram of a third main amplifier.

19 is a circuit diagram of a fourth main amplifier.

20 is a diagram of a connection method of a second local IO of the present invention;

21 is a diagram showing the second data path configuration of the present invention.

Fig. 22 is an operational waveform diagram at the time of reading in the second data path.

Fig. 23 is a block diagram of a column sense amplifier in conventional SRAM.

BRIEF DESCRIPTION OF DRAWINGS To describe the present invention in detail, it will be described according to the accompanying drawings. In addition, in the whole figure for demonstrating an Example, the thing with the same function attaches | subjects the same code | symbol, and the repeated description is abbreviate | omitted.

(First embodiment)

1 shows a memory array ARY and a sense amplifier SA of the present invention. In order to explain the function of the sense amplifier, a chip configuration of the semiconductor memory device of the present invention is shown in Fig. 2A. The entire chip CHIP may be broadly divided into a control circuit CNTL, an input / output circuit DQC, and a memory block BLK. A clock, an address, and a control signal are input to the control circuit from the outside of the chip, and the operation mode of the chip is determined and the predecode of the address is performed. The input / output circuit includes an input / output buffer, write data is input from the outside of the chip, and outputs read data to the outside of the chip.

The configuration of the memory block BLK is shown in FIG. 2B. In the memory block, a memory array ARY disposed on a plurality of arrays is disposed, and a sense amplifier sequence SAA, a sub word driver sequence SWDA, and a cross area XP are arranged around the memory block. In the outer periphery of the block, the column decoder YDEC and the main amplifier column MAA are arranged in parallel with the sense amplifier columns, and the row decoder XDEC and the array control circuit ACC are arranged in parallel with the sub word driver columns.

1 shows two memory arrays and a sense amplifier array therebetween. The sense amplifier SA of the present invention comprises a transfer gate TGC, a precharge circuit PCC, a restore amplifier CC, a write circuit WP, an amplification circuit, that is, a direct sense amplifier DSA. The transfer gate is a circuit for connecting between the sense amplifier and the memory array when the sense amplifier separation signal SHR is activated. The precharge circuit equalizes between paired bit lines when the precharge signal PC is activated to precharge to the bit line precharge level. The bit line precharge level is usually set to the midpoint VDL / 2 of the bit line amplitude VDL (the same level as or reduced with the power supply voltage VCC from the outside of the chip). When the twin cell method is used, the precharge level can be set to the high level (VDL) or the low level (VSS) of the bit line without using the dummy cell for generating the reference voltage. However, the direct sense amplifier described later has a high transfer conductance when the bit line level is near VDL / 2. Therefore, it is preferable to set the bit line precharge level to VDL / 2 for high speed operation. The restore amplifier drives the P-side common source line CSP to VDL and the N-side common source line CSN to VSS after a small read signal from the memory cell is generated on the bit line. The circuit which amplifies the higher voltage among the (BL, BLB) to VDL and the lower voltage to VSS.

The write circuit WP is a circuit which connects the write local IO line WLIO / WLIOB and the bit line pair when the write column select line WYS is activated. The WLIO is precharged to VBLR during standby to prevent current consumption in unselected sense amplifier strings. The direct sense amplifier DSA is a circuit for driving the read local IO line RLIO / RLIOB with a small signal generated on the bit line to transfer the signal. In standby, RLIO is precharged to the IO line precharge level (VPC). The direct sense amplifier common source line DSAS is precharged to the IO line precharge level VPC during standby, and is driven to VSS during the read operation.

In this sense amplifier, when the lead row select line (RYS) is activated, the DSAS is driven by VSS in the selected sense amplifier row, and the DSAS is maintained in the VPC in the non-selected sense amplifier row, so that only the selected sense amplifier is activated. This is advantageous in that current is not consumed in the non-selective sense amplifier train. In addition, in this amplifier, the size controlled by RYS between the MOS transistors MN0 and MN1 and the RLIO line is large (e.g., gate width of 4 mu m) which acts as a differential pair connected to the bit line by the gate ( For example, the gate width 1 mu m) MOS transistors MN2 and MN3 are inserted and separated. Therefore, in an unselected direct sense amplifier in which RYS is VSS, since the channel capacity of the differential pair is not seen from the RLIO line, the parasitic capacitance of the RLIO line can be reduced, and the parasitic capacitance is changed by the data pattern on the bit line. It can also prevent.

The memory array is composed of a plurality of memory cells MC. In this embodiment, the memory cell has a twin cell configuration consisting of two DRAM cells. The DRAM cell is composed of one MOS transistor and one capacitor, one source or drain of the MOS transistor is connected to the bit line, the other source or drain is connected to the accumulation node SN, and the gate is a word line. Is connected to. One terminal of the capacitor is connected to the accumulation node SN, and the other terminal of the capacitor is connected to the plate electrode PL in common with the other cell. The twin cell connects two DRAM cells to a common word line and a paired bit line, writes complementary data into an accumulation node of each cell, and stores information. Hereinafter, the present invention will be described using a twin cell, but the sense amplifier of the present invention can be applied even when one DRAM cell is used as a memory cell. In this manner, the use of the twin cell almost doubles the signal amount of the bit line compared with the case of using only one DRAM cell. In the case of using the direct sense amplifier as shown in Fig. 1, since the signal generated from the memory cell can be converted into a current difference from the direct sense amplifier and read out to the local IO line without amplifying the signal for the restore amplifier, The amount of signal read out to the local IO line increases. Therefore, the combination of the direct sense amplifier and the twin cell system enables higher speed.

FIG. 3A shows the layout of the memory array, and FIG. 3B shows a sectional view taken along the line AA ′ thereof. The DRAM cell has an N-channel MOS transistor formed in the substrate PW and a stack capacitor formed on the bit line BL. The active region of the MOS transistor is shown as ACT, the word line as WL, and the N type diffusion layer region as N. The active region is separated by the insulator SiO ₂ . A contact CB is disposed on the diffusion layer, and a bit line contact BC or an accumulation node contact SC is disposed on the contact layer. The bit line BL is disposed in the direction orthogonal to the word line on the bit line contact. A concave accumulation node SN is disposed on the accumulation node contact. The plate electrode PL is embedded inside the accumulation node, and these constitute a capacitor with the capacitor insulating film CI interposed therebetween. This memory array is an open memory array in which DRAM cells are connected at intersections of all bit lines and word lines, and word lines can be reduced to 2F (F: minimum machining dimension) and bit line pitch to 3F. In this embodiment, two DRAM cells are used as one memory cell to form a twin cell type memory cell. However, two adjacent DRAM cells such as MCa are paired, and two DRAM cells separated such as MCb are paired. There is a case. If a twin cell is formed using two such intersection cells, the cell size becomes 12F2 power, and the area can be reduced as compared with the case of using two two intersection cells. In addition, since the bit lines paired with each other can be arranged on the same array differently from the normal one intersection cell, there is an advantage in that noise at the time of a problem in the one intersection cell does not occur.

FIG. 4 shows a circuit diagram of the sub word driver SWD and the sub word driver array SWDA formed by plural arrangement thereof. The sub word driver consists of two N-channel MOS transistors and one P-channel MOS transistor. In one N-channel MOS transistor, a main word line MWLB is connected to a gate, a word line WL is connected to a drain, and a ground potential VSS is connected to a source. In the other N-channel MOS transistor, the complementary word driver select line FXB is connected to the gate, the word line WL is connected to the drain, and the ground potential VSS is connected to the source. In the P-channel MOS transistor, a main word line MWLB is connected to a gate, a word line WL is connected to a drain, and a word driver select line FX is connected to a source. As shown in the figure, four sets of FX are wired on one SWDA, and one WL is activated by selecting any one of four SWDs selected from one MWLB. In addition, a main IO line pair MIO / MIOB is wired over or adjacent to the sub word driver column.

The circuit diagram of the cross area XP is shown in FIG. The cross area includes SHR signal driver (SHD), RLIO line precharge circuit (RPC), lead gate (RGC), DSAS line driver (DSAD), WLIO line precharge circuit (WPC), light gate (WGC), CS line driver (CSD), CS line precharge circuit (SPC), PC signal driver (PCD), and FX line driver (FXD). The SHR signal driver receives the complementary signal SHRB of the sense amplifier separation signal SHR and outputs the SHR. The RLIO line precharge circuit precharges the RLIO line to the VPC when the read enable signal RE is at an inactive VSS level. The lead gate is a circuit for connecting the RLIO line and the main IO line (MIO / MIOB) when the RE is an active VCL (used as a power supply voltage for the peripheral circuit at the same level as the external VCC level or stepped down). At this time, if the VPC is set to VCL / 2, even if the read gate is composed only of NMOS, the ON current of the NMOS can be taken large, so that the load on the MIO can be made smaller than that of the CMOS configuration, and the signal on the MIO line is increased. It is possible. In addition, even if the VPC is VCL / 2, if the threshold value of the NMOS used in the direct sense amplifier is lowered, there is no problem in operation. The DSAS line driver is a circuit that precharges the DSAS to the VPC when the RE is inactive and drives to the VSS when activated. By arranging the DSAS line driver in the cross area in this manner, the DSAS line can be activated on a mat basis, so that the direct sense amplifier can be activated only on the selected mat, and power consumption can be reduced. In addition, compared with the case where the DSAS line driver is concentrated in the array control circuit (ACC) part in FIG. 2, the disparity of the potential on the DSAS line is reduced due to the effect that the driver is distributedly arranged. There is an advantage that can reduce the variation in the sense speed according to the place.

The WLIO line precharge circuit precharges the WLIO line to VDL / 2 when the write enable signal WE is at an inactive VSS level. The write gate is a circuit for connecting the WLIO line and the main IO line (MIO / MIOB) when the WE gate is at the VCL level in the active state. With this CMOS configuration, it is possible to output the VCL level and the VSS level without decreasing the amplitude when writing from the MIO line to the WLIO line. The CS line driver drives the P-side common source line CSP to VDL (H level of the bit line) and the N-side common source line CSN to VSS when the sense amplifier enable signal SE is active. It is a circuit. The CS line precharge circuit SPC is a circuit which precharges CSP and CSN to VDL / 2 when the precharge signal PC is activated. The complementary signal PCB of the precharge signal PC is input to the PC signal driver and outputs the PC. The complementary signal FXB of the FX line is input to the FX line driver, and an FX is output.

6 shows the main amplifier circuit MA. The main amplifier consists of MIO precharge circuit (IPC), load circuit (LD), transfer gate (TGC), MA precharge circuit (APC), latch circuit (LTC), GIO buffer (GB) and write buffer (WB). . The MIO precharge circuit precharges the MIO line to the VPC when the MIO precharge signal IP is activated. The load circuit functions as a load in the MIO line when the transfer gate control signal TG is activated and the complementary signal TGB becomes VSS. The transfer gate conducts when TG is activated, and connects the MIO and the latch circuit. The main amplifier precharge circuit precharges the inside of the main amplifier to the VPC when the main amplifier precharge signal AP is activated. The latch circuit is a circuit for amplifying and holding a small amplitude signal input from the MIO to the full amplitude (VCL, that is, the power supply potential, or VSS) when the latch signal LT is activated. The GIO buffer is a circuit that outputs the data held in the latch circuit to the read global IO line (GIOR) when the GIO buffer enable signal (GBE) is activated. The write buffer WB is a circuit that outputs data on the write global IO line GIOW to MIO / MIOB when the write buffer enable signal WBE is activated.

In order to show the read operation in FIG. 7, a block diagram is shown with attention to two memory arrays ARY0 and ARY1 and three sense amplifier sequences SAA0 to SAA2, which are part of FIG. In this figure, the lead column select line RYS is connected to one direct sense amplifier DSA in all sense amplifier rows, but RYS may be connected to a plurality of direct sense amplifiers. In this case, it is necessary to increase the lead LIO pair by that much. In addition, two pairs of MIO0 / MIOB0 and MIO1 / MIOB1 are alternately connected to the lead gate circuit in the cross area. Therefore, when the word lines WL0 and RYS0 are activated, data is read into the sense amplifier strings SAA0 and SAA1, and these data are read into MIO0 / MIOB0 and MIO1 / MIOB1 through RLIO0 / RLIOB0 and RLIO1 / RLIOB1, respectively.

A read operation is shown using the operation waveform of FIG. 8. When the read command RD is input from the outside of the chip, the sense amplifier separation signal SHR and the precharge signal PC are deactivated in the sense amplifier strings SAA0 and SAA1 designated by the address. In addition, the read enable signal RE is activated to drive the direct sense amplifier common source lines DSAS0 and DSAS1 to VSS. Here, when RYSO is activated by the column decoder, the direct sense amplifiers are activated in the sense amplifier strings SAA0 and SAA1. At this time, in the non-selective sense amplifier string SAA2, since RLIO2 / RLIOB2 and DSAS2 are coincident with the VPC, no penetrating current flows. Similarly, the other unselected sense amplifiers do not flow through the current, and the current consumption is reduced. In addition, the coin position here means that the potential difference between RLIO2 / RLIOB2 and DSAS2 is such that the direct sense amplifier to which these wires are connected does not start. In addition, the current consumption can be reduced by setting both the RIO2 / RIO2B and the DSAS to a voltage higher than the threshold voltage of the NMOS used for the DSAS from the bit line potential VDL / 2. As is clear from the block diagram of Fig. 1, since RYS is connected to many sense amplifier trains, this circuit system is effective for reducing the operating current. Also, the absolute value of the potential difference between the RLIO / RIOB and the common source line DSAS connected to the selected sense amplifier string is greater than the absolute value of the potential difference between the RLIO / RIOB and the common source line DSAS connected to the unselected sense amplifier string. It is also possible to enlarge and to prevent the fall of the penetration current. In this manner, the current flowing between the source and the drain of the transistor connecting the unselected sense amplifier and the bit line is less than the current flowing between the source and the drain of the transistor connecting the selected sense amplifier and the bit line. The same effect can be obtained.

When the main word line MWLB is lowered to VSS in the row decoder and FX is activated in the array control circuit ACC, the selected word line WL0 is activated to VPP. In the memory cell selected by the word line WL, the cell transistor is turned on so that a signal is read out on the bit line BL. Since the memory cell has a twin cell configuration, one of the BL / BLB is higher than the precharge level of the bit line, and the other is low. In response to the signal on the bit line, a direct sense amplifier drives the RLIO / RLIOB so that a voltage difference appears in the RLIO / RLIOB. This signal is transmitted to the MIO / MIOB because the lead gate is in a conductive state in the cross area by the RE. In this embodiment, the word line WL is activated after RYS0 is activated and DSASO and DSAS1 are driven to VSS. However, it is also possible to raise WL before driving RYSO, DSASO, and DSAS1. As a result, the operating margin can be reduced compared to that of a normal sense amplifier.

This following operation is explained in FIG. Since the transfer gate control signal TG is activated almost at the same time as the RE is activated, the signal on the MIO is input to the latch in the main amplifier. At a timing when the signal is sufficiently large at the input of the latch, the TG is deactivated, the latch signal LT is activated, and data is confirmed and retained. Thereafter, the GIO buffer enable signal GBE is activated to transmit data to the output circuit DQC through the read global IO line GIOR, and output the data to the DQ. After the data is confirmed in the latch, precharging is started for the RLIO line pair, MIO line pair, and DSAS line used for reading.

At the same time as reading the data after the direct sense amplifier, a rewrite operation is performed in the memory array. As shown in Fig. 8, when the P-side common source line CSP is driven by VDL and the N-side common source line CSN is driven by VSS, the restoring amplifier CC in the sense amplifier drives the bit line to VDL or VSS. Amplify. The word line is deactivated to VSS at the timing at which data is sufficiently written into the memory cell. In the sense amplifier row, the PC and SHR are activated, and the bit line and the common source line are precharged to terminate the read cycle. Therefore, when the direct sense amplifier is used, data readout and memory array rewrite operation can be performed in parallel, so that the direct sense amplifier starts up faster than the word line is activated, thereby speeding up the data readout. The word line is activated by the restore amplifier, and after the signal from the memory cell is sufficiently generated on the bit line, the amplifier can be started and a reliable rewrite operation can be performed.

In order to show write operations in FIG. 10, a block diagram is shown with attention to two memory arrays ARIO and ARY1 and three sense amplifier sequences SAA0 to SAA2, which are part of FIG. In the drawing, the write column select line WYS is connected to one write circuit WP in all sense amplifier columns, but WYS may be connected to a plurality of write circuits. In this case, it is necessary to increase the write LIO pair by that amount. Further, two pairs of MIO0 / MIOB0 and MIO1 / MIOB1 are alternately connected to the write gate circuit in the cross area. Thus, when the word lines WL0 and WYS0 are activated, the data on MIO0 / MIOB0 and MIO1 / MIOB1 are transferred from the write circuits in the sense amplifier strings SAA0 and SAA1 via WLIO0 / WLIOB0 and WLIO1 / WLIOB1, respectively, to the data lines and memory cells of the memory array. Is filled in.

The write operation is shown using the operation waveform of FIG. When the write command WT is input from the outside of the chip, write data is obtained from the DQ and output to the write global IO line GIOW. When the MIO precharge signal IP is deactivated and the write buffer enable WBE is activated, write data is output to the MIO line.

The subsequent array operation is described in FIG. When the write command WT is input from the outside of the chip, the sense amplifier separation signal SHR and the precharge signal PC are deactivated in the sense amplifier strings SAA0 and SAA1 designated by the address. Further, the write enable signal WE is activated to conduct the write gate in the cross area, and write data is written from the MIO / MIOB to the WLIO / WLIOB. When WYS0 is activated by the column decoder, writing to the bit lines of the memory array is started. At this time, since WLIO2 / WLIOB2 is VDL / 2 in the unselected sense amplifier string SAA2, even if they are connected to the bit line, no current flows because the bit line is coincident with the bit line. The same is true for other non-selective sense amplifier trains. As apparent from the block diagram of Fig. 1, since the WYS is connected to many sense amplifier trains, this circuit system is effective for reducing the operating current.

When the main word line MWLB falls to VSS in the row decoder and FX is activated in the array control circuit ACC, the selected word line WL0 is activated to VPP. In the memory cell selected by the word line WL, the cell transistor is turned on to write data from the bit line to the memory cell. When the P-side common source line CSP is driven by VDL and the N-side common source line CSN is driven by VSS, the restore amplifier CC in the sense amplifier amplifies the bit line by VDL or VSS. When data writing to the memory array ends, WE is deactivated, the WLIO and MIO are disconnected, and the WLIO and MIO are precharged. The word line is deactivated to VSS at the timing at which data is sufficiently written into the memory cell. In the sense amplifier string, the PC and SHR are activated, precharging the bit line and the common source line ends the write cycle.

13 shows a second sense amplifier SA circuit. In this sense amplifier, two SAs share a set of direct sense amplifiers DSA and write circuit WP. For this reason, selecting means such as a multiplexer (MUX) is added, and which one of the two SAs is connected to the RLIO / RLIOB or the WLIO / WLIOB, depending on which of S0 and S1 is selected. The circuits and operations of the transfer gate TGC, the precharge circuit PCC, the restore amplifier CC, the write circuit WP, and the direct sense amplifier DSA are the same as those shown in FIG. In this sense amplifier, in addition to the same effects as the sense amplifier of FIG. 1, since the direct sense amplifier (DSA) can be arranged in the area of two sense amplifiers, the size of the MOS transistor in the direct sense amplifier (DSA) can be increased. Thus, the amount of signals read into the RLIO / RLIOB and MIO / MIOB can be increased. Adding a multiplexer in the sense amplifier in this manner increases the load capacity of the bit line, thereby reducing the signal amount of the bit line. In the present invention, however, since twin cells are used as shown in the drawing, the signal amount of the bit line is about twice as large as that of using one conventional DRAM cell, and the amount of bit line signal due to the addition of a multiplexer There is an advantage that the effect of the reduction is small.

14 shows a third sense amplifier SA circuit. In this sense amplifier, the selection line YS is used as a lead and a light. For this reason, the MOS transistor controlled by the write enable signal WE is connected in series with the MOS transistor controlled by the column select line in the write circuit WP. Since the WE is deactivated during the read operation, the sense amplifier and the WLIO / WLIOB are not connected even when the column select line YS is activated. The circuits and operations of the transfer gate TGC, the precharge circuit PCC, the amplifier for restoration CC, and the direct sense amplifier DSA are the same as those shown in FIG. In this sense amplifier, in addition to the same effect as the sense amplifier of FIG. 1, the number of column select lines can be halved compared to the sense amplifier of FIG. 1, so that the wiring pitch is increased to facilitate the process or to increase the number of power lines. This makes it possible to speed up the sense amplifier operation.

15 shows a fourth sense amplifier SA circuit. In this sense amplifier, in the sense amplifier of FIG. 14, the MOS transistors MN2 and MN3 controlled by the column select line YS in the direct sense amplifier DSA and the MOS transistors MN0 and MN1 connected to the gates of the bit lines are connected. The equalized MOS transistor MN4 is connected between the connection points N0 and N1. This MOS transistor conducts when the precharge signal PC is activated, and shorts between N0 and N1. The operation waveform of the sense amplifier of FIG. 14 without MN4 is shown in FIG. Note that a sense amplifier in which YS is unselected in the read operation, N0 and N1 are VSS when the DSAS is driven at VSS. If the DSAS is returned to the VPC while the bit lines BL and BLB are amplified to VDL and VSS, the N0 is turned on and the MN1 is turned off, so that N0 is VPC, but N1 remains VSS. When precharging the bit lines, N0 remains the VPC, but N1 rises only to VDL / 2-VT since the gate of MN0 is VDL / 2. Here, VT is the threshold voltage of MN1. Therefore, a potential difference occurs between N0 and N1 while the bit line is precharged. In the next read cycle, when DSAS is driven to VSS, N0, N1 drops again to VSS, at which time the coupling voltage returning to the bit line through MN0, MN1 is unbalanced to BL and BLB, Noise to the amplifier. In the sense amplifier of FIG. 15 to which the equalized MOS transistor MN4 is added, the potential difference between N0 and N1 at the time of precharge can be eliminated, so that noise during operation can be reduced and stable circuit operation can be realized.

In the sense amplifier of FIG. 15, the MOS transistors MN7 and MN8 controlled by the column select line YS and the MOS transistors MN5 and MN6 controlled by the write enable signal WE in the write circuit WP. The equalized MOS transistor MN9 is connected between the connection points N2 and N3. This MOS transistor conducts when the precharge signal PC is activated, and shorts between N2 and N3. In the sense amplifier of FIG. 14 without MN9 installed, if WE returns to VSS while the bit lines BL and BLB are amplified to VDL and VSS during the write operation, N2 and N3 are in the state of VDL and VSS. Left. Since the charges accumulated in these nodes are retained even when the bit line is precharged, when WE is activated in the next write cycle, the electric charges are discharged to BL and BLB to generate positive noise. Therefore, by adding the equalized MOS transistor MN9, noise during operation can be reduced, and stable circuit operation can be realized. In the case of the sense amplifier shown in Fig. 14, MN9 does not need to be connected if WE is activated during precharging and only deactivated during read operation. In this case, however, unless WE is deactivated sooner than the word line is activated, the read signal from the memory cell flows out to the LIO through MN5 to 8 in the bit line in which YS is selected. Therefore, in the sense amplifier of FIG. 15, if WE is deactivated during precharging and only during write operation, the timing margin during operation is alleviated.

In addition, although FIG. 15 shows the case where the column select line connected to the direct sense amplifier DSA and the column select line connected to the write circuit WP are common, the same effect is obtained even if these are separated. Even in this case, MN5 and MN6 are required to perform the light mask operation of stopping the light in the sense amplifiers of some of the sense amplifiers selected by WYS and DSAS during the write operation. It is available to install.

17 shows a second main amplifier circuit MA. The main amplifier includes an MIO precharge circuit (IPC), a load circuit (LD), a MA precharge circuit (APC), a latch circuit (LTC), a GIO buffer (GB), and a write buffer (WB). The MIO precharge circuit precharges the MIO line to the VPC when the MIO precharge signal IP is activated. The load circuit functions as a load in the MIO line when the lead enable RE is activated and the REB becomes VSS. The main amplifier precharge circuit precharges the output node of the latch to VCL (power supply potential) when the complementary main amplifier precharge signal ABB becomes VSS. The latch circuit is a circuit for amplifying and retaining a small amplitude signal input from the MIO to the full amplitude (VCL or VSS) when the latch signal LT is activated. The latch circuit of this main amplifier uses a gate input amplifier and a cross couple differently from the latch circuit in the main amplifier of FIG. Therefore, there is an advantage that the input capacitance seen from the MIO line becomes small, the input signal of the main amplifier is taken large, and the operation speed is high. On the other hand, if the MIO level is too low, the conductance of the MOS transistor input to the gate of the MIO decreases and the operation speed is slowed. Therefore, the first main amplifier of FIG. 6 is advantageous in terms of operation margin. The configuration of the GIO buffer and the write buffer WB is similar to that of the main amplifier of FIG.

18 shows a third main amplifier circuit MA. In this main amplifier, only the positions of the load circuit LD and the transfer gate TGC are changed in the first main amplifier circuit of FIG. 6, and the other circuits are completely the same. Thus, when the load circuit is formed inside the transfer gate of the N-type MOS transistor with respect to the main IO, they act as a gate ground amplifier. Therefore, the signal difference at M10 / MIOB0 is amplified and transferred to the inputs LN and LNB of the latch. Therefore, the input signal of the latch circuit becomes large, which has the advantage of the operation speed of the latch and the expansion of the operation margin.

19 shows a fourth main amplifier circuit MA. In this main amplifier, the gate ground amplifier GA in the third main amplifier circuit of FIG. 18 is combined with the latch circuit LTC of FIG. In addition, a source follower circuit SF is provided between LTC and GA to perform impedance conversion. In this circuit, not only the input signal can be pre-amplified by the gate ground amplifier, but also the input capacitance of the latch-type amplifier is small, so that the signal amount can be large, and the margin can be operated at high speed. In addition, by providing a source follower circuit, the coupling noise applied to the input terminal from the differential MOS transistor of the latch amplifier when the latch amplifier is started can be reduced. In this main amplifier, since the input / output of the latch amplifier LTC is separated, it is possible to precharge the output node of the latch amplifier to VCL. Therefore, the gate of the NMOS in the GIO buffer is cut off from VSS. Therefore, if LT is input and GBE is activated by activating the GIO buffer before the latch enters the data, the GIO buffer can be driven only by the timing of the latch. It is possible to speed up access.

(2nd Example)

20 shows the connection method of the second local IO of the present invention. With this connection method, in the case where the direct sense amplifier DSA and the write circuit WP are connected to different local IO lines in one sense amplifier SA, two sets of LIO line pairs are used for one sense amplifier. Two bits of data can be read from both the amplifier and the read and write stages.

For this purpose, the sense amplifier is divided into group a and group b in the center of one sense amplifier array (SAA). In the group a, the write circuit WP is connected to one local IO line pair LIO0 / LIO0B, and the direct sense amplifier DSA is connected to the other local IO line pair LIO1 / LIOB1. In contrast to group b, the write circuit WP is connected to the local IO line pair LIO1 / LIOIB, and the direct sense amplifier DSA is connected to the other local IO line pair LIO1 / LIOB1.

When RYS is activated one by one from the groups a and b at the time of read, the data from the sense amplifiers of group a is read into LIO1 and LIOB1, and the data from the sense amplifiers of group b is read into LIO0 and LIOB0. When writing, one WYS is activated from each of the groups a and b, and data can be written to the sense amplifiers of group a using LIO0 and LIOB0, and data can be written to the sense amplifiers of group b using LIO1 and LIOB1. I can write it. In contrast, when a plurality of RYSs are activated in FIG. 7, data read from a plurality of sense amplifiers collide on the same LIO. In addition, in the case of activating a plurality of WYS in FIG. 10, the same data is written to the plurality of sense amplifiers. Therefore, according to the local IO connection method of the present invention shown in FIG. 20, the number of bits that can be read or written from one sense amplifier string can be doubled without increasing the number of wirings of the LIO lines.

(Third Embodiment)

21 shows a second data path configuration of the present invention. In the data path of the present invention, by providing the offset compensation sub-amplifier at the connection portion between the local IO line and the main IO line, the offset of the direct sense amplifier can be compensated without giving the offset compensation to the direct sense amplifier itself. The memory array ARY and the sense amplifier SA are as shown in Fig. 1, but only a part of them is extracted. What is different in the present invention is the provision of the sub amplifier BA in the cross area XP. Other circuits in the cross area are the same as those in FIG. 5 and are omitted in FIG.

The operation waveform of FIG. 22 is used to illustrate the operation of the data path of the present invention. When the read command RD is input, the precharge signal PC is deactivated to VSS. Almost simultaneously with this, the read enable signal RE is activated to VCL and REB to VSS, and the sub amplifier BA is activated. In addition, the DSAS is driven from the VPC to the VSS to activate the direct sense amplifier (DSA). At this time, since the bit line serving as the input of the DSA is still precharged to VDL / 2, when the lead row select line RYS is activated, the signal corresponding to the offset of the direct sense amplifier is applied to the lead local IO line RLIO / RLIOB. Occurs. At this point, the compensation signal CP is VCL, and the input terminals GT and GB of the sub-amplifier connected to the LIO and the decoupling capacitor are short-circuited with the output terminal and fixed at the offset compensation potential. The offset of the sub amplifier itself is compensated at this point.

Subsequently, the CP is deactivated to VSS, the sub amplifier is amplified, and the word line WL is activated to generate a signal from the memory cell between the bit lines BL / BLB. The direct sense amplifier amplifies this and outputs a signal to RLIO and RLIOB. At this time, the GT and GB generate a signal through the decoupling capacitor, and thus a voltage obtained by adding the variation of RLIO and RLIOB to the offset compensation potential is generated. Therefore, since a signal is generated based on the potential difference between RLIO and RLIOB at the time when CP falls to VSS, a substantial RLIO signal can be obtained by removing the offset of the direct sense amplifier. Thus, the offset of the direct sense amplifier is compensated. The sub amplifier amplifies the potential difference between GT and GB and outputs it to MIO and MIOB.

In order to perform offset compensation in this manner, a decoupling capacitance and a pass transistor are required. However, when this is provided in each direct sense amplifier, the area of the sense amplifier becomes very large. Using the data path structure of the present invention, the operating margin when reading out can be increased while keeping the chip size small.

The present invention described above can be used as a high speed random access memory such as DRAM and SRAM, in particular, a memory for transferring a signal read out from a memory cell to a bit line from a gate input amplifier to a peripheral circuit at high speed. However, even in nonvolatile memories such as FLASH, FERAM, and MRAM, the present invention can be used to speed up reading. In addition, in on-chip memory embedded in logic chips such as microprocessors and DSPs, the speed of access time accompanying the improvement of the clock frequency is required. Therefore, the demand for speed improvement is stronger than that of a single memory. It is valid to apply.

As mentioned above, although the invention made by this inventor was demonstrated concretely based on the Example, this invention is not limited to the said Example, Of course, various changes are possible in the range which does not deviate from the summary.

The main effects obtained by the present invention are as follows.

First, since the direct sense amplifier can be selectively activated in the random access memory, the power consumption during the read operation can be greatly reduced. In addition, since the load capacity of the local IO line can be reduced at that time, the read speed can be increased. In addition, the data pattern dependency of the load capacity of the local IO line in the read operation is reduced, so that the test after manufacture is facilitated.

Secondly, noise in the direct sense amplifier at the time of high speed operation is reduced, and the operating margin is expanded. Third, it is possible to double the number of bits read from one memory array without increasing the chip size.

The present invention can be used in high-speed random access memories such as DRAM and SRAM, particularly in a memory that transfers signals read out from a memory cell to a bit line from a gate input amplifier to a peripheral circuit at high speed. The present invention can also be used to speed up reading even in nonvolatile memories such as FLASH, FERAM, and MRAM. In addition, the present invention can be applied not only to a memory single chip but also to an on-chip memory embedded in a logic chip such as a microprocessor or a DSP.

Claims (15)

A word line extending in a first direction, first and second bit lines extending in a second direction crossing the first direction, a memory cell connected to the word line and the first and second bit lines, and the memory First and second regions each having an amplifier circuit for amplifying information read from a cell, first and second IO lines for receiving information read from the amplifier circuit, and source lines for controlling the amplifier circuit, respectively; A semiconductor memory device having a column select line connected in common to the first and second regions and extending in the second direction, The amplifier circuit includes first to fourth MOS transistors, A gate of the first MOS transistor is connected to the first bit line, a gate of the second MOS transistor is connected to the second bit line, and sources of the first and second MOS transistors are connected to the source line, , A drain of the third MOS transistor is connected to the first IO line, a drain of the fourth MOS transistor is connected to the second IO line, Gates of the third and fourth MOS transistors included in the amplifier circuits provided in the first and second regions are commonly connected to the column select lines. A drain of the first MOS transistor is connected to a source of the third MOS transistor, The drain of the second MOS transistor is connected to the source of the fourth MOS transistor, In the first state, the potentials of the first and second IO lines included in the first region are higher than the potentials of the source lines included in the first region, and the first and second IO lines and source included in the second region. The line is a coin-operated semiconductor memory. A word line extending in a first direction, first and second bit lines extending in a second direction crossing the first direction, a memory cell connected to the word line and the first and second bit lines, and the memory First and second regions each having an amplifier circuit for amplifying information read from a cell, first and second IO lines for receiving information read from the amplifier circuit, and source lines for controlling the amplifier circuit, respectively; A semiconductor memory device having a column select line connected in common to the first and second regions and extending in the second direction, The amplifier circuit includes first to fourth MOS transistors, A gate of the first MOS transistor is connected to the first bit line, a gate of the second MOS transistor is connected to the second bit line, and sources of the first and second MOS transistors are connected to the source line, , A drain of the third MOS transistor is connected to the first IO line, a drain of the fourth MOS transistor is connected to the second IO line, Gates of the third and fourth MOS transistors included in the amplifier circuits provided in the first and second regions are commonly connected to the column select lines. A drain of the first MOS transistor is connected to a source of the third MOS transistor, A drain of the second MOS transistor is connected to a source of the fourth MOS transistor, In the first state, the potentials of the first and second IO lines included in the first region are higher than the potentials of the source lines included in the first region, The potential of the first and second IO lines and the source line included in the second region is an absolute value of a value obtained by subtracting the threshold voltages of the first and second MOS transistors from the potentials of the first and second bit lines. store. The method according to claim 1 or 2, In the first state, the semiconductor memory device reads information from the memory cells included in the first area. The method according to claim 1 or 2, The first region includes a plurality of the amplifier circuits, and a source line driver for driving the source lines. The plurality of amplifier circuits included in the first region are commonly connected to the source line, And the source line driver is disposed in a region surrounded by a sense amplifier string including the plurality of amplifying circuits and a word driver string including a plurality of word drivers for driving the word lines. The method according to any one of claims 1 to 4, The plurality of amplifier circuits are commonly connected to the first and second IO lines, And a second amplifier circuit for compensating offsets of the plurality of amplifier circuits is connected to the first and second IO lines. The method according to claim 1 or 2, The amplifier circuit further includes a fifth MOS transistor, The source of the fifth MOS transistor is connected with the drain of the second MOS transistor, the drain of the fifth MOS transistor is connected with the drain of the first MOS transistor, and the gate of the fifth MOS transistor is a precharge signal. Semiconductor memory controlled. The method according to claim 1 or 2, The first region further includes a write circuit for writing information into the memory cell, a write column select line for selecting the write circuit, a write control signal line for controlling the write circuit, and a pair of write IO lines connected to the write circuit. Equipped, The write circuit further includes sixth to ninth MOS transistors, Gates of the sixth and seventh MOS transistors are connected to the write column select line, a drain of the sixth MOS transistor is connected to one of the write IO line pairs, and a drain of the seventh MOS transistor is connected to the write IO line pairs. Connected to the other side of Gates of the eighth and ninth MOS transistors are connected to the write control signal line, a source of the eighth MOS transistor is connected to the first bit line, and a source of the ninth MOS transistor is connected to the second bit line; , And a source of the sixth MOS transistor is connected to a drain of the eighth MOS transistor, and a source of the seventh MOS transistor is connected to a drain of the ninth MOS transistor. The method of claim 7, wherein And the write column select line is connected to the column select line. The method according to claim 7 or 8, The write circuit further includes a tenth MOS transistor, The source of the tenth MOS transistor is connected with the source of the sixth MOS transistor, the drain of the tenth MOS transistor is connected with the source of the seventh MOS transistor, and the gate of the tenth MOS transistor is a precharge signal. Semiconductor memory controlled. A word line extending in a first direction, a plurality of pairs of bit lines extending in a second direction crossing the first direction, a plurality of memory cells connected to the word line and the plurality of bit line pairs, and reading from the memory cell An amplifying circuit for amplifying the information to be output, first and second IO lines for receiving information read from the amplifying circuit, a source line for controlling the amplifying circuit, and selection means for selecting a signal input to the amplifying circuit; First and second regions each having, A semiconductor memory device having a column select line connected in common to the first and second regions and extending in the second direction, The amplifier circuit includes first to fourth MOS transistors, Gates of the first and second MOS transistors receive input from the selection means, sources of the first and second MOS transistors are connected to the source lines, A drain of the third MOS transistor is connected to the first IO line, a drain of the fourth MOS transistor is connected to the second IO line, Gates of the third and fourth MOS transistors respectively included in the amplifier circuit are connected to the column select line in common. A drain of the first MOS transistor is connected to a source of the third MOS transistor, A drain of the second MOS transistor is connected to a source of the fourth MOS transistor, And said selecting means is a semiconductor memory device to which signals of said plurality of bit line pairs are input. The method of claim 10, In the semiconductor memory device, in the first state, the potentials of the first and second IO lines included in the first region are higher than the potentials of the source lines included in the first region, The potential of the first and second IO lines and the source line included in the second region is equal to or greater than the absolute value of the potential of the plurality of bit line pairs included in the second region minus the threshold voltage of the third and fourth MOS transistors. store. The method according to claim 10 or 11, wherein The memory cell has two transistors and two capacitors, And said selecting means is a multiplexer. A plurality of bit lines extending in a first direction, a plurality of bit lines extending in a second direction crossing the first direction and including first and second bit lines, and a plurality of bit lines connected to the word line and the plurality of bit lines First and second circuit strings each including a memory cell, an amplifier circuit for amplifying information read from the memory cell, and a write circuit for writing information to the memory cell, and connected to the circuit string in the first direction. First and second regions each having an extended first and second IO line pairs and a source line connected to the amplifying circuit; A semiconductor memory device comprising first and second read column selection lines and first and second write column selection lines that are commonly connected to the first and second regions. The first and second read column selection lines and the first and second write column selection lines extend in the second direction, Each of the amplifying circuits provided in the first and second circuit strings includes first to fourth MOS transistors, A gate of the first MOS transistor is connected to the first bit line, a gate of the second MOS transistor is connected to the second bit line, and sources of the first and second MOS transistors are connected to the source line Become, A drain of the first MOS transistor is connected to a source of the third MOS transistor, A drain of the second MOS transistor is connected to a source of the fourth MOS transistor, The drain of the third MOS transistor of the amplifier circuit included in the first circuit string is connected to one of the first IO line pairs connected to the write column select line included in the second circuit string, and the drain of the fourth MOS transistor is Connected to the other side of the first IO line pair connected with the write circuit included in the second circuit row, The drain of the third MOS transistor of the amplifying circuit included in the second circuit string is connected to one of the second IO line pairs connected to the write circuit included in the first circuit string, and the drain of the fourth MOS transistor is the second. Connected to the other side of the second IO line pair connected with the write circuit included in the one circuit column, A write circuit included in the first circuit column is connected to the first write column select line; The write circuit included in the second circuit column is connected to the second write column select line, Gates of the third and fourth MOS transistors of the amplification circuit of the first circuit sequence included in the first region, and gates of the third and fourth MOS transistors of the amplification circuit of the first circuit sequence included in the second region. Is commonly connected to the first read column selection line, Gates of the third and fourth MOS transistors of the amplification circuit of the second circuit string included in the first region, and gates of the third and fourth MOS transistors of the amplification circuit of the second circuit string included in the second region. Is commonly connected to the second read column selection line, In a first state, the first and second read column select lines are activated, The potential of the first and second IO line pairs included in the first region is higher than the potential of the source line included in the first region, The pair of first and second IO lines included in the second area and the source line are coincident or the potentials of the first and second IO lines included in the second area and the potential of the source line are the first and second lines. A semiconductor memory device having an absolute value obtained by subtracting threshold voltages of the first and second MOS transistors from the potential of a bit line. A semiconductor memory comprising a first amplifier circuit including first and second N-channel MOS transistors and first and second P-channel MOS transistors, and a second amplifier circuit for amplifying information read out from the memory cell to a power supply voltage amplitude. As a device, A gate of the first N-channel MOS transistor and a gate of the second N-channel MOS transistor are connected to a first power supply potential, a source of the first N-channel MOS transistor is connected to a first input terminal, and the second N A source of the channel MOS transistor is connected to the second input terminal, The gate of the first P-channel MOS transistor and the gate of the second P-channel MOS transistor are connected to a ground potential, and the source of the first P-channel MOS transistor and the source of the second P-channel MOS transistor are the first power source. Connected to the potential, A drain of the first N-channel MOS transistor is connected with a drain of the first P-channel MOS transistor, a drain of the second N-channel MOS transistor is connected with a drain of the second N-channel MOS transistor, And the first and second N-channel MOS transistors receive input of information read from the memory cell before the first and second P-channel MOS transistors. The method of claim 14, The semiconductor memory device further has a first circuit including third to sixth N-channel MOS transistors, A gate of the third N-channel MOS transistor is connected with a drain of the first P-channel MOS transistor, a gate of the fourth N-channel MOS transistor is connected with a drain of the second P-channel MOS transistor, A source of the third N-channel MOS transistor and a source of the fourth N-channel MOS transistor are connected to the second amplifier circuit, A drain of the third N-channel MOS transistor and a drain of the fourth N-channel MOS transistor are connected to the first power source potential, A gate of the fifth N-channel MOS transistor and a gate of the sixth N-channel MOS transistor are connected to a second power supply potential, A drain of the fifth MOS transistor and the sixth MOS transistor is connected to the second amplifier circuit, And a source of the fifth MOS transistor and a source of the sixth MOS transistor are connected to a ground potential.

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