JP4338045B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and relates to a technique for mounting a large capacity memory and a logic circuit on the same chip.

The list of documents referred to in this specification is as follows, and the documents are referred to by document numbers. [Reference 1]: Kiyoo Ito, “Ultra LSI Memory”, Baifukan, 1996, pp. 12-15. [Document 2]: Japanese Patent Laid-Open No. 62-226494 (corresponding US Patent Publication No. 4803664).
Ito Kiyoo "VLSI LSI" Baifukan, 1996, pp. 12-15 JP-A 62-226494

  Recently, a system-on-chip LSI in which a dynamic random access memory (DRAM) and a logic circuit (logic circuit) are combined has become important for multimedia applications. In the future, it will be necessary to incorporate DRAM, static random access memory (SRAM), logic circuits, and processors on a single chip. In such a system-on-chip LSI, the current DRAM memory cell composed of one transistor and one special large-capacity capacitor has the same capacitor formation process, and therefore the same logic circuit (logic). It is difficult to create DRAM in the process step. For this reason, there is a limit to reducing the price. Therefore, a DRAM memory cell that does not require a capacitor is required.

  As candidates for this, the inventors of the present application have begun to consider re-evaluating a so-called three-transistor cell as shown in [Document 1]. Here, the three-transistor cell includes a storage MOSFET that stores information voltage at the gate, a write MOSFET that writes the information voltage to the gate, and a read MOSFET that reads the state of the gate voltage. Such a three-transistor cell can be manufactured easily because the manufacturing process can be made substantially the same as that of the logic circuit, and there is a possibility that the cost can be reduced. Further, since the cell itself has an amplification function, the read signal voltage read to the data line is large and the operation is stable. Furthermore, the present inventor has found that the present invention has a feature that low power consumption suitable for multimedia use can be realized because it is suitable for low voltage operation.

  Further, a DRAM using a three-transistor cell is described in [Document 2]. Since this memory has a pair of data lines, high-speed writing / reading is possible. However, in order to discriminate and amplify the stored information of the memory cell with the sense amplifier, a dummy cell must be used for each data pair line, and the area increases accordingly. Further, since the dummy cell disclosed therein also has an amplification function, the reference voltage appearing on the data line changes with time. Therefore, it is difficult to set the start timing of the sense amplifier, and in some cases, the read information cannot be discriminated by the sense amplifier. This is because, if the start timing of the sense amplifier is set too late, the voltage difference between the paired wires becomes small and the operation becomes unstable.

  Accordingly, a first object of the present invention is to provide a memory that does not use dummy cells. Another object of the present invention is to balance the parasitic capacitance of the global data line pair to which the three-transistor cell is connected.

  A typical example of the present invention is as follows. That is, in the plurality of first memory cells, the gates of the first and second transistors are connected to one of the plurality of first word lines, and the drain of the third transistor is connected to the source / drain path of the second transistor. Is done. In the plurality of second memory cells, the gates of the fourth and fifth transistors are connected to one of the plurality of second word lines, and the drain of the sixth transistor is connected to the source / drain path of the fifth transistor. . The source / drain path of the first transistor of the first memory cell is connected to a first wiring, and the source / drain path of the fourth transistor of the second memory cell is connected to a second wiring. The source / drain path of the second transistor of the first memory cell is connected to the second wiring via a first switch, and the source / drain path of the fifth transistor of the second memory cell is connected via the second switch. Connected to the first wiring.

  The parasitic capacitance of the global data line pair can be balanced.

<Example 1>
FIG. 1A shows the concept of the present invention, and shows the configuration and operation timing of a pair of data lines in the DRAM. A plurality of memory cells (MC1 to MCn), a sense amplifier (SA), and a precharge circuit are connected to the pair of data lines (DL, DLB). The memory cell is a gain cell as will be described later. Here, for example, in an example using an N-type MOSFET as will be described later, a gain cell selectively discharges a data line precharged to a high potential VDD in advance to 0 V in accordance with stored information of the memory cell. It is a memory cell that can be used. Of course, a P-type MOSFET may be used, and in this case, it is a memory cell that can selectively charge a data line precharged to 0 V in advance to the VDD level. The data line includes a data line DL used for reading data in the memory cell and a data line DLB used for reference during differential amplification. DLB is also used for writing / rewriting data stored in memory cells. The feature of the present invention resides in that the precharge voltages of the paired wires are set to different values. That is, the DL precharge voltage is set to VDD when an N-type gain cell is used, for example, and the DLB precharge voltage is set to a lower value, for example, VDD / 2. Here, the sense amplifier is, for example, a latch type CMOS sense amplifier as shown in FIG. 2, and amplifies a differential voltage corresponding to information appearing between the data pair lines to VDD at high speed. The sense amplifier is activated by applying voltages of 0 V and VDD to the terminals SAN and SAP in FIG. 2A and to the terminals SPE and SNE in FIG. 2B, respectively.

The basic operation of the present invention will be described below with reference to FIGS. 1B and 1C in the case of an N-type gain cell. In order to read stored information from the memory cell, first, DL and DLB are precharged to VDD and VDD / 2 respectively by a precharge circuit, then the precharge signal PC is set to low level, and then one word line is selectively selected. Set to read level (WLR on in the figure). Thus, it is determined whether the potential of the data line DL is maintained at the precharge level or discharged to 0V according to the stored information of the memory cell. FIG. 1B is a waveform diagram when the memory cell holds stored information that discharges the data line DL. After a time (T1) when the voltage of the data line DL is reduced by Δ (sense amplifier sensitivity) from VDD / 2, the sense amplifier SA is activated to start amplification (SA on in the figure). As a result, DL is amplified to 0V and DLB is amplified to VDD at high speed. This Δ
Is almost 100 mV due to the offset voltage of the sense amplifier. On the other hand, FIG. 1C is a waveform diagram in the case where the selected memory cell holds stored information that keeps the data line DL at the precharge level. If the sense amplifier is activated after time T1, DL is amplified to VDD and DLB is amplified to 0V at high speed. That is, by activating the sense amplifier after time T1 after activating the word line WL, it is possible to accurately discriminate and read the stored information of the memory cell. In the figure, the difference in precharge voltage between the paired wires is VDD / 2, but this difference may be greater than or equal to Δ. If the difference in the precharge voltage between the paired wires is Δ, T1 is shortened, so that it can be amplified more quickly. Furthermore, if the precharge voltage of the data line DLB is set to Δ instead of VDD / 2, the read voltage difference between the paired lines for the binary information becomes equal. This condition gives the minimum value of the precharge voltage of the data lines DL and DLB, and the precharge voltage of the data line DL is lowered to 2Δ (approximately 200 mV). However, the advantages of setting the precharge voltage of the data line DLB to VDD / 2 are that the circuit design is facilitated and the precharge voltage level can be controlled with high accuracy. Therefore, the precharge voltage of the data pair lines (DLB and DL) may be determined based on the balance between speed requirements and circuit design difficulties. Note that, based on the precharge voltage condition described above, the minimum value of the operating voltage VDD can be lowered to 2Δ in principle. This is an example that does not necessarily require a sense amplifier. Therefore, if the requirement for the operation speed is satisfied, the operation voltage can be set to 2Δ, and a configuration without a sense amplifier can be provided.

  Writing to the memory cell can be performed by selectively setting the word line to a write level (for example, a high voltage such as VDH) (WLW on in the figure). For example, as shown in FIGS. 1B and 1C, when the write data is different from the storage voltage of the memory cell, if a differential voltage having a reverse polarity is applied to the data lines DL and DLB, the data is written into the memory cell. Good. In the rewriting operation, as described later, the read data is amplified and the amplified voltage is rewritten.

  As described above, in the present invention, the precharge level of the data line DLB can be used as the reference voltage at the time of amplification. Therefore, since there is no need to use a dummy cell, there is no increase in area due to the dummy cell as in the prior art, and since the reference voltage is constant over time, there is an effect that the sensing operation can be performed stably.

3 and 4 are examples of gain cells applied to the present invention, which are three-transistor memory cells composed of N-type MOSFETs. Here, QS, QW, and QR are storage, write, and read transistors, respectively. This memory cell retains information by writing VDD or 0V data corresponding to binary information to the gate of QS, and then turning off QW. In the memory cell of FIG. 3, the same word line is connected to the write and read transistors. This memory cell has a small area but requires a ternary level as a word line drive voltage. That is, when the memory cell is not selected (when the row is not selected), the voltage of the word line is normally fixed to VSS of 0V, the intermediate voltage VDL is applied during reading, and the sufficiently high voltage VDH is applied during writing or rewriting. Is done. The reason why the word line voltage is set to the intermediate level at the time of reading is to make the read transistor QR conductive while keeping the write transistor QW nonconductive. Otherwise, the information charge held at the gate of QS leaks to the data line DLB by the read operation. In order to control the word line voltage with the above three values, it is necessary to appropriately set the threshold voltages of QR and QW. First, QW threshold voltage (Vtw) is as high as possible in order to discharge data line DL at high speed with QR when QW is difficult to conduct at the time of reading and QS keeps stored information. It is desirable that the QR threshold voltage (Vtr) be as low as possible. Therefore, it is usually more convenient to set the threshold voltages of these two transistors connected to the same word line to different values. However, if Vtw is too large, in order to write VDD to the gate of QS, the condition of VDH ≧ VDD + Vtw is necessary. Therefore, there is a limit to the maximum value that Vtw can take. On the other hand, if Vtr becomes too small, a large number of row non-selected memory cells connected to the data line DL become weakly conductive due to so-called subthreshold leakage current, preventing normal reading of the selected cells. Therefore, there is a limit to the minimum value that Vtr can take. Normally, when a row is not selected at a word line voltage of 0 V, the QR threshold voltage Vtr needs to be 0.5 V or more to make QR non-conductive. If Vtr is increased in this way, the read operation is remarkably reduced at an intermediate level read voltage. One way to solve this problem is to set the row unselect level (VSS) of the word line from the conventional 0V to a negative voltage. For example, even if Vtr is set to 0V, VSS may be deeply biased to −0.5V or more so that QR becomes non-conductive when a row is not selected. At this time, the effective gate voltage that determines the QR drive speed is VDL-Vtr. Therefore, the value increases by 0.5V compared to the case where VSS is 0V and Vtr = 0.5V, enabling high-speed reading. It becomes. Furthermore, in order to amplify the data line at a higher speed, it is necessary to reduce the parasitic capacitance of the data line. For this purpose, a hierarchical data line described later is effective. The threshold voltage Vts of QS is determined based on the condition that QS is strongly conducted at the gate voltage of VDD and QS is non-conducted at the gate voltage of 0 V or is conducted very weakly, but normally Vtr ≧ 0V It is. Details of the operation example of this memory cell will be described later.

In the memory cell of FIG. 4, a read word line and a write word line are connected to gates of read and write transistors, respectively. A read voltage (VDH) is applied to the read word line to read the stored information in the memory cell, and a write voltage (VDH) is applied to the write word line to write / rewrite the stored information in the memory cell. Note that the read voltage may be VDD if the read speed is sufficient. Although the area of this memory cell is larger than that of the memory cell of FIG. 3, it is not necessary to control the voltage of the word line with three values as described above. Therefore, there is no problem of low-speed operation associated with setting the read voltage to an intermediate level, and the design of the drive circuit is facilitated. In addition, since the threshold voltages of QR and QW can be made the same in principle, there is an effect of reducing the process cost for manufacturing a plurality of MOSFETs. Furthermore, in order to operate at high speed even with a low operating voltage VDD, it is effective to lower Vtr and set the non-selection level to a negative voltage as described above. As described above, it is also effective to reduce the data line parasitic capacitance.

<Example 2>
FIG. 5 shows an embodiment of a memory circuit to which the above-described embodiment is specifically applied. Each element and circuit block shown in the figure are formed on a single semiconductor substrate (LSI) such as single-crystal silicon on which it is mounted by a known semiconductor integrated circuit manufacturing technique.

  In this embodiment, each data line includes local data pair lines DL (DL1 to DLk) and DLB (DLB1 to DLBk) that exchange data with memory cells, and global data pair lines GDL (GDL1 to GDLk). , GDLB (GDLB1 to GDLBk) has a hierarchical structure, and extends in parallel in the vertical direction. A plurality of blocks BLK (BLK11 to BLKmk) are connected to the pair of global data lines. Each block includes a pair of local data lines to which a plurality of memory cells MC (MC11 to MCn1, etc.) shown in FIG. 3A are connected, and a switching MOSFET (QRT) for connecting the global data lines and the local data lines. , QWT). These switching MOSFETs are controlled by block selection signals RWC (RWC1 to RWCm) generated in the peripheral circuit (PERI). The pair of global data pairs, after the external input address (YADR) of the DRAM core (DRAMC) is decoded by the Y decoder (YDEC), the corresponding switches QY1 and QY2 are driven by the corresponding Y driver (YDRV). By doing so, they are connected to complementary common data pair lines (IO and IOB). Each global data pair is not particularly limited, but a well-known CMOS latch type differential amplifier SA comprising P-type MOSFETs Q1 and Q2 and N-type MOSFETs Q3 and Q4 as shown in FIG. Provided. The sense amplifier SA is activated by applying the ground potential VSS and the power supply voltage VDD to the common sources SAN and SAP, respectively. Further, for example, in the differential sense amplifier shown in FIG. 3B, a P-type MOSFET is connected to the high-voltage power supply VDD side and an N-type MOSFET is connected to the ground side of the latch type differential amplifier of FIG. The amplification operation is switched by control signals SPE and SNE. Although this sense amplifier increases the area of the switch, it is characterized by a large driving force because it is connected to the power source by this switch. Hereinafter, this embodiment will be described using the sense amplifier of FIG.

As described above, the present invention has a feature that a data line having a hierarchical structure can reduce a capacity of a data pair line directly driven by a sense amplifier, thereby enabling a high-speed amplification operation. This is because the diffusion layer capacitance of the MOSFET is larger than the parasitic capacitance of the metal in the wiring layer, so it is effective to reduce the number of MOSFETs connected to the same wiring in order to reduce the parasitic capacitance. is there. The reason for using the differential amplifier is to prevent a through current generated by QR and QS when writing to the memory cell. For example, when attention is paid to the block BLK11 and VDD is written to the node N1 in the block BLK11, the QS is turned on. At this time, QR1 and QW are also on, so DL1 has a path to VSS. Therefore, unless DL1 is 0V, a through current is generated in QR and QS. This becomes a problem at the time of, for example, an operation of inverting 0 information stored in the node N1 to 1 information (so-called reverse writing). At this time, DL1 is at the precharge level, and unless it is written differentially, a through current flows through QR and QS.

  The local data lines DL and DLB are provided with precharge MOSFETs QP1 and QP2 controlled by a precharge signal PC. In the precharge period, the DL and DLB are precharged to the power supply voltage VDD (for example, 1 V) and half the voltage VDD / 2 (for example, 0.5 V), respectively. The global data pair lines GDL and GDLB are precharged to the VDD / 2 level during the precharge period by the precharge MOSFETs QP3 and QP4 controlled by the precharge signal PC.

  The memory array is composed of the plurality of pairs of data lines and a plurality of word lines (WL1 to WLmn, etc.) orthogonal thereto. In the figure, four word lines WL1, WLn, WLmn-n + 1, WLmn are illustrated as representatives. By decoding the external input X address (XADR) by an X decoder (XDEC), one of these word lines is selectively driven by an X driver (XDRV) (also called a word driver). Although the figure shows an example in which the X address and the Y address are input without being multiplexed, it is also possible to halve the number of address terminals by multiplexing the addresses by the address multiplex method.

  A memory cell is provided at the intersection of the word line and the local data lines DL and DLB. When the word line is selected, it is held by the storage MOSFETs QS and QS that are turned on or off by the information voltage of the gate. The read MOSFET QR for reading out the read information and transmitting it to the local data line DL and the write MOSFET QW for transmitting the write data given to the local data line DLB to the gate of the QS are configured. In this embodiment, the gates of QW and QR are connected to the same word line. The source-drain path of the storage MOSFET QS is connected to the readout MOSFET QR and the ground potential VSS (0 V).

  Data input / output to / from the DRAM core is as follows. The read switch RSW is turned on, and the storage information transmitted to the IO and IOB by reading the memory cell is output to the data output terminal DO via the main amplifier and the data output buffer DOB. On the other hand, at the time of writing, data input from the data input terminal DI to the data input buffer DIB is transmitted to the IO and IOB as a differential voltage by turning on the write switch WSW, and written to the memory cell by a writing operation described later. Include.

  The power supply generation circuit (VGC) has a function to step down the VDD voltage input from the outside with a regulator etc. to make it a VDL power supply, a function to boost VDL or VDD with a charge pump circuit etc. and generate a VDH power supply, These VDL and VDH are used for a word line read level and a write level, which will be described later. When the VDL power source needs to be higher than the VDD voltage, the VDD voltage input from the outside may be boosted as it is or may be boosted after being stepped down once.

  In this embodiment, as will be described later, by combining a memory cell having an amplification function and a local data pair line set to a different precharge voltage, the reference voltage level of the differential sense amplifier can be set without using a dummy cell. There is a feature in generating.

  FIG. 6 is a waveform diagram showing the write operation of the memory cell of the embodiment. Here, the block BLK11 will be described as an example. When the precharge signal PC becomes the high voltage VDH (VDH ≧ VDD + Vtw (where Vtw is the threshold voltage of QW)) level, the local data lines DL and DLB are precharged to the power supply voltages VDD and VDD / 2, respectively. Similarly, the global data pair lines (GDL and GDLB), the common sources (SAN and SAP) of the sense amplifier SA, and the common IO lines (IO, IOB) are precharged to VDD / 2.

  When the precharge signal PC becomes 0V, the precharge MOSFET is turned off, so that the paired wires are in a floating state and keep the precharge voltage. In this state, writing / reading to / from the memory cell is performed. Hereinafter, the write / read / refresh operation of the memory cell when the word line WL1 and the column line YS1 are selected will be described.

(1) Write operation In order to write the high voltage VDD or the low voltage VSS corresponding to the binary information 1 or 0 to the storage node (N1) of the memory cell MC1, a sufficiently high voltage VDH is applied to the word line WL1. There is a need to. This VDH needs to satisfy the relationship of VDH ≧ VDD + Vtw (in this case, for example, VDH = 2.5 V) when the threshold value of the writing MOSFET QW is Vtw (for example, 0.5 V). When one block selection signal (RWC1) (RWC1) is selected under these conditions, the differential voltage corresponding to the write data input from the data input terminal DI is changed from the global data line to the corresponding local data line. Via QS, the data is written to MC11. However, it should be noted here that when the above-mentioned VDH is applied to the word line WL1, the stored information of the column non-selected memory cells not selected by the column selection signal on the same word line is destroyed. That is, the precharge voltage VDD / 2 of the corresponding local data line DLB1 is applied to the storage node in each column non-selected memory cell. In order to prevent such information destruction, all memory cells on the selected word line are read once, amplified by each sense amplifier, and the amplified voltage is rewritten to each memory cell. However, the amplified voltage may be replaced with the input data voltage from the common data line IOB and written into the selected memory cell MC11. Therefore, the read operation is essential prior to the write operation. Therefore, the reading operation in this case will be described below. As described above, the word line voltage of the memory cell in FIG. 3 requires VDL at the time of reading, VDH at the time of writing, VSS at the time of row non-selection, and a three-level voltage.

  First, reading when the high voltage VDD is stored in the memory cell MC11 will be described. The read operation is started by applying a pulse of an intermediate level VDL to the word line, and the amplitude VDL thereof is set to turn on QR but turn off QW. To do so, the following conditions must be met.

  The memory cell stores binary information of VDD or 0 V at the gate of QS, and the stored information is discriminated depending on whether QS is on or off when a read pulse is applied to the word line. In order to apply the read pulse of VDL to make QR conductive, it is necessary to satisfy the following relational expression when the threshold voltage of QR is Vtr.

VDL> Vtr (1)
At this time, in order that the stored information of the gate of QS is not destroyed even if a read pulse is applied to QW, the following conditions are necessary. In other words, when the gate voltage of QS is VDD, a condition for making QW non-conductive may be obtained so that the charge stored in the gate of QS does not disappear to the local data line DLB1 through QW. Since the data line precharged to VDD / 2 becomes the source of QW, this condition is as follows when the threshold voltage of QW is Vtw.

VDL <VDD / 2 + Vtw (2)
On the other hand, when the gate voltage of QS is 0V, even if QW is turned on and the gate of QS is charged and boosted from 0V, if the boosted voltage is lower than the threshold voltage Vts of QS, QS is not turned on. It remains. This condition is as follows.

VDL <Vts + Vtw (3)
Here, in order to prevent the charge stored in the gate of QS from disappearing to the local data line for a long time (for example, 2 ms to 64 ms), it is desired to increase the threshold voltage Vtw. On the other hand, Vts and Vtr should be as low as possible for high-speed reading. Therefore, the three threshold voltages can be freely selected within a range that satisfies the above-described equation. However, Vtr cannot be as low as Vts. This is because unstable operation is caused. This is because a leak current (so-called subthreshold current) flows through the transistors QR in other non-selected memory cells connected in large numbers to the same local data line, and the precharge voltage of the local data line decreases. . For example, if VDD = 1V, Vtw = 1V, Vts = 0V, Vtr = 0.5V, etc., the range of VDL in which stored information is not destroyed by QW is as follows from equations (1) to (3).

1.5V>VDL> 0.5V
When VDL is set in this way, DL1 and DLB1 precharged to VDD and VDD / 2 change as follows. If the gate of QS (storage node N1) is VDD, DL1 is discharged to 0V (indicated by N1 in FIG. 6), and since QWT is off, DLB1 is maintained at the precharge level VDD / 2. On the other hand, when the potential of the gate of QS (storage node N1) is 0V, QS is off, so DL1 holds the precharge level (indicated as N1 ′ in FIG. 6), and DLB1 is precharged because QWT is off. The charge level is maintained at VDD / 2. As described in the first embodiment, it is effective to set the row non-selection level of the word line to a negative voltage and set Vtr to a low value such as 0 V for high-speed reading.

  Now, after the stored information is read out to the local data line DL1, the control signal RWC1 is set to high level to turn on QRT and QWT, so that DL1 and GDL1 or DLB1 and GDLB1 are connected to each other. At this time, since DLB1 and GDLB1 are at the same potential level (precharge level), there is no potential change. However, the read signal (vs) appears in GDL1 by charge distribution according to the parasitic capacitance as follows.

  When the local data line DL1 is discharged and at 0V, the level of the global data line GDL1 decreases by vs with respect to VDD / 2, and DL1 also has the same value VDD / 2−vs level. On the other hand, when the read data line DL1 remains at the precharge level VDD, GDL1 rises (+ vs) by a minute voltage with respect to the precharge voltage VDD / 2, and DL1 also has the same value VDD / 2 + vs level. Become. This situation is described by dotted lines in the waveform diagrams of DL1, DLB1, GDL1, and GDLB1 in FIG. 6 and indicated by dashes symbols DL1 ′, DLB1 ′, GDL1 ′, and GDLB1 ′. Thus, a minute read signal of −vs or + vs with respect to VDD / 2 appears on the global data line GDL1 in accordance with the binary information (1 or 0) held in the storage node of the memory cell. Therefore, discrimination and amplification can be performed by the sense amplifier with reference to the precharge voltage VDD / 2 of the other global data line GDLB1. Here, a case where a sense amplifier as shown in FIG. 2A is used will be described. This amplification is performed by setting the common source line SAP to a high voltage such as VDD and the common source line SAN to a low voltage such as VSS. As a result, the global data line GDL is at the low level (VSS), and the other global data line GDLB1 complementary to GDL1 is at the high level (VDH). As described above, the present invention has a feature that dummy cells, which have been essential in the past, are not required for amplifying memory storage information. The control signal RWC1 may be set to the high level at the same time as the precharge signal PC becomes the low level. In that case, since the timing to be controlled is reduced, there is an effect that the design becomes easy.

  After being amplified by the sense amplifier, the differential voltage between VDD and VSS applied to the common data pair lines (IO, IOB) for writing to the memory cell should selectively set the column selection line YS1 to the high level. Are sent to the global data pair (GDL1, GDLB1) and the local data pair (DL1, DLB1). (The movement of DL1 ′ indicated by the dotted line in the figure is when 0V is stored in the gate of the storage MOSFET QS.) Thereafter, the word line level is set to the write level VDH. As a result, the voltage of the write data line DLB1 is transmitted to the gate of QS in the memory cell MC11 to complete the writing. The amplified storage voltage is rewritten to other column non-selected memory cells on the same word line.

  When the write operation to the memory cell selected in the column and the rewrite operation to the non-selected memory cell are completed as described above, the word lines WL1 and YS1 are set to the low level, and the QY1 and QY2 are turned off. Further, by setting the precharge signal PC to the high level (VDH), each local data pair line and global data pair line are precharged, and can be prepared for the next memory access.

(2) Read operation FIG. 7 shows a waveform diagram showing the read operation. In the read operation, in the write operation as described above, the read signal of the memory cell selected in the row and column may be amplified by the sense amplifier SA, output to the common data pair line, and taken out from the data output terminal DO. When the row selection level of the word line is set to the high voltage VDH, the voltage corresponding to the read information is rewritten to all the column selection cells and the column non-selection cells.

(3) Refresh operation In the refresh operation, the read / rewrite operation for all the memory cells on the word line may be performed for all the word lines while the column selection line YS is not selected in FIG.

FIG. 8 is a layout diagram related to the memory cell of the present invention. This figure shows four memory cells shown in FIG. 5, QRT, and QWT. A part of the word line WL1 made of a polysilicon layer (POLY) or the like forms the QR and QW gates of the memory cell MC11, and the same polysilicon layer forms the QS gate (GQS). Local data lines (DL1 and DLB1, etc.) are formed of the same layer (M2) metal, and global data line pairs (GDL1 and GDL1B) are formed of the other layer (M3) metal. The contact LCT shown in the figure directly connects the diffusion layer and the gate. Also, VSS is applied to the source of QS, which is laid out with a metal 1 layer (M1) and shared with adjacent memory cells for miniaturization. For this reason, the two memory cells are laid out in a mirror image relationship. The connection between the two wires is a MOSFET (QRT, QWT) with a part of the wiring such as polysilicon as the gate.
).

  In order to clarify the relationship between the layers, the aa ′ cross section and the bb ′ cross section of FIG. 8 are shown in FIGS. 9A and 9B. FIG. 9 (a) is an aa ′ cross section, showing a cross section passing through the local data line DL1 and the global data line GDL1. FIG. 9B shows a cross section taken along the line bb ′, which passes through the local data line DLB1 and the global data line GDLB1. In this figure, two contacts LCT are shown. Further, FIGS. 10A and 10D show cross sections cc ′ and dd ′ in a direction perpendicular to the aa ′ cross section bb ′ cross section. (b) shows two contacts LCT.

<Example 3>
In the second embodiment, the control of the read transfer MOSFET QRT and the write transfer MOSFET QWT is controlled by one signal RWC, so there is a margin in timing margin, and the electrical of the data pair line as viewed from the sense amplifier. Since the degree of balance is also good, high speed stable operation is possible accordingly. However, since it is necessary to wire the VSS and VDD / 2 power supply lines for each block BLK, there is a concern that the area may increase in some cases.

  Figure 11 shows that VDD is used as the precharge power supply for local data lines DL and DLB, read signal RC is used to control read block selection MOSFET QRT, and write block control MOSFET QWT is controlled to write This means that the control signal is made independent by reading and writing, such as using the control signal WC. Compared with the second embodiment, this embodiment may slow down the operation speed by making RC and WC control independent, but it is used for precharge for each block wired in the memory array. Since the power supply wiring can be halved, the area can be reduced.

  FIG. 12 is an operation waveform diagram of the embodiment shown in FIG. Here, a case where the memory cell MC1 of the block BLK1 in FIG. 11 is selected will be described as a representative. Writing is almost the same as in FIG. 6, but the connection method of the global data pair line and the local data pair line is different. In FIG. 6, the write transfer MOSFET QWT and the read transfer MOSFET QRT are simultaneously turned on / off using the same control signal RWC. In this embodiment, the potential of the local data line DL is VSS (the potential of the storage node N1). DL is connected to DL using only the control signal RC1 after the precharge level VDD (when the potential of the storage node N1 is 0 V). As a result, as described with reference to FIG. 6, DL and GDL are at the level of VDD / 2−vs when the storage node N1 is VDD, and at the level of VDD / 2 + vs when the storage node N1 is 0V. When the sense amplifier is activated after the potential of the global data line GDL is thus determined, the potential of the global data pair line is amplified. After being amplified by the sense amplifier, as described in FIG. 6, when write data is transmitted from the outside, QWT is turned on by setting the control signal WC1 to the VDH level, and the write data is transferred to the local data line DLB. Communicated. After the write data is transmitted to the local data line DLB, the write data is written to the storage node N1 of the memory cell by setting the potential of the word line to the write potential VDH. QRT and QWT cannot be turned on at the same time when reading. This is because the precharge level of the local data line DLB is VDD, so if QWT is turned on at the time of reading, a positive minute signal is transmitted to the global data line GDLB precharged to VDD / 2, which makes accurate reference This is because the potential cannot be obtained. In particular, when the storage node N1 is VDD, there is a possibility that an accurate amplification operation cannot be performed due to the magnitude relationship with the above-described positive minute signal + vs appearing on the global data line GDL.

  In the read operation, the read signal of the selected memory cell is amplified by the sense amplifier SA, outputted to the common data pair line, and taken out from the data output terminal DO. When the word line selection level is set to the high voltage VDH, the voltage corresponding to the read information is rewritten to all the column selected cells and the column non-selected cells.

  In the refresh operation, the read / rewrite operation for all the memory cells on the word line may be performed for all the word lines while the column selection line YS is not selected.

<Example 4>
In the embodiments described so far, the local data pair connected to the global data pair is only the selected block when amplified by the sense amplifier. In such a configuration, since the number of MOSFETs connected to the global data pair can be reduced, the load capacity is small and a high-speed amplification operation is possible. This is because, generally, the parasitic capacitance of the metal wiring is smaller than the parasitic capacitance generated when a large number of MOSFETs are connected. However, there are cases where it is desired to save the number of wires rather than the high-speed amplification operation. An embodiment of a memory array with a small number of wires will be described below.

  FIG. 13 is an example of another memory circuit according to the present invention. The feature of this embodiment is that the write local data line (DLB) is shared with the global data line GDLB to reduce the number of wirings, and the QWT required in the second embodiment is not used. Therefore, the QW in FIG. 5 is directly connected to the global data line GDLB. Therefore, as will be described later, it is possible to install signal lines other than data lines on the memory array without adding a wiring layer, and there is an effect that a limited wiring layer can be used effectively.

  FIG. 14 is a waveform diagram of the write operation of the memory circuit shown in FIG. Similar to the description in FIG. 6, the memory is read / written after the precharge signal PC is set to low level. Also in this embodiment, the read operation is performed prior to the write operation. The only difference from FIG. 6 is that there is no DLB. As described above, the storage information of the memory cell MC1 is read as a signal having a different polarity to the global data line GDL1, and the information is sensed with reference to the voltage (VDD / 2) of the other global data line GDLB1 that forms a pair. Amplified and discriminated by an amplifier. After that, as described above, the above-described amplified voltage is replaced with the voltage of the externally written data, and written to the memory cell MC1. At this time, the original memory voltage is rewritten in the other memory cells. Read and refresh operations are also performed as described above.

  FIG. 15 is a layout diagram around the memory cell of the present invention. This figure shows the four memory cells shown in FIG. 13, QRT, and QWT. In the memory cell MC1, a part of the word line WL1 made of a polysilicon layer or the like forms QR and QW gates, and the same polysilicon layer forms a QS gate. Local data line DL and global data line GDLB are wired with the same layer (M2) metal, and global data line GDL and column selection line signal lines (SIG1, SIG2, etc.) are with other layers (M3) metal. It is formed. The contact LCT shown in the figure directly connects the diffusion layer and the gate. The power supply VSS is applied to the source of the QS, which is laid out with a single metal layer and shared with adjacent memory cells for miniaturization. For this reason, the two memory cells are laid out in a mirror image relationship. DL and GDL are connected by a MOSFET QRT whose gate is a part of wiring such as polysilicon. In order to clarify the relationship between the layers, the ee ′ cross section and the ff ′ cross section of FIG. 15 are shown in FIGS. 16 (a) and 16 (b). FIG. 16 (a) is an ee ′ cross section, showing a cross section passing through the read data line DL1 and the global data line GDL1. FIG. 16B is a cross section taken along the line ff ′ and passes through the global data line GDLB1 and the signal line. In this figure, two contacts LCT are shown. Further, FIGS. 17 (a) and 17 (b) show cross sections gg ′ and hh ′ in a direction perpendicular to the ee ′ cross section and the ff ′ cross section. (b) shows two contacts LCT.

<Example 5>
FIG. 18 shows an embodiment in which the number of power lines for precharging in the array is reduced to further reduce the area. FIG. 18A shows a case where, for example, FIG. 2B is used as a sense amplifier. FIG. 18B shows a case where, for example, FIG. 2A is used as the sense amplifier. This embodiment is characterized in that the power supply wiring for precharging the local data pair lines required for each block BLK in FIG. 5 is eliminated and the precharge power supply is shared with the global data pair lines. 18 (a) and 18 (b) show an example in which there are four blocks BLK, the present invention can be implemented without limiting the number of blocks to four. First, FIG. 18 (a) will be described. In the figure, global data line GDL and local data line DL (DL1 to DL4) are precharged to power supply voltage VDD during the precharge period, and global data line GDLB and local data line DLB (DLB1 to DLB4) are half charged during the precharge period. Precharged to precharge level VDD / 2. For this,
It is necessary to set all the control signals RWC (RWC1 to RWC4) to high level (ON) during the precharge period. In order to eliminate the through current during the precharge period, the sense amplifier activation signal SPE is set to the high level and the SNE is set to the low level. The through current during the precharge period, which is a problem here, occurs because the precharge voltages of GDL and GDLB are not equal to VDD and VDD / 2, respectively. For example, when the sense amplifier of FIG. 2A is used, the transistor Q4 is turned on halfway during the precharge period, so that a current flows from the GDL to the common source line SAN.

  Here, the write operation of the embodiment of FIG. 18 (a) will be described with reference to FIG. In this embodiment, the read operation is performed prior to the write operation. Here, the read operation will be described taking the memory cell MC11 of the block BLK1 as an example. In this figure, word lines connected to each memory cell are omitted. The data line is precharged when the precharge signal (PC) is at a high level. At this time, the global data pair lines GDL and GDLB are precharged to VDD and VDD / 2, respectively. At the same time, in order to precharge the local data pair lines DL1 and DLB1, the control signal RWC1 is set to the high level to connect the local data pair line to the global data pair line. As a result, the local data pair lines DL1 and DLB1 are precharged to VDD and VDD / 2, respectively. In order to enter the read operation, it is necessary to stop the precharge, and this is done by setting the PC to a low level. When the PC is at the low level, reading from the memory cell selected for the row is started by setting the potential of the word line to the read level VDL. At this time, the control signals RWC2 to RWC4 of the non-selected blocks are preferably set to the low level as indicated by RWC ′ in FIG. In this way, the load capacity to the global data pair can be reduced. This is because the memory cell transistors in the non-selected block are electrically disconnected from the global data pair line, so that the load capacitance can be reduced by the parasitic capacitance due to these non-connected MOSFETs. After waiting until the read potential to the local data line DL1 and the global data line GDL drops below VDD / 2, the sense amplifier start signal SPE is set to low level, the SNE is set to high level, the sense amplifier is started, the read signal is set to 0, Amplify accurately to 1.

  In writing to the memory cell, first, the column selection switches QY1 and QY2 are turned on to transmit the write signal voltage transmitted to the common data pair to the global data pair. Thereafter, the word line is set to the write level VDH to transmit a write signal to the storage node n1 of the memory cell, the word line is set to the column non-select level 0V, and the storage node is isolated from the local data line. Thereafter, the state returns to the precharge state, which is the same as described with reference to FIG.

  Next, FIG. 18B will be described. This is a modification of the embodiment described in FIG. 18A, and the configuration of the sense amplifier is different. In this example, a sense amplifier having the same precharge level of the data pair line connected to the sense amplifier as shown in FIG. 2A is used. Since the precharge levels of the global data pair lines GDL and GDLB in FIG. 18B are VDD and VDD / 2, respectively, the precharge levels of both global data pair lines are not equal. Therefore, the main data pair lines MGDL and MGDLB separated by the isolation MOSFETs Qi1 and Qi2 and having a precharge level of VDD / 2 are newly provided, and this MGDL and MGDLB are connected to a sense amplifier to amplify the read signal. To do.

  Here, the write operation of the embodiment of FIG. 18B will be described with reference to FIG. Also in this case, the read operation is performed prior to the write operation. Here, the read operation will be described using the block BLK1 as an example. In this figure, word lines connected to each memory cell are omitted. The data line is precharged when the precharge signal (PC) is at a high level. At this time, the main data pair lines MGDL and MGDLB are precharged to VDD / 2 level, respectively, and the global data pair lines GDL and GDLB are precharged to VDD and VDD / 2, respectively. At the same time, in order to precharge the local data pair lines DL1 and DLB1, the control signals RWC1 to RWC4 are set to the high level to connect the local data pair line to the global data pair line. As a result, the local data pair lines DL and DLB are precharged to VDD and VDD / 2, respectively. In order to enter the read operation, it is necessary to stop the precharge, and this is done by setting the PC to a low level. When the PC is at the low level, reading from the memory cell selected for the row is started by setting the potential of the word line to the read level VDL. At this time, it is desirable that the control signals RWC2 to RWC4 of the non-selected blocks be at a low level as indicated by RWC ′ in FIG. In this way, the load capacity to the global data pair can be reduced. When reading to the local data line DL1 and the global data line GDL is completed, the control signal IC is set to the high level, and the read signal voltage transmitted to the global data line is transmitted to the main data line MGDL. As a result, a read signal (± vs) having a different polarity according to the information voltage of the storage node appears on the main data line MGDL by charge distribution according to the parasitic capacitance of each data line. At this time, since GDLB and MGDLB are at the same potential level (precharge level), there is no potential change. Therefore, as described in the description of FIG. 6, a read signal of VDD / 2 + vs or VDD / 2−vs is transmitted to the MGDL in accordance with a read signal from the memory cell. After the read signal is transmitted to the MGDL, the control signal IC is set to the low level to isolate the main data pair lines MGDL and MGDLB from the global data pair lines GDL and GDLB. Thus, if the global data line is isolated during amplification, the parasitic capacitance of the main data lines MGDL and MGDLB is reduced, so that the amplification can be performed at high speed. Thereafter, the read signal is accurately amplified to 0 and 1 by a sense amplifier connected to the main data line.

  To write to the memory cell, first, by turning on the column selection switches QY1 and QY2, the write signal voltage transmitted to the common data pair line is transmitted to the main data pair lines MGDL and MGDLB, and the control signal IC is set to the high level. The switches QI1 and QI2 are turned on and transmitted to the global data pair. Thereafter, the word line is set to the write level VDH to transmit a write signal to the storage node N1 of the memory cell, and the word line is set to the non-select level 0V to isolate the storage node from the local data line. Thereafter, the state returns to the precharge state, which is the same as described with reference to FIG. Note that the precharge MOSFET QP1 and the isolation MOSFET Qi1 are unnecessary in principle because the precharge voltages of MGDLB and GDLB are equal. However, the advantage of providing these MOSFETs is that a stable amplification operation can be realized because the main data pair lines MGDL and MGDLB are electrically balanced.

<Example 6>
FIG. 21 shows another embodiment in which the precharge power source is shared between the local data pair line and the global data pair line. In the memory array configuration of the embodiment shown in FIG. 13, the precharge power supply wiring is shared by the local data pair line and the global data pair line. The difference from FIG. 13 is that the precharge level of the global data line GDL is VDD. Although FIG. 21 shows the case where the number of blocks is four, the present invention can be implemented without limiting the number of blocks to four.

  The write operation and the read operation conform to the description of FIG. 14, but the control of writing / reading to the global data line conforms to the description of FIG. That is, the operation of RWC and RWC ′ in FIG. 19 may be replaced with the operation of RC and RC ′, and control may be performed according to an operation waveform diagram that does not use the operation of DLB1.

<Example 7>
In the memory array configurations of FIGS. 5, 10, and 13, the number of MOSFETs connected to the global data pair GDL and GDLB is not uniform, so that the parasitic capacitance differs between GDL and GDLB. For this reason, when viewed from the sense amplifier, there is a possibility of acting on effective noise or a low-speed operation. FIG. 22 shows an embodiment in which a paired line configuration for reducing non-uniformity of parasitic capacitance is applied to FIG. This embodiment has an effect of crossing the global data pair lines on the memory cell and eliminating the capacity imbalance between the pair lines. Also, as shown in this figure, if the crossing method is changed for each adjacent global data pair line, it is possible to cancel out noises appearing in GDL and GDLB well.

  First, the balancing of parasitic capacitance will be described. Here, for the sake of convenience, the explanation will be made by paying attention to adjacent global data pairs (GDL1 and GDLB1 and GDL2 and GDLB2). Assume that four blocks each composed of n memory cells MC11 to MC1n are connected to these global data pair lines. Consider a case where the block BLK11 is selected and the control signal RC is at a high level. At this time, the number of MOSFETs connected to GDL1 is n + 1 for the QRK of QRK11 and the read MOSFET connected to it, n for the write MOSFET for BLK12, one for the read transfer MOSFET for BLK13, and n for the write MOSFET for BLK14. The total number of MOSFETs connected to GDLB1 is n BLK11 write MOSFETs, BLK13 read transfer MOSFETs, BLK13 write MOSFETs, and BLK14 read. One transfer MOSFET, 2n + 2 in total. If the global data lines are not crossed, the number of MOSFETs connected to GDL is BLK11 QRT and n read MOSFETs connected to it, BLK12 read transfer MOSFET, BLK13 read transfer MOSFET, BLK14 read transfer MOSFET The total number of n + 4 in the GDLB is 4n including n BLK11 write MOSFETs, BLK13 write MOSFETs, BLK13 write MOSFETs, and BLK14 write MOSFETs. Therefore, it can be said that the imbalance of the number of MOSFETs connected to the global data pair is greatly improved. Similarly, even if the global data pair is arranged like GDL2 and GDLB2, the number of connections on the read side and the write side of the block BLK is equal, which clearly improves the number of connected MOSFETs. It is.

  Next, reduction of noise appearing in GDL and GDLB will be described. During memory read / write operations, GDL and GDLB change from the precharge level to VDD or VSS, and at this time, it is known that noise due to capacitive coupling occurs in adjacent global data lines. If GDL and GDLB are wired as shown in Fig. 22, for example, when GDL1 is focused, the global data pair (GDL2, GDLB2) is placed next to GDL1 with the same length, so the same noise is Appears equally to GDLB2. Therefore, the noise generated in GDL2 and GDLB2 is the same, which has the effect of eliminating the possibility of malfunction during amplification by the sense amplifier.

  Although an example in which four blocks are connected to a pair of global data lines is shown in this figure, the present invention can be implemented without limiting the number of connected blocks to four.

<Example 8>
FIG. 23 shows another embodiment for balancing the parasitic capacitance of the global data pair. For half the blocks connected to the global data pair (for example, BLK11 and BLK13), the read transfer MOSFET is connected to GDL1, the write MOSFET is connected to GDLB1, and the other half block (for example, BLK12) is connected. And BLK14), a write MOSFET is connected to GDL1, and a read transfer MOSFET is connected to GDLB1. As a result, when BLK11 is selected, 3n + 2 MOSFETs are connected to GDL1, and 2n + 2 MOSFETs are connected to GDLB1. This uses a structure that does not cross the global data pairs in order to eliminate the capacity imbalance. Since the wiring intersection usually uses two or more metal wiring layers, the present invention can reduce the number of wiring layers to be used. Therefore, there is an effect of saving area by allocating a limited wiring layer to other signal lines and power supply lines. In this figure, the configuration of blocks connected to adjacent global data pair lines is such that, for example, BLK11 and BLK21 are arranged in a mirror image relationship with respect to the global data line, but they need not be arranged in a mirror image relationship. The arrangement method of the blocks may be determined depending on the ease of layout.

<Example 9>
FIG. 24 is an operation waveform diagram for explaining another embodiment for further balancing the parasitic capacitance generated in the GDL and GDLB in the memory cell described above. Here, description will be made using the example described in the embodiment of FIG. This embodiment relates to a control signal control method for transmitting storage information of a memory cell to a global data line. This embodiment is characterized in that the read transfer MOSFET is turned on by the control signal RC1 and read data is transferred to the global data line GDL, and then the read transfer MOSFET is turned off before being amplified by the sense amplifier. . As a result, the n QRs of the selected block are electrically disconnected from the GDL, so that this capacitance does not contribute as a load capacitance during sensing. Therefore, the number of MOSFETs connected to GDL and GDLB is 2n + 2, respectively, and there is an effect that the parasitic capacitance imbalance is further eliminated.

  The present invention eliminates the need for a dummy cell, which has been conventionally required in a DRAM circuit using a gain cell, and thus has the effect of reducing the area and manufacturing cost. In addition, the hierarchical data line structure has an effect of enabling high-speed operation.

(a) is one Example which shows the most fundamental structure of this invention, (b), (c) is the operation | movement waveform diagram. (A) is explanatory drawing comprised by a CMOS latch circuit, (b) is explanatory drawing of a CMOS latch type | mold sense amplifier which has a switch in a power supply. (a) is a circuit diagram of a three-transistor DRAM having the same read and write word lines, and (b) is a waveform diagram of the word line drive. (a) is a circuit diagram of a three-transistor DRAM in which a read word line and a write word line are separated, and (b) is a waveform diagram of the word line drive. 1 is a circuit diagram showing a main part of an embodiment of a memory circuit configured in a semiconductor integrated circuit according to the invention; FIG. 6 is a waveform diagram for explaining an example of a write operation of the memory circuit of FIG. 5. FIG. 6 is a waveform diagram for explaining an example of a read operation of the memory circuit of FIG. 5. FIG. 6 is a diagram showing an example of a layout around the memory cell of FIG. 5. (a) is sectional drawing of the aa 'cross section of FIG. 8, (b) is sectional drawing of the bb' cross section of FIG. FIG. 9A is a cross-sectional view taken along the line cc ′ of FIG. 8, and FIG. 9B is a cross-sectional view taken along the line dd ′ of FIG. The principal part circuit which shows another Example of the memory circuit comprised by the semiconductor integrated circuit concerning this invention. FIG. 11 is a waveform diagram for explaining an example of a write operation of the memory circuit of FIG. The principal part circuit which shows another Example of the memory circuit comprised by the semiconductor integrated circuit concerning this invention. FIG. 14 is a waveform diagram for explaining an example of a write operation of the memory circuit of FIG. 13. The figure which shows one Example of the layout around the memory cell in the Example of FIG. 15A is a cross-sectional view taken along the line ee ′ of FIG. 15, and FIG. 15B is a cross-sectional view taken along the line ff ′ of FIG. 15A is a cross-sectional view taken along a line gg ′ in FIG. 15, and FIG. 15B is a cross-sectional view taken along a line hh ′ in FIG. FIG. 4 is still another embodiment of the present invention. (A) is a figure which shows the example using a sense amplifier like FIG.2 (b), (b) is a figure which shows the example using a sense amplifier like (a) of FIG. FIG. 18 is an operation waveform diagram showing the write operation of FIG. FIG. 18 is an operation waveform diagram showing the write operation of FIG. FIG. 4 is still another embodiment of the present invention. An example of a global data line arrangement method. An example which shows the connection method of a block and a global data line. One embodiment for realizing electrical balance of global data lines.

Explanation of symbols

VDD ... Low-voltage power supply, VSS ... VDD ground potential, VDL ... Word line potential during reading, VDH ... Word line potential during writing, WLR on ... Start reading, SA on ... Sense amplifier activation, WLW on ... Start writing, Δ ... Sensitivity of sense amplifier, BLK ... Block, n ... Storage node, MC ... Memory cell, QR ... Read MOSFET, QW ... Write MOSFET, QS ... Storage MOSFET, QP ... Precharge MOSFET, QY ... Column selection switch MOSFET , QRT ... Read transfer MOSFET, QWT ... Write transfer MOSFET, DL ... Read data line, DLB ... Write data line, GDL ... Global data line, GDLB ... Global data line (for GDL complementary signal), SA ... Sense amplifier , IO ... Common IO line, IOB ... Common IO line (for complementary signal of IO), WL ... Word line, PC ... Precharge signal, YS ... Column selection signal, RWC ... Block selection signal, WC ... Write control signal, RC ... Read control signal, XDEC ... Row decoder, XDRV ... Word dry , YDEC ... Column decoder, YDRV ... Driver, MA ... Main amplifier, DIB ... Data input buffer, DOB ... Data output buffer, VGC ... Power generation circuit, RSW ... Read switch, WSW ... Write switch, SAP ... Sense amplifier start Signal (P-type MOSFET source side), SAN ... Sense amplifier start signal (N-type MOSFET source side), SPE ... Sense amplifier start signal (P side), SNE ... Sense amplifier start signal (N side), M1 to M3 ... Metal wiring layer, ND ... MOSFET diffusion layer, LCT ... Local contact, CT1-2 metal interlayer contact, P-SUB ... P-type silicon substrate, MGDL ... Main data line, MGDLB ... Main data line (for complementary signals of MGDL) Qi ... Main data line and global data line isolation MOSFET, IC ... Main data line and global data line isolation control signal, DRAMC ... DRAM core circuit.

Claims (1)

A first memory block comprising first and second wirings, a first switch, a plurality of first word lines, and a plurality of first memory cells;
A second memory block including a second switch, a plurality of second word lines, and a plurality of second memory cells;
Each of the plurality of first memory cells includes first, second, and third transistors, and the gates of the first and second transistors are connected to one of the plurality of first word lines, The drain of the third transistor is connected to the source / drain path of the second transistor,
Each of the plurality of second memory cells includes fourth, fifth, and sixth transistors, and gates of the fourth and fifth transistors are connected to one of the plurality of second word lines, A drain of the sixth transistor is connected to a source / drain path of the fifth transistor; a source / drain path of the first transistor of the plurality of first memory cells is connected to the first wiring;
Source / drain paths of the fourth transistors of the plurality of second memory cells are connected to the second wiring;
Source / drain paths of the second transistors of the plurality of first memory cells are connected to the second wiring via the first switch,
A semiconductor integrated circuit in which a source / drain path of the fifth transistor of the plurality of second memory cells is connected to the first wiring via the second switch.