JP2002368134A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for reducing noise in a semiconductor memory device. SOLUTION: This device is provided with a capacitor, formed with a recessed part on the wafer of a semiconductor device and a polysilicon layer provided in that recessed part; when 4F<2> memory cells(MC) is formed by being laminated on the polysilicon layer and having a channel made by an intrinsic semiconductor into a longitudinal structure, adjacent bit lines are formed on mutually different layers; and when notice is taken of adjacent bit lines, by alternately locating the MC, each time the bit lines(BL) which cross word lines(WL), bit line load is made uniform. Then, by exchanging the adjacent bit lines through bit line crossing, inter bit line noise is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
Furthermore, PLED (Phase state Low)
The present invention relates to a semiconductor memory device using an Electron Number Drive (Electron number Drive) transistor.

[0002]

2. Description of the Related Art DRAM as an example of a memory device
(Dynamic random access memory) includes an address buffer and a decoder as described in “LSI Handbook (pages 486-)” issued by Ohmsha on November 30, 1984. For a peripheral circuit such as a sense amplifier, a dynamic circuit that operates in synchronization with an internal clock is used. In DRAM, 1
A three-phase external clock is required, and an internal clock is generated based on these clocks to control the operation of the internal circuit.

[0003] Japanese Patent Application Laid-Open No. 10-200001 has a memory node in which a charge is written from a control electrode through a multi-tunnel barrier structure, and the accumulated charge affects the conductivity of a source / drain path. Thus, a memory device that enables reading of data by monitoring the conductivity of this path has been proposed.

Japanese Patent Publication No. Hei 8-506214 describes a memory device having a memory node to which a multi-stage transistor device having a side wall gate is connected. The memory node exhibits first and second quantized memory states in which the level of the stored charge is limited by Coulomb interference, and the difference, the excess or shortage of a small number of electrons, for example 10 electrons, causes the quantized memory state. Is represented.

[0005] US Patent Nos. 5, 10
7,459 "has a memory configuration in which a memory cell is realized by combining a transistor having a vertical structure and a trench capacitor, and furthermore, noise is reduced by forming two bit lines and crossing bit lines. Has been proposed.

[0006] "A dual layer DRAM"
array with Vcc / Vss hybrid
precharge for multi-giga
bit DRAMs (1996 Symposium)
on VLSI Circuits Digest
of Technical Papers) proposes a memory structure capable of canceling noise between adjacent bit lines by improving a bit line crossing technique.

[0007] US Patent No. 5,86
No. 4,181 "shows how to cross bit lines in two layers in a memory device.

[0008]

When the minimum processing size of a semiconductor device is indicated by "F", the size of one bit of a memory cell is expressed as 4F ² , 6F ² , 8F ² or the like.
That is, “4F ² ” is a 4F ² rectangular area (vertical 2
(F, horizontal 2F) means that a 1-bit memory cell is formed. Similarly, “6F ² ” means that a 1-bit memory cell is formed in a 6F ² rectangular area, and “8F ² ” means that a 1-bit memory cell is formed in an 8F ² rectangular area. Means to be done. Further, a configuration in which a pair of bit lines of a complementary level extend in the same direction and a signal level between the pair of bit lines of the complementary level is amplified by a sense amplifier is referred to as a “two-intersection cell arrangement”. A configuration in which bit lines are formed on both sides of a sense amplifier and a signal level of one bit line is amplified and a potential level of the other bit line becomes a reference is referred to as "one intersection cell arrangement".

[0009] For ^4F 2 -1 intersections cells, as compared to ^8F 2 -2 intersection cell, requires only a small chip area occupied. However, since a bit line pair of a complementary level is not used in the one intersection cell, bit line coupling noise and inter-bit line noise from the word line WL cannot be canceled. If alleviate bit line arrangement pitch in the 6F ² cells, it can reduce the noise between the bit lines,
The memory cell size in this case, increases in 1.5 times the 4F ² cells.

The above US Patent Nos. 5, 1
According to the technique described in 07,459 ", the transistor of vertical structure, to achieve 4F ² cell by combining the trench capacitor, further, by cross bit lines as well as two layers of bit lines Noise can be reduced. However, although the bit line load imbalance seen from the sense amplifier can be reduced, the adjacent bit lines are always the same, so that the adjacent bit lines are likely to be affected by noise. Further, since the bit line in the upper layer has a structure directly above the bit line in the lower layer, the area of the bit line cross portion is relatively large.

The above "A dual layer DRA"
M array with Vcc / Vss hybr
id precharge for multi-gi
gabti DRAMs (1996 Symposi)
mon VLSI Circuits Diges
In “T of Technical Papers”, a memory structure capable of canceling noise between adjacent bit lines has been proposed by improving a bit line crossing technique. However, since all memory cells are connected to a lower layer of a bit line, The load on the memory cell is likely to be uneven.

"US Patent No. 5,86
In 4,181 ", but how 2 stratified bit lines cross is shown in the memory device, since a 6F ² cells, compared to 4F ² cells, the chip area occupied by the memory cell array portion is increased.

An object of the present invention is to provide a technique for reducing noise in a semiconductor memory device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, it includes a plurality of word lines, a plurality of bit lines arranged so as to intersect the plurality of word lines, and a plurality of memory cells coupled to the word lines and the bit lines. When a semiconductor memory device is configured, the memory cell is a capacitor formed including a recess in a semiconductor substrate and a polysilicon layer provided in the recess when a minimum processing dimension of the semiconductor device is indicated by F; laminated on the polysilicon layer, and a transistor which is a vertical structure having a channel by intrinsic semiconductor, one formed in the area of 4F ^2, further said word lines, between adjacent bit lines It is formed so as to surround each bit line by being inserted.

According to the above means, there is provided a capacitor formed including the concave portion in the substrate of the semiconductor device and the polysilicon layer provided in the concave portion, and a channel laminated with the polysilicon layer and made of an intrinsic semiconductor. memory cell of 4F ² by being a vertical type structure is formed by. The word lines penetrate between adjacent bit lines and surround the individual bit lines, thereby exhibiting a shielding function between adjacent bit lines and achieving a reduction in crosstalk noise between adjacent bit lines.

A metal wiring layer is laminated corresponding to the word line, and the word line and the corresponding metal wiring layer are electrically coupled to reduce the resistance of the word line. Thus, the word rise time can be shortened.

Also, the semiconductor device includes a plurality of word lines, a plurality of bit lines arranged to cross the plurality of word lines, and a plurality of memory cells coupled to the word lines and the bit lines. When a semiconductor memory device is formed, the memory cell includes a capacitor including a recess in a semiconductor substrate and a semiconductor layer provided in the recess when a minimum processing dimension of the semiconductor device is indicated by F; the stacked, it is one formed in a region of 4F ² and a and vertical structure transistors have a channel by intrinsic semiconductor. Further, when the adjacent bit lines are formed in different layers from each other, and when attention is paid to the adjacent bit lines, the memory cell is connected each time the bit lines cross the word lines.
Arrange alternately.

According to the above means, there is provided a capacitor formed including the concave portion in the substrate of the semiconductor device and the polysilicon layer provided in the concave portion, and a channel laminated on the polysilicon layer and formed of an intrinsic semiconductor. memory cell of 4F ² by being a vertical type structure is formed by. Also, adjacent bit lines are formed in different layers from each other,
Focusing on this adjacent bit line, by alternately arranging the memory cells each time the bit line intersects with the word line, it is possible to equalize the bit line load and unbalance the load as viewed from the sense amplifier. Is easily resolved.

At this time, by exchanging the adjacent bit lines by the bit line cross, the crosstalk noise between the bit lines can be reduced.

When the word line is formed by a first semiconductor layer and the bit line is formed by a second semiconductor layer different from the first semiconductor layer, a first metal wiring corresponding to the word line is formed. By stacking layers and electrically connecting the word line and the corresponding first metal wiring layer, the resistance of the word line is reduced, and a second metal different from the first metal wiring layer is provided. a wiring layer, by multi-layering the bit line by the said second semiconductor layer, 4F ² -2
Implement the intersection cell.

[0023]

FIG. 23 shows an SDRAM (Synchronous Dynamic Random Access Memory) which is an example of a semiconductor memory device according to the present invention.

The SDRAM 32 shown in FIG. 23 is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique, although not particularly limited. The SDRAM 32 includes a memory cell array 200A forming a memory bank A and a memory cell array 200B forming a memory bank B. Each of the memory cell arrays 200A and 200B includes dynamic memory cells arranged in a matrix, and the selection terminals of the memory cells arranged in the same column are coupled to a word line (not shown) for each column, and are connected to the same row. Data input / output terminals of the arranged memory cells are coupled to complementary data lines (not shown) for each row.

One word line (not shown) of the memory cell array 200A is driven to a selected level in accordance with a result of decoding a row address signal by the row decoder 201A. A complementary data line (not shown) of the memory cell array 200A is coupled to a sense amplifier and column selection circuit 202A. Sense amplifier and column selection circuit 202A
Is an amplifier circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from a memory cell. The column selection circuit in this case is a switch circuit for selecting complementary data lines individually and conducting the data to the complementary common data line 204. The column selection circuit is selectively operated according to the result of decoding the column address signal by the column decoder 203A. Similarly, the row decoder 201B, the sense amplifier and the column selection circuit 202 are provided on the memory cell array 200B side.
B, a column decoder 203B is provided. The complementary common data line 204 is connected to the output terminal of the input buffer 210 and the input terminal of the output buffer 211. The input terminal of the input buffer 210 and the output terminal of the output buffer 211 are 16-bit data input / output terminals I / O0 to I / O1.
5 is connected.

The row address signal and the column address supplied from the address input terminals A0 to A11 are taken into the column address buffer 205 and the row address buffer 206 in an address multiplex format. The output of the column address buffer 205 is the column address counter 20
7, the column address counter 207 sends the column address as the preset data, or a value obtained by sequentially incrementing the column address as an initial value, to the redundancy repair circuit 214 at the subsequent stage according to the operation mode. Output.

In the redundancy repair circuit 214, the column address (the initial address in the burst mode) output from the column address buffer 205 is not particularly limited.
The column address counter 207 performs a redundancy judgment on the incremented address. In this address comparison, if both addresses do not match,
This means that redundancy relief has not been performed for the address.
5 or the address incremented by the column address counter 207 is transmitted to the column decoders 203A and 203B.
However, in the address comparison by the redundancy rescue circuit 214, if the two addresses match, it means that the address has been rescued by the redundant bit, and thus the column address output from the column address buffer 205 or the column address An address for selecting a redundant bit in place of the address incremented by the address counter 207 is the column decoder 203A, 203B.
Is transmitted to Redundancy relief is performed by such address replacement.

The memory cell arrays 200A, 200
B includes a dynamic memory cell, and it is necessary to perform a refresh operation at predetermined time intervals in order to maintain a storage state. The refresh operation is performed in the memory cell array 20.
A refresh counter 208, which is enabled by selecting the word lines 0A and 200B and capable of generating a refresh address for such a refresh operation, is provided.

The controller 212 includes, but is not limited to, a clock signal CLK and a clock enable signal CK.
E, chip select signal CS * (symbol * means that the signal attached thereto is a row enable signal), column address strobe signal CAS *, row address strobe signal RAS *, write enable signal WE *, etc. A command decode circuit 310 for generating an operation mode signal by decoding a command given by a combination of external control signals, and a timing control circuit 32 for forming an internal timing signal.
0 and a mode register 300 for holding operation mode information and test mode information.

The clock signal CLK, the clock enable signal CKE, the chip select signal CS *,
Column address strobe signal CAS *, row address strobe signal RAS *, and write enable signal W
Various control signals such as E * are transmitted from the CPU 31 via the system bus BUS. The clock signal CLK is S
This is used as the master clock of the DRAM 32, and other external input signals are made significant in synchronization with the rising edge of the clock signal CLK. The chip select signal CS * indicates the start of a command input cycle by its low level. When the chip select signal is at a high level (chip unselected state), other signal inputs have no meaning.
However, the internal operation such as the selected state of the memory bank or the burst operation is not affected by the change to the chip non-selected state. Each signal of RAS *, CAS *, and WE * is a significant signal when defining a command cycle. The clock enable signal CKE is a signal for indicating the validity of the next clock signal. If the signal CKE is at a high level, the rising edge of the next clock signal CLK is valid, and if it is at a low level, it is invalid. . further,
Although not shown, the output buffer 2 in the read mode
An external control signal for controlling the output enable of the output buffer 11 is also supplied to the controller 212. When the signal is at a high level, for example, the output buffer 211 is set to a high output impedance state.

The signal input from the address input terminal A11 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input signal from the address input terminal A11 is at a low level, the memory bank A is selected, and when it is at a high level, the memory bank B is selected. The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the unselected memory bank are not selected, the input buffer 210 and the output buffer of the selected memory bank only. 211
It can be performed by a process such as connection to.

In the precharge command cycle,
An input signal from the address input terminal A11 indicates a mode of a precharge operation for a complementary data line or the like, a high level thereof indicates that a precharge target is both memory banks, and a low level thereof indicates a state of A11. One of the designated memory banks is to be precharged.

The column address is the clock signal CL
It is defined by the logic levels of A0 to A7 in a read command cycle or a write command cycle synchronized with the rising edge of K. Then, the column address defined in this way is used as a start address (column initial address) for burst access.

Next, the memory cell arrays 200A, 200A
The detailed configuration of 00B will be described.

The above memory cell arrays 200A, 200B
Where the 4F ² -1 intersection cell is applied and 4F ^2-
In some cases, two intersection cells are applied.

First, the memory cell arrays 200A, 200A
A case where a 4F ² -1 intersection cell is applied to 00B will be described.

FIG. 3 shows an example of arrangement of 4F ² -1 intersection cells.

The memory cell MC is formed by a charge storage capacitor and a vertical transistor. Said charge storage capacitor is a capacitor formed by providing a polysilicon layer in a recess formed in the semiconductor substrate, that the vertical transistor is formed directly above the capacitor, 4F ² memory cell can be realized.

A plurality of word lines WL and a plurality of bit lines BL are formed so as to intersect with the plurality of word lines WL, and memory cells MC are provided at locations where the word lines WL and the bit lines BL intersect. The plurality of bit lines BL include a plurality of pairs of bit lines at complementary levels, and a plurality of sense amplifiers are provided to amplify a potential difference between the pair of bit lines. For example, a bit line pair BL1, BL1B is coupled to the sense amplifier SA1. In the case of the 4F ² -1 intersection cell, the bit line BL1 is arranged on the left side of the sense amplifier SA1 as viewed in the drawing, and the bit line BL1B at a complementary level to the bit line BL1B is arranged on the right side of the sense amplifier SA1. When amplifying the minute potential of the bit line BL, the potential of the bit line BL1B is used as a reference. Other sense amplifiers SA2, SA3,
In SA4, as in the case of the sense amplifier SA1, the bit lines BL2, BL3,
BL4 is arranged, and a complementary bit line BL2 is provided.
B, BL3B, BL4B are the sense amplifiers SA2, S
It is arranged on the right side of A3 and SA4.

FIG. 5B shows a configuration example of the sense amplifier SA1 shown in FIG.

N channel type MOS transistors 26 and 2
7 and p-channel MOS transistors 28 and 29 are coupled to form an amplifier section for amplifying the potential difference of the bit line. N-channel MOS transistors 26 and 27 connected in series and p-channel MOS
From the series connection of the transistors 28 and 29 to the common line C
SN and CSP are retrieved. When reading memory cell data via the bit line BL1, the bit line BL1
When the potential of B is set to the reference level and the memory cell data is read through the bit line BL1B, the bit line BL
The potential of 1 is set as the reference level. In such a configuration, n-channel MOS transistors 23 and 2 for equalizing a bit line pair by equalizing control signal BLEQ are used.
4, 25 are provided.

Here, a technique to be compared with the present invention will be described with reference to FIGS. 8, 16B and 17B.

FIG. 8 shows a configuration example of the 4F ² -1 intersection cell.

The plurality of word lines WL1 to WL12 intersect with the plurality of bit lines BL, and a memory cell MC is arranged at the intersection. A plurality of word lines WL1 to WL12
Is formed by the first polysilicon layer (Poly-1). The plurality of bit lines BL are connected to the first metal wiring layer (M-
1). A plurality of word lines WL1 to WL
The arrangement pitch of 12 or a plurality of bit lines BL is set to “2F”.

FIG. 16B shows a cross section taken along the line AA in FIG. 8, and FIG. 17B shows a cross section taken along the line BB in FIG.
A line cross section is shown.

A recess is provided in the semiconductor substrate PL (Sub), and the polysilicon layer SN (p) is
poly-Si) is formed. At this time, a capacitor is formed by the inner wall surface of the concave portion and the surface facing the polysilicon layer SN. This capacitor is used as a charge storage capacitor in the memory cell, and a PLED transistor is formed directly above the capacitor. That is, immediately above the polysilicon layer SN (poly-Si) forming the capacitor, the first
Barrier film BR1 _(Si 3 _{N 4)} channel by intrinsic semiconductor via a CH (i-Poly) is laminated further on the channel CH (i-Poly), the second barrier film B
The polysilicon layer BN (po) is interposed via R2 (Si ₃ N ₄ ).
ly-Si) is formed. This polysilicon layer BN
Is through a through hole (M1 to Poly)
The bit line BL (M
1). Then, the channel CH (i-P
and the first barrier films BR1 (Si ₃
N ₄ ) and the second barrier film BR 2 (Si ₃ N ₄ ) from the side so as to surround the word line WL of the polysilicon layer.
(Poly-Si) is formed. Polysilicon layer BN
(Poly-Si) is used as the drain electrode of the PLED,
The polysilicon layer SN (poly-Si) is used as the source electrode of the PLED transistor, and the polysilicon layer forming the word line WL is used as the gate electrode of the PLED transistor.

However, in the above configuration, since adjacent bit lines are formed by the same wiring layer,
Crosstalk noise between adjacent bit lines is relatively large.

Therefore, in order to reduce the crosstalk noise between the adjacent bit lines, the memory cell array 200
16A and FIG. 16A, the word lines WL are formed so as to surround the individual bit lines BL by being inserted between adjacent bit lines, as shown in FIGS. Apply Here, FIG.
FIG. 17A is a sectional view corresponding to FIG.
It is sectional drawing corresponding to 7 (B).

FIG. 16 (A) and FIG. 17 (A)
Is different from that shown in FIGS. 16 (B) and 17 (B).
This is because the second barrier film BR2 (Si₃N₄) Laminated
Bit line with polysilicon layer (Poly-Si)
Points used as BL, and such bit lines BL
Are formed in parallel, this individual bit line B
Word line WL is formed so as to cover L. this
In this case, the word line WL is formed of a polysilicon layer (Poly-S
formed by i). In such a configuration,
Line WL functions as a shield between adjacent bit lines BL
4F ²-1 intersection cell, adjacent bit line
Cross talk noise between BL can be reduced
You.

In the above-described configuration, the word line WL is formed of a polysilicon layer (Poly-Si) and has a relatively high resistance. By connecting a metal wiring layer to the word line WL, the word line WL is formed. Low resistance can be achieved. FIG. 20A and FIG. 21A show a configuration example in that case. The cross section shown in FIG. 20A corresponds to FIG. 16A, and the cross section shown in FIG. 20A corresponds to FIG. FIG. 20 (A) and FIG.
As shown in (A), when the word line WL is formed of a polysilicon layer (Poly Si), a first metal wiring layer M1 is formed along the word line WL and above the word line. , Through hole (M1to Po
ly), the first metal wiring layer M1 is connected to the word line W
Binds to L. Since the resistance value of the first metal wiring layer M1 is much smaller than that of the polysilicon layer (Poly-Si), the first metal wiring layer M1 is coupled to the word line WL formed by the polysilicon layer (Poly-Si). By doing
The resistance of the word line WL can be reduced. By reducing the resistance of the word line WL, a voltage drop on the word line WL can be suppressed.

Next, the memory cell arrays 200A, 200A
A case where a 4F ² -2 intersection cell is applied to 00B will be described.

[0052] Figure 4 is a layout example of ^4F 2 -2 intersection cell is shown.

A plurality of word lines WL and a plurality of bit lines BL
Are crossed, and the memory cells MC are alternately arranged at the crossing points. BL1 and BL1B, BL2 and BL2B, BL
Complementary bit line pairs are formed by BL3 and BL3B, and BL4 and BL4B. Although not particularly limited, the bit lines BL1, BL2, BL3, BL4 are formed by the first metal wiring layer M1, and the bit lines BL1B, BL2
B, BL3B and BL4B are formed by the second metal wiring layer. A plurality of sense amplifiers for amplifying the potential of the bit line pair are provided. For example, sense amplifier SA
1 amplifies the potential of bit lines BL1 and BL1B, sense amplifier SA2 amplifies the potential of bit lines BL2 and BL2B, sense amplifier SA3 amplifies the potential of bit lines BL3 and BL3B, and sense amplifier SA4 amplifies the potential of bit line BL4. ,
Amplify the potential of BL4B. As described above, since the potential of the bit line at the complementary level is amplified by the sense amplifier, noise components mixed in the complementary bit line pair are canceled in the amplification process of the sense amplifier. ing.

FIG. 2 shows an 8F, which is a comparison object of the present invention.
Arrangement of ² -2 intersection cell is shown.

A plurality of word lines WL and a plurality of bit lines BL are formed so as to intersect with the word lines WL, and memory cells MC are provided at locations where the word lines WL and the bit lines BL intersect. The plurality of bit lines BL include a plurality of bit line pairs set to complementary levels. A plurality of sense amplifiers are provided to amplify the potential difference between the bit line pair. For example, a bit line pair BL1 and BL1B is coupled to the sense amplifier SA1, and the potential difference between the bit line pair BL1 and BL1B is amplified by the sense amplifier SA1. A bit line pair BL2, BL2B is coupled to the sense amplifier SA2, and a potential difference between the bit line pair BL2, BL2B is amplified by the sense amplifier SA2. Such 8F ²
Arrangement example -2 intersection cell is widely used in the DRAM, since one memory cell MC is formed in a region of 8F ^2, thus the memory size is relatively large.

[0056] In contrast, ^4F 2 -2 of FIG 4
In the intersection cell, one of the memory cell MC in the area of 4F ²
Is formed, the memory size is smaller than that of the 8F ² -2 intersection cell.

FIG. 5A shows the sense amplifier SA1.
Is shown.

N channel type MOS transistors 16, 1
7 and p-channel MOS transistors 18 and 19 are coupled to form an amplifier section for amplifying the potential difference of the bit line. N-channel MOS transistors 16 and 17 connected in series, and p-channel MOS
From the series connection of the transistors 18 and 19 to the common line C
SN and CSP are retrieved. The sense amplifier SA1 is
Bit line pairs BL1 and BL located on the left and right sides of the page
In order to prevent data destruction on the bit line,
An n-channel MOS transistor 11, 12 for separating the bit line pair BL1, BL1B located on the left side of the sense amplifier SA1 from the amplifier section by the shared control signal SHR-L, and a sense amplifier by the shared control signal SHR-R. There are provided n-channel MOS transistors 20 and 21 for separating the bit line pair BL1 and BL1B located on the right side of SA1 from the amplifier section. Further, n-channel MOS transistors 13, 14, and 15 for equalizing the bit line pair by the equalization control signal BLEQ are provided.

The other sense amplifiers have the same configuration.

FIG. 10 shows the memory cell array 200
A, an example of an array configuration of 4F ² -2 intersection cells applied to 200B is shown.

A plurality of bit lines BL are formed to cross a plurality of word lines WL. When the minimum processing size of the semiconductor device is indicated by F, the arrangement pitch of the word lines WL is 2
F. The plurality of word lines WL are formed using the second polysilicon layer Poly-2. Bit line BL
In order to realize the ^4F 2 -2 intersection cell, the bit line pair BL1, BL1B each complementary levels, BL2, B
L2B has two layers. That is, the bit line BL
Has a lower bit line and an upper bit line, the lower bit line is realized by a first metal wiring M-1, and the upper bit line is realized by a second metal wiring M-2.

For example, the bit lines BL1 and BL2 are lower bit lines formed by the first metal wiring M-1 at locations where they intersect with the word lines WL1 to WL4.
~ WL8, the second metal wiring M-
2 as an upper bit line. Bit lines BL1B, B
L2B is displaced from the bit lines BL1 and BL2 by one pitch, respectively, and at a place where it intersects with the word lines WL1 to WL4, is formed as an upper bit line by the second metal wiring M-2 and intersects with the word lines WL5 to WL8. In this case, the lower bit line is formed by the first metal wiring M-1.
A bit line coupling unit for coupling the lower bit line and the upper bit line is provided. The size of the bit line coupling portion in the bit line extending direction is 5F. The bit lines BL1B and BL2B are connected to the first metal wiring M
-1 and the upper bit line by the second metal interconnection M-2 are connected by a contact hole.
On the other hand, the bit lines BL1 and BL2 have the first polysilicon layer Poly-1 interposed at the bit line coupling portion in order to avoid contact with the adjacent bit line, and the lower bit line of the first metal wiring M-1. Line to first polysilicon layer P
These are coupled by a through hole to poly-1 and a through hole from the upper bit line by the second metal wiring M-2 to the first polysilicon layer Poly-1.

Each time the adjacent bit line crosses the word line, the memory cell MC has the memory cells arranged alternately between the adjacent bit lines. They are alternately arranged with a shift of one pitch for each word line along the extending direction of the bit lines. For example, the memory cell MC1 is provided at the intersection of the word line WL1 and the bit line BL1B,
C2 is provided at the intersection of the word line WL1 and the bit line BL2B, and the memory cell MC3 is provided at the intersection of the word line WL2 and the bit line BL1.
C4 is provided at the intersection of word line WL2 and bit line BL2. The memory cell MC5 is connected to the word line W
The memory cell MC6 is provided at the intersection of the word line WL3 and the bit line BL2B, and the memory cell MC7 is provided at the intersection of the word line WL4 and the bit line BL1. The memory cell MC8 is provided at the intersection of the word line WL4 and the bit line BL2.

FIG. 9 shows the memory cell array 200
A, array configuration example of ^4F 2 -2 intersection cell to be compared with the applied ^4F 2 -2 intersection cell 200B is shown in FIG. 18 (A) is sectional view taken along line C-C in FIG. 9 Is shown.

In FIG. 9, the bit line BL is divided into two layers.
By allocating adjacent bit lines to different layers, short circuit between adjacent bit lines is prevented. Representatively shown 4
Bit lines BL1, BL1B, BL2, BL2B
In the bit line coupling portion, the first metal wiring layer M-1
From the metal wiring layer M-2 or the second metal wiring layer M-2 to the first
Changed to metal wiring layer M-1. 5F. The size of the bit line coupling portion in the bit line extending direction is 5F. The bit lines BL1B and BL2B are changed from the second metal wiring layer M-2 to the first metal wiring layer M-1 via the contact holes (M2 to M1), while the bit lines BL1 and BL2 are A polysilicon layer is interposed to prevent short circuit. The memory cell MC is coupled to the bit line BL by the first metal wiring layer M-1, but is not coupled to the bit line BL by the second metal wiring layer M-2. Therefore, the bit line B by the first metal wiring layer M-1
L and the bit line BL formed by the second metal wiring layer M-2 have different loads on the bit line BL as viewed from the sense amplifier. For example, when a low level signal is sensed by the sense amplifier and a high level signal And when you sense
The time until the logic is determined may be different.

On the other hand, the configuration shown in FIG. 10 is a configuration in which the bit line and the second metal wiring layer M-1 are formed by the first metal wiring layer M-1.
-2, the memory cells MC are equally coupled to both of the bit lines, and the memory cells MC are alternately arranged between adjacent bit lines every time they cross the word lines.
The bit line load is equalized. For this reason, in the sense amplifier, the conditions for the case of sensing the low level and the case of sensing the high level can be matched, and the time until the logic of the low level is determined and the time until the logic of the high level are determined. Can reduce the difference.

Next, the case where the crosstalk noise between the bit lines is reduced by crossing the bit lines will be described with reference to FIGS. 6 and 7. FIG.

In FIG. 6 and FIG. 7, although not particularly limited, the bit line shown by a solid line is formed by a first metal wiring layer, and the bit line shown by a broken line is formed by a second metal wiring layer.

In the case shown in FIG. 6A, the bit lines do not cross. In the structure shown in FIG. 6B, the formation layers of the bit lines are exchanged, but the bit lines are not crossed. In the configuration shown in FIG. 6C, a bit line cross is performed between the bit lines BL1, BL1B, BL2, and BL2B, and the bit lines BL3, BL3B, B
A bit line cross is performed between L4 and BL4B. However, although the bit lines are crossed, the adjacent bit lines are basically the same, so that crosstalk noise between the bit lines cannot be sufficiently reduced.

There are many variations of the bit line cross as shown in FIG. In FIG. 7, the bit line indicated by a solid line is formed by a first metal wiring layer, and the bit line indicated by a broken line is formed by a second metal wiring layer. The connection between the bit line formed by the first metal wiring layer and the bit line formed by the second metal wiring layer is performed through a contact hole. The position of the contact hole is indicated by a dot.

The structure shown in FIG. 7A is a complementary bit line pair BL1, BL1B, BL2, BL2B, BL3, B
The adjacent bit lines cross each other while changing the formation layer for each of L3B, BL4, and BL4B. According to such a configuration, each time a bit line is crossed, the adjacent bit line is changed, so that noise between adjacent bit lines can be reduced.

In the structure shown in FIG. 7B, the bit lines BL1B and BL2 adjacent to each other are only changed in the formation layer, but the bit lines BL1 and BL2B
, Bit line crossing is performed in a state shifted by 3 pitches. Similarly, adjacent bit lines BL
For 3B and BL4, only the formation layer is changed, but for bit lines BL3 and BL4B, bit line crossing is performed with a shift of 3 pitches.
According to such a bit line cross, when attention is paid to the bit lines BL1 and BL2B and the bit lines BL3 and BL4B, each time the bit line is crossed, the adjacent bit line is changed. Less is needed.
Incidentally, the bit lines BL1 and BL2B are connected, and the bit line B
L3 and BL4B, the MOS transistors 11, 12, and 2 in the sense amplifiers SA1 to SA4 are connected.
By controlling the off-off operations of 0 and 21 (see FIG. 5A), the signal of the bit line is transmitted to only one of the sense amplifiers.

The structure shown in FIG.
A bit line cross is performed between L1, BL1B, BL2, BL2B, and BL3, and bit lines BL3B, BL4,
A bit line cross is performed between BL4B. In such a configuration, each time a bit line is crossed, an adjacent bit line is changed, so that the influence of crosstalk between bit lines can be reduced. Since the bit lines BL1B and BL2B are coupled and the bit lines BL3B and BL4B are coupled, the MOS transistors 11 in the sense amplifiers SA1 to SA4,
The on / off operations of 12, 20, and 21 (see FIG. 5A) are controlled so that the bit line signal is transmitted to only one of the sense amplifiers.

Next, a specific layout example in the case of performing a bit line cross will be described.

FIG. 1 shows the memory cell array 200
A, an example of arrangement of 4F ² -2 intersection cells applied to 200B is shown.

A plurality of bit lines BL are formed to cross a plurality of word lines WL. When the minimum processing size of the semiconductor device is indicated by F, the arrangement pitch of the word lines WL is 2
F. The plurality of word lines WL are formed using the second polysilicon layer Poly-2. Bit line BL
In order to realize the ^4F 2 -2 intersection cell, the bit line pair BL1, BL1B each complementary levels, BL2, B
L2B has two layers. That is, the bit line BL
Has a lower bit line and an upper bit line, the lower bit line is realized by a first metal wiring M-1, and the upper bit line is realized by a second metal wiring M-2. The potential difference between the bit line pair BL1 and BL1B is amplified by a first sense amplifier (not shown), and the potential difference between the bit line pair BL2 and BL1
The potential difference between 2B is amplified by a second sense amplifier (not shown).

For example, the bit lines BL1 and BL2 are upper bit lines formed by the second metal wiring M-2 at the locations where they intersect with the word lines WL1 to WL4.
~ WL8, the first metal wiring M-
1 is a lower bit line. Bit lines BL1B, B
L2B is shifted from the bit lines BL1 and BL2 by one pitch (corresponding to F in this case), and the word line WL1 is shifted.
~ WL4, the first metal wiring M-
1 and lower word lines WL5 to WL8.
At the intersection with the upper bit line formed by the second metal wiring M-2. A bit line coupling unit for coupling the lower bit line and the upper bit line is provided. The size of the bit line coupling portion in the bit line extending direction is 7F.

To reduce bit line noise, bit line B
As L1 and BL2 are crossed at the bit line coupling portion, the arrangement positions of the bit lines are exchanged. FIG. 19A shows a main cross section of the bit line coupling portion in this case. That is, the bit line BL1 is formed by the second metal wiring layer M-2 at a position intersecting the word lines WL1 to WL4, but at the bit line coupling portion via the contact hole.
1 and a part of the first metal wiring layer M-1 is formed so as to extend in parallel with the word line WL and then bend so as to be parallel with the other bit lines. The bit line BL1 is formed at a position crossing the word lines WL5 to WL8 two pitches (2 pitches) from the bit line formation position at a position crossing the word lines WL1 to WL4.
The position is shifted by F).

Similarly, bit line BL2 is connected to word line WL
1 to WL4, the second metal wiring layer M
-2, but at the bit line coupling,
Extending in parallel with the word line WL, and then coupled to the first metal wiring layer M-1 via a contact hole;
The first metal wiring layer M-1 is formed so as to extend in parallel with other bit lines, so that word lines WL5 to WL5 are formed.
The position where the bit line BL2 is formed at the position where the bit line BL8 intersects is shifted by two pitches (2F) from the position where the bit line BL2 is formed at the position where the bit line BL1 crosses the word lines WL1 to WL4.

Although the bit lines BL1B and BL2B do not cross bit lines, the formation layers are exchanged. In other words, the bit lines BL1B and BL2B are formed by the first metal wiring layer M-1 at the locations where they intersect with the word lines WL1 to WL4.
Is formed by the second metal wiring layer M-2. The formation layers of the bit lines BL1B and BL2B are exchanged at the bit line coupling portion. At this time, as shown in FIG. 19B, the bit lines BL1B and BL2B are connected to the first polysilicon layer Po in order to avoid electrical contact with adjacent bit lines in the bit line coupling portion.
This is performed via ly-1. The connection between the first metal wiring layer M-1 and the first polysilicon layer Poly-1 and the connection between the second metal wiring layer M-1 and the first polysilicon layer Poly-1 are formed through through holes (M1 topory, M2t
o poly).

The bit line cross between the bit lines BL1B and BL2B, and the bit lines BL1B and BL2B
In the bit line coupling portion, the dimension in the bit line extending direction is set to 7F so that the formation layer can be replaced.

The memory cells MC are alternately arranged with a shift of one pitch for each word line along the extending direction of the bit lines.
For example, the memory cell MC1 is provided at the intersection of the word line WL1 and the bit line BL1B, and the memory cell MC2
Is provided at the intersection of the word line WL1 and the bit line BL2B, and the memory cell MC3 is provided at the intersection of the word line WL2 and the bit line BL1.
Are provided at intersections between word lines WL2 and bit lines BL2. The memory cell MC5 is connected to the word line WL3
Cell MC6 is provided at the intersection of word line WL3 and bit line BL2B, and memory cell MC7 is provided at the intersection of word line WL2 and bit line BL2B.
The memory cell MC8 is provided at the intersection of the word line WL4 and the bit line BL2. The word line WL and the bit line BL
Is connected to the memory cell MC via a through hole.

FIG. 18B shows a cross section taken along line DD in FIG. Memory cells MC1, MC3, MC6, M
As a representative example of the configuration of C8, the plurality of memory cells MC have the same configuration. For example, the memory cell MC8 is configured as follows.

A concave portion is provided in the semiconductor substrate PL (Sub), and the concave portion is formed in the concave portion via an insulating film.
poly-Si) is formed. At this time, a capacitor is formed by the inner wall surface of the concave portion and the surface facing the polysilicon layer SN. This capacitor is used as a charge storage capacitor in the memory cell, and a PLED transistor is formed directly above the capacitor. That is, immediately above the polysilicon layer SN (poly-Si) forming the capacitor, the first
Barrier film BR1 _(Si 3 _{N 4)} channel by intrinsic semiconductor via a CH (i-Poly) is laminated further on the channel CH (i-Poly), the second barrier film B
The polysilicon layer BN (po) is interposed via R2 (Si ₃ N ₄ ).
ly-Si) is formed. This polysilicon layer BN
Is through a through hole (M1 to Poly)
The bit line BL (M
1). Then, the channel CH (i-P
and the first barrier films BR1 (Si ₃
N ₄ ) and the second barrier film BR 2 (Si ₃ N ₄ ) from the side so as to surround the word line WL 1 made of a polysilicon layer.
(Poly-Si) is formed. Polysilicon layer BN
(Poly-Si) is used as the drain electrode of the PLED,
The polysilicon layer SN (poly-Si) is used as the source electrode of the PLED transistor, and the polysilicon layer forming the word line WL is used as the gate electrode of the PLED transistor.

As described above, the concave portion is provided in semiconductor substrate PL (Sub), and the inner wall surface of the concave portion and polysilicon layer S
N is the capacitor formed by the opposing faces of, by the memory cells MC is formed by PLED transistors are arranged directly above the capacitor can be formed at a ratio of one to an area of 4F ² .

As described above, the memory cell array shown in FIG. 1 is a 4F ² -2 intersection cell, and adjacent bit lines are replaced by a bit line cross, so that crosstalk noise between bit lines can be reduced.

FIG. 11 shows the memory cell array 200
A, another example of an array configuration of 4F ² -2 intersection cells applied to 200B is shown.

The configuration shown in FIG. 11 is largely different from that shown in FIG. 1 in the way bit lines are crossed.

In the configuration shown in FIG. 11, bit line BL
2 and BL2B, the formation layer is replaced,
A bit line cross is performed between the bit lines BL1 and BL1B.

The bit line BL2B is connected to the word lines WL1 to WL
The portion that intersects L4 is formed by the second metal wiring layer M-2, while the portion that crosses the word lines WL5 to WL8 is formed by the first metal wiring layer M-1. In the bit line BL2B, in the bit line coupling portion, coupling between the bit line by the second metal wiring layer M-2 and the bit line by the first metal wiring layer M-1 is performed by a contact hole.

The bit line BL2 is connected to the word lines WL1 to WL
4 are formed by the first metal wiring layer M-1; however, at the positions crossing the word lines WL5 to WL8, they are formed by the second metal wiring layer M-2. The bit line BL2 is connected to the first
A bit line formed by the metal wiring layer M-1 and a second metal wiring layer M;
-2, but the first polysilicon layer Po is used to avoid electrical contact with adjacent bit lines.
ly-1 is passed. First metal wiring layer M-1 and second metal wiring layer M-1
A metal wiring layer M-2 and a first polysilicon layer Poly-1
Are connected via a through hole.

The bit line BL1 is formed by the first metal wiring layer M-1, and the bit line BL2 is formed by the second metal wiring layer M-2. Crossed. The size of the bit line coupling portion in the bit line extending direction is 9F.

In such a structure, each time the word line WL intersects between adjacent bit lines, the memory cell M
Since Cs are alternately arranged with a shift of one pitch, the load on the bit lines can be equalized as in the case of FIG. In addition, since the bit line adjacent to the bit line BL2 is replaced at the bit line junction by the cross of the bit lines BL1 and BL1B, noise between bit lines can be reduced.

FIG. 12 shows the memory cell array 200
A, another example of an array configuration of 4F ² -2 intersection cells applied to 200B is shown.

The configuration shown in FIG. 12 is greatly different from that shown in FIG. 1 in the way the bit lines BL are crossed.

In the configuration shown in FIG. 12, bit line BL
2 and BL2B, the formation layer is replaced,
A bit line cross is performed between the bit lines BL1 and BL1B.

The bit line BL2B is connected to the word lines WL1 to WL
A portion intersecting with L4 is formed by the first metal wiring layer M-1, and a portion intersecting with the word lines WL5 to WL8 is formed by the second metal wiring layer M-2. The formation layer of the bit line BL2B is exchanged via the first polysilicon layer Poly-1 and the first metal wiring layer M-1 at the bit line coupling portion. First polysilicon layer Poly
-1 and the first metal wiring layer M-1 are connected via a through hole.

The bit line BL2 is connected to the word lines WL1 to WL
4 are formed by the second metal wiring layer M-2, and at the intersections with the word lines WL5 to WL8,
The first metal wiring layer M-1 is formed. Bit line BL
In No. 2, the formation layers are exchanged at the bit line junction, but in order to avoid contact with the bit line BL2B,
The bit line coupling portion is formed to be bent toward the bit line BL1B side so as to be shifted by one pitch. This bending is performed by the first metal wiring layer M-1.

The bit line BL1 is connected to the second metal wiring layer M-2.
Is formed by The bit line BL1B is formed by the first metal wiring layer M-1 at a position crossing the word lines WL1 to WL4, and is formed by the second metal wiring layer M-2 at a position crossing the word lines WL5 to WL8. You. The bit lines BL1 and BL1B are crossed at the bit line coupling portion. At this time, the bit line BL1B is passed through the first polysilicon layer Poly-1 to avoid contact between the bit lines BL1 and BL2. The dimension of the bit line coupling portion in the bit line extending direction is 13F.

In such a configuration, each time the word line WL intersects between adjacent bit lines, the memory cell M
Since Cs are alternately arranged with a shift of one pitch, the load on the bit lines can be equalized as in the case of FIG. In addition, since the bit line adjacent to the bit line BL2 is replaced at the bit line junction by the cross of the bit lines BL1 and BL1B, noise between bit lines can be reduced.

FIG. 13 shows the memory cell array 200
A, another example of an array configuration of 4F ² -2 intersection cells applied to 200B is shown.

The configuration shown in FIG. 13 is greatly different from that shown in FIG. 1 in the way the bit lines BL are crossed.

In the configuration shown in FIG. 13, bit line BL
For 1B and BL2, the formation layers are exchanged,
A bit line cross is performed between the bit lines BL1 and BL2B.

The bit line BL1B is connected to the word lines WL1 to WL
The portion intersecting with L4 is formed by the second metal wiring layer M-2, but the portion intersecting with the word lines WL5 to WL8 is formed by the first metal wiring layer M-1. In the bit line BL1B, the bit line formed by the second metal wiring layer M-2 and the bit line formed by the first metal wiring layer M-1 are connected by a contact hole at a bit line connecting portion.

The bit line BL2 is connected to the word lines WL1 to WL
4 are formed by the first metal wiring layer M-1; however, at the positions crossing the word lines WL5 to WL8, they are formed by the second metal wiring layer M-2. The bit line BL2 is connected to the first
A bit line formed by the metal wiring layer M-1 and a second metal wiring layer M;
-2, but the first polysilicon layer Po is used to avoid electrical contact with adjacent bit lines.
ly-1 is passed. First metal wiring layer M-1 and second metal wiring layer M-1
A metal wiring layer M-2 and a first polysilicon layer Poly-1
Are connected via a through hole.

The bit line BL1 is formed by a first metal wiring layer M-1, and the bit line BL2B is formed by a second metal wiring layer M-2.
Crossed at the bit line coupling section. The size of the bit line coupling portion in the bit line extending direction is 11F.

Even in such a structure, each time the word line WL intersects between adjacent bit lines, the memory cell M
Since Cs are alternately arranged with a shift of one pitch, the load on the bit lines can be equalized as in the case of FIG. Since the bit lines adjacent to the bit lines BL1 and BL2B are changed at the bit line junction due to the cross of the bit lines BL1 and BL2B, noise between bit lines can be reduced.

FIG. 14 shows the memory cell array 200
A, another example of an array configuration of 4F ² -2 intersection cells applied to 200B is shown.

The configuration shown in FIG. 14 is greatly different from that shown in FIG. 1 in the way the bit lines are crossed.

In the configuration shown in FIG. 14, bit line BL
For 2B, the formation layers are exchanged, and the bit line B
A bit line cross is performed between L1, BL1B, and BL2.

Bit line BL2B is connected to word lines WL1 to WL
The portion intersecting with L4 is formed by the second metal wiring layer M-2, but the portion intersecting with the word lines WL5 to WL8 is formed by the first metal wiring layer M-1. In the bit line BL2B, the bit line formed by the second metal wiring layer M-2 and the bit line formed by the first metal wiring layer M-1 are connected by a contact hole at a bit line connecting portion.

The bit line BL1 is connected to the word lines WL1 to WL
4 are formed by the first metal wiring layer M-1; however, at the positions crossing the word lines WL5 to WL8, they are formed by the second metal wiring layer M-2. At this time, the bit line BL1 is coupled to the first polysilicon layer Poly-1 at the bit line coupling portion, and the formation position is shifted by two pitches by being bent by the first polysilicon layer Poly-1. . The coupling between the first metal wiring layer M-1 and the second metal wiring layer M-2 and the first polysilicon layer Poly-1 is performed through a through hole.

The bit line BL1B is connected to the second metal wiring layer M-
2 and the formation position is shifted by one pitch in the bit line coupling part due to the bit line cross.

The bit line BL2 is connected to the first metal wiring layer M-1.
And the formation position is shifted by one pitch in the bit line coupling part due to the bit line cross. The size of the bit line coupling portion in the bit line extending direction is 9F.

Also in such a configuration, each time the word line WL intersects between adjacent bit lines, the memory cell M
Since Cs are alternately arranged with a shift of one pitch, the load on the bit lines can be equalized as in the case of FIG. In addition, bit line crossing is performed between the bit lines BL1, BL1B, and BL2, and adjacent bit lines are changed, so that noise between bit lines can be reduced.

FIG. 15 shows the memory cell array 200
A, another example of an array configuration of 4F ² -2 intersection cells applied to 200B is shown.

The configuration shown in FIG. 15 is significantly different from that shown in FIG. 1 in the way the bit lines are crossed.

In the configuration shown in FIG. 15, bit line BL
For 1, the formation layers are exchanged, and the bit line BL
A bit line cross is performed between the bit lines 1B, BL2, and BL2B.

The bit line BL1 is connected to the word lines WL1 to WL
4 are formed by the first metal wiring layer M-1; however, at the positions crossing the word lines WL5 to WL8, they are formed by the second metal wiring layer M-2. The bit line BL1 is connected to the first
A bit line formed of the metal wiring layer M-1 and a second metal wiring layer M;
-2 is connected to the bit line by a contact hole. The bit line BL1B is formed of the second metal wiring layer M-2, and its formation position is shifted by one pitch in the bit line coupling portion due to the bit line cross. The bit line BL2 is formed by the first metal wiring layer M-1, and its formation position is shifted by one pitch in the bit line coupling portion due to the bit line cross. The bit line BL2B is formed by the second metal wiring layer M-2, and its formation position is shifted by two pitches in the bit line coupling portion due to the bit line cross. At this time, in order to avoid contact with the adjacent bit line, the first polysilicon layer Poly-1 is used in the bit line coupling portion. Second metal wiring layer M-2
And the first polysilicon layer Poly-1 are connected via through holes.

In such a configuration, each time the word line WL intersects between adjacent bit lines, the memory cell M
Since Cs are alternately arranged with a shift of one pitch, the load on the bit lines can be equalized as in the case of FIG. Also, bit lines BL1B, BL2, BL2B
The bit line crossing is performed between the two and the adjacent bit line is changed, so that noise between bit lines can be reduced.

[0121] Also in the case of 4F 2 ^-2 intersection cell, as in the case of the 4F 2 ^-1 intersection cell, the word line, so as to surround the individual bit lines by causing enter between adjacent bit lines Can be formed. The cross-sectional configuration in this case is shown in FIGS. 20 (B) and 21 (B). The cross sections shown in FIGS. 20 (B) and 21 (B) correspond to FIGS. 20 (A) and 21 (B), respectively. FIG.
(B) and FIG. 21 (B), the two-layered bit line
This is realized by the first polysilicon layer and the second metal wiring. Although not particularly limited, FIGS. 20B and 21B
The lower bit line BL1 is formed by the first polysilicon layer laminated on the barrier layer BR2 forming the PLED transistor, and the first metal wiring layer M1
When the upper bit line BL1B is formed by the second metal wiring layer M2 formed in the upper layer,
The word line WL formed by the polysilicon layer (poly-Si) is formed to enter. With such a structure, the word line WL exerts a shielding function between the adjacent bit lines BL, so that crosstalk noise between the adjacent bit lines can be reduced.

Even when the configuration shown in FIGS. 20B and 21B is adopted, bit line crossing is possible. Although not particularly limited, as shown in FIG. 22A, a lower bit line BL1 formed by a polysilicon layer (poly-Si) and an upper bit line BL1B formed by a second metal wiring layer (M2). Means through hole (M2 to poly) at the bit line coupling part
22 and a case where the connection is made via the first metal wiring layer (M1) as shown in FIG. 22 (B). This enables bit line crossing.

According to the above example, the following functions and effects can be obtained.

(1) When the word line WL is connected to the adjacent bit line BL
Since it functions as a shield between the cells, the crosstalk noise between adjacent bit lines BL can be reduced in the 4F ² -1 intersection cell.

(2) The word line WL is formed of a polysilicon layer (Poly-Si) and has a relatively high resistance. However, by connecting a metal wiring layer to the word line WL, the word line WL is low. Resistance can be achieved. By reducing the resistance of the word line WL, a voltage drop on the word line WL can be suppressed.

(3) The memory cells MC are evenly coupled to both the bit line formed by the first metal wiring layer M-1 and the bit line formed by the second metal wiring layer M-2. Since the memory cells MC are alternately arranged every time the line crosses, the bit line load is equalized, so that the sense amplifier senses a low level and a high level. The conditions can be made uniform, and the difference between the time until the low-level logic is determined and the time until the high-level logic is determined can be reduced.

(4) According to bit line crossing, each time a bit line is crossed, an adjacent bit line can be changed, thereby reducing crosstalk noise between bit lines.

(5) As shown in FIG. 1, FIG. 11, FIG. 13, FIG. 14, and FIG. 15, at the bit line coupling portion, the second metal wiring layer is connected to the polysilicon through a through hole (M2 to Poly). By bonding with the layers (Fig. 1
9 (B) and FIG. 22 (A)), the size of the bit line coupling portion in the bit line extension direction can be reduced as compared with the configuration without such coupling (FIG. 12). Thus, the area of the memory cell array can be reduced.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

In the above description, the invention made mainly by the present inventor has been described in the SDR which
Although the case where the present invention is applied to AM has been described, the present invention is not limited to this, and can be widely applied to various semiconductor memory devices.

The present invention provides at least a plurality of word lines,
The present invention can be applied on condition that it includes a plurality of bit lines arranged to cross the plurality of word lines and a plurality of memory cells coupled to the word lines and the bit lines.

[0132]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a capacitor formed including a recess in a substrate of a semiconductor device and a polysilicon layer provided in the recess, and a vertical structure having a channel made of an intrinsic semiconductor and laminated on the polysilicon layer. memory cell of 4F ² by are able to form, in this case, the word line, enters between adjacent bit lines, by surrounding the individual bit lines, the shielding function between adjacent bit lines Therefore, crosstalk noise between adjacent bit lines can be reduced. Then, a metal wiring layer is stacked corresponding to the word line, and the word line and the corresponding metal wiring layer are electrically coupled to each other to reduce the resistance of the word line. The word rise time can be shortened.

Further, when the adjacent bit lines are formed in different layers from each other and attention is paid to the adjacent bit lines, the memory cells are alternately arranged each time the bit lines intersect the word lines. To make the load even,
The load imbalance seen from the sense amplifier can be easily eliminated. At this time, by exchanging adjacent bit lines with a bit line cross, it is possible to reduce crosstalk noise between bit lines.

Further, when the word line is formed by the first semiconductor layer and the bit line is formed by the second semiconductor layer different from the first semiconductor layer, the first metal wiring corresponds to the word line. By stacking layers and electrically connecting the word line and the corresponding first metal wiring layer, the resistance of the word line can be reduced, thereby shortening the word rise time. Can be planned.

[Brief description of the drawings]

FIG. 1 is an example of a semiconductor memory device according to the present invention;
FIG. 2 is a plan view of a main part of a memory cell array in a DRAM.

2 is an arrangement example illustration of ^8F 2 -2 intersection cell.

FIG. 3 is an explanatory diagram of an example of the arrangement of 4F ² -1 intersection cells.

4 is an arrangement example illustration of ^4F 2 -2 intersection cell.

FIG. 5 is a circuit diagram illustrating a configuration example of a sense amplifier corresponding to the memory cell;

FIG. 6 is a diagram illustrating the relationship between a bit line cross and noise reduction.

FIG. 7 is an explanatory diagram showing a relationship between a bit line cross and noise reduction.

8 is a main part plan view of a memory cell array including a 4F 2 ^-1 intersection cell.

9 is a main part plan view of a memory cell array including a 4F 2 ^-2 intersection cell.

10 is a main part plan view of a memory cell array including a 4F 2 ^-2 intersection cell.

11 is a main part plan view of a memory cell array including a 4F 2 ^-2 intersection cell.

12 is a main part plan view of a memory cell array including a 4F 2 ^-2 intersection cell.

13 is a main part plan view of a memory cell array including a 4F 2 ^-2 intersection cell.

14 is a main part plan view of a memory cell array including a 4F 2 ^-2 intersection cell.

15 is a main part plan view of a memory cell array including a 4F 2 ^-2 intersection cell.

FIG. 16 is a sectional view of a main part in the memory cell array.

FIG. 17 is a sectional view of a main part in the memory cell array.

FIG. 18 is a sectional view of a main part in the memory cell array.

FIG. 19 is a sectional view of a main part of a bit line coupling part in the memory cell array.

FIG. 20 is a cross-sectional view showing another configuration example of a main part in the memory cell array.

FIG. 21 is a cross-sectional view showing another configuration example of a main part in the memory cell array.

FIG. 22 is a sectional view of another main part of a bit line coupling part in the memory cell array.

FIG. 23 is a block diagram illustrating an overall configuration example of the SDRAM.

[Explanation of symbols]

 32 SDRAM 200A, 200B Memory cell array MC Memory cell BL Bit line WL Word line PL Semiconductor substrate BR1 First barrier film BR2 Second barrier film CH Channel made of intrinsic semiconductor M1 First metal wiring layer M2 Second metal wiring layer Poly-1 First 1 polysilicon layer Poly-2 second polysilicon layer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazuo Nakazato 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo F-term in Central Research Laboratory, Hitachi, Ltd. 5F083 AD17 LA13 LA15 5M024 AA22 AA41 AA70 BB02 BB12 BB13 BB35 BB36 CC20 CC50 CC52 EE05 EE29 JJ02 LL01 LL05 LL11 LL13 LL14 MM13 PP01 PP03 PP04 PP05 PP10

Claims (5)

[Claims] A semiconductor including a plurality of word lines, a plurality of bit lines arranged to intersect the plurality of word lines, and a plurality of memory cells coupled to the word lines and the bit lines; A memory device, wherein the memory cell has a minimum processing dimension of a semiconductor device of F
A capacitor comprising a recess provided in a semiconductor substrate and a semiconductor layer formed in the recess, and a transistor stacked on the semiconductor layer and having a channel of an intrinsic semiconductor and having a vertical structure. including the door, it is one formed in a region of 4F ^2, the word line, the semiconductor memory device characterized by being formed so as to surround the individual bit lines by entering between adjacent bit lines. 2. The semiconductor memory device according to claim 1, wherein a metal wiring layer is laminated corresponding to said word line, and said word line and said metal wiring layer corresponding thereto are electrically coupled. 3. A semiconductor including a plurality of word lines, a plurality of bit lines arranged to cross the plurality of word lines, and a plurality of memory cells coupled to the word lines and the bit lines. A memory device, wherein the memory cell has a minimum processing dimension of a semiconductor device of F
When shown by, a capacitor formed including a concave portion provided in the semiconductor substrate and a semiconductor layer provided in the concave portion, and a vertical structure having a channel of an intrinsic semiconductor stacked on the semiconductor layer. Including the transistor
Is one formed in a region of 4F ^2, are formed in different neighboring bit lines from one another layer, each time the adjacent bit lines crossing the word lines, the memory cells are alternately arranged between the adjacent bit lines A semiconductor device, comprising: 4. The semiconductor memory device according to claim 3, wherein adjacent bit lines are replaced by a bit line cross. 5. The first metal wiring corresponding to the word line when the word line is formed by a first semiconductor layer and the bit line is formed by a second semiconductor layer different from the first semiconductor layer. The layers are stacked, and the word line and the corresponding first metal wiring layer are electrically coupled to each other. The second metal wiring layer different from the first metal wiring layer, and the second semiconductor layer 5. The semiconductor memory device according to claim 3, wherein said bit line is formed as a multilayer.