JP2014139995A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an occupied area of a bit line equalization circuit while maintaining precharge characteristics.SOLUTION: A semiconductor device comprises equalization circuits EQ which include: diffusion layer regions SDT1, SDB1 in which contact conductors CE1, CE2 for connection with bit lines BLT1, BLB1, respectively are installed; a diffusion layer region SDEQ which extends in an X direction and to which precharge potential is supplied; and linear gate electrodes G for connecting the diffusion regions each provided at a boundary between every diffusion region. The diffusion layer regions SDT1, SDB1 are isolated from each other.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an equalize circuit that equalizes a pair of bit lines to the same potential.

  A DRAM (Dynamic Random Access Memory) which is a typical semiconductor device reads data by amplifying a potential difference generated between a pair of bit lines by a sense amplifier. In order to perform amplification by the sense amplifier, it is necessary to equalize a pair of bit lines to the same potential in advance, so that each bit line pair is provided with an equalize circuit.

  Usually, the equalizing circuit is composed of three transistors. Among these, the first transistor is connected between one bit line and the precharge wiring, the second transistor is connected between the other bit line and the precharge wiring, and the third transistor is a pair of Connected between bit lines. As a method for efficiently arranging these three transistors in a limited space, a layout described in Patent Document 1 is known.

JP 2008-171928 A

  The layout described in Patent Document 1 has a structure in which the periphery of a diffusion layer to which a precharge wiring is connected is surrounded by a ring-shaped gate electrode. For this reason, if the ring size of the gate electrode is too small, contact with the diffusion layer cannot be performed correctly. Therefore, the ring size of the gate electrode needs to be a predetermined size or more. As a result, the straight portion of the gate electrode, that is, the width of the gate electrode of the third transistor is narrowed, and a sufficient on-current cannot be obtained.

  The semiconductor device according to the present invention is positioned in the first direction when viewed from the first diffusion layer region and the first diffusion layer region to which the first bit line is connected, and is connected to the second bit line. A second diffusion layer region and a third diffusion layer which is located in a second direction intersecting the first direction when viewed from the first and second diffusion layer regions and to which a first potential is supplied A gate electrode having a region, a first portion, a second portion, and a third portion sandwiched in the first direction by the first and second portions, and first to third of the gate electrode A plurality of channel regions including first to third channel regions respectively covered with the first to third channel regions. The first diffusion layer region and the third diffusion layer region are connected via the first channel region, and the second diffusion layer region and the third diffusion layer region are connected via the second channel region. The first diffusion layer region and the second diffusion layer region are connected via the first to third channel regions.

  According to the present invention, it is easy to reduce the size of the equalizing circuit by reducing the size of the diffusion region in which the bit line contact is disposed.

It is a block diagram which shows the whole structure of a semiconductor device. It is a schematic plan view showing a part of the memory cell array in an enlarged manner. 2 is a schematic plan view showing a part of the memory cell array 11 in an enlarged manner. It is a circuit diagram of a sense amplifier and an equalize circuit. It is a schematic plan view for explaining the layout of each functional block included in the sense amplifier region. It is a schematic plan view showing a layout of an equalize circuit. It is an equivalent circuit diagram of an equalize circuit. It is a figure for demonstrating the relationship between the diffusion layer area | regions SDT1 and SDEQ which comprise the transistor Tr2, (a) shows the case where the precharge operation is performed after the bit line BLT1 is driven to the high level (VRAY), (B) shows the case where the precharge operation is performed after the bit line BLT1 is driven to the low level (VSS). FIG. 5 is a diagram for explaining the relationship between diffusion layer regions SDT1 and SDB1 constituting a transistor Tr1, and (a) after the bit line BLT1 is driven to a high level (VRAY) and the bit line BLB1 is driven to a low level (VSS). A case where the precharge operation is performed is shown, and (b) shows a case where the precharge operation is performed after the bit line BLT1 is driven to the low level (VSS) and the bit line BLB1 is driven to the high level (VARY).

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing the overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is a DRAM integrated on a single semiconductor chip, and has a memory cell array 11. The memory cell array 11 includes a plurality of sub word lines SWL and a plurality of bit lines BL, and has a configuration in which memory cells MC are arranged at intersections thereof. Selection of the sub word line SWL is performed by the row decoder 12, and selection of the bit line BL is performed by the column decoder 13.

  As shown in FIG. 1, the semiconductor device 10 is provided with an address terminal 21, a command terminal 22, a clock terminal 23, a data terminal 24, and a power supply terminal 25 as external terminals.

  The address terminal 21 is a terminal to which an address signal ADD is input from the outside. The address signal ADD input to the address terminal 21 is supplied to the address latch circuit 32 via the address input circuit 31 and is latched by the address latch circuit 32. The address signal ADD latched by the address latch circuit 32 is supplied to the row decoder 12, the column decoder 13, or the mode register 14. The mode register 14 is a circuit in which a parameter indicating the operation mode of the semiconductor device 10 is set.

  The command terminal 22 is a terminal to which a command signal CMD is input from the outside. The command signal CMD includes a plurality of signals such as a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE. Here, a slash (/) at the head of the signal name means that the corresponding signal is an inverted signal or that the signal is a low active signal. The command signal CMD input to the command terminal 22 is supplied to the command decoding circuit 34 via the command input circuit 33. The command decode circuit 34 is a circuit that generates various internal commands by decoding the command signal CMD. The internal commands include an active signal IACT, a column signal ICOL, a refresh signal IREF, a mode register set signal MRS, and the like.

  The active signal IACT is a signal that is activated when the command signal CMD indicates row access (active command). When the active signal IACT is activated, the address signal ADD latched by the address latch circuit 32 is supplied to the row decoder 12. Thereby, the sub word line SWL designated by the address signal ADD is selected.

  The column signal ICOL is a signal that is activated when the command signal CMD indicates column access (read command or write command). When the internal column signal ICOL is activated, the address signal ADD latched by the address latch circuit 32 is supplied to the column decoder 13. As a result, the bit line BL specified by the address signal ADD is selected.

  Therefore, when an active command and a read command are input in this order, and a row address and a column address are input in synchronization therewith, read data is read from the memory cell MC specified by these row address and column address. The read data DQ is output to the outside from the data terminal 24 via the FIFO circuit 15 and the input / output circuit 16. On the other hand, when an active command and a write command are input in this order, a row address and a column address are input in synchronization with them, and then write data DQ is input to the data terminal 24, the write data DQ is input to the input / output circuit 16 The data is supplied to the memory cell array 11 via the FIFO circuit 15 and written to the memory cell MC specified by the row address and the column address. The operations of the FIFO circuit 15 and the input / output circuit 16 are performed in synchronization with the internal clock signal LCLK. The internal clock signal LCLK is generated by the DLL circuit 100.

  The refresh signal IREF is a signal that is activated when the command signal CMD indicates a refresh command. When the refresh signal IREF is activated, row access is performed by the refresh control circuit 35, and a predetermined sub word line SWL is selected. As a result, the plurality of memory cells MC connected to the selected sub word line SWL are refreshed. Selection of the sub word line SWL is performed by a refresh counter (not shown) included in the refresh control circuit 35.

  The mode register set signal MRS is a signal that is activated when the command signal CMD indicates a mode register set command. Therefore, if a mode register set command is input and a mode signal is input from the address terminal 21 in synchronization therewith, the set value of the mode register 14 can be rewritten.

  The clock terminal 23 is a terminal to which external clock signals CK and / CK are input. The external clock signal CK and the external clock signal / CK are complementary signals, and both are supplied to the clock input circuit 36. The clock input circuit 36 generates an internal clock signal ICLK based on the external clock signals CK and / CK. The internal clock signal ICLK is supplied to the timing generator 37, whereby various internal clock signals are generated. Various internal clock signals generated by the timing generator 37 are supplied to circuit blocks such as the address latch circuit 32 and the command decode circuit 34, and define the operation timing of these circuit blocks.

  The internal clock signal ICLK is also supplied to the DLL circuit 100. The DLL circuit 100 is a clock generation circuit that generates an internal clock signal LCLK that is phase-controlled based on the internal clock signal ICLK. As described above, the internal clock signal LCLK is supplied to the FIFO circuit 15 and the input / output circuit 16. As a result, the read data DQ is output in synchronization with the internal clock signal LCLK.

  The power supply terminal 25 is a terminal to which power supply potentials VDD and VSS are supplied. The power supply potentials VDD and VSS supplied to the power supply terminal 25 are supplied to the internal power supply generation circuit 38. The internal power supply generation circuit 38 generates various internal potentials VPP, VARY, VBLP, VPERI and the like based on the power supply potentials VDD and VSS. The internal potential VPP is a potential mainly used in the row decoder 12, the internal potentials VARY and VBLP are mainly potentials used in the memory cell array 11, and the internal potential VPERI is used in many other circuit blocks. Potential.

  FIG. 2 is a schematic plan view showing a part of the memory cell array 11 in an enlarged manner.

  As shown in FIG. 2, the memory cell array 11 has a number of memory mats MAT arranged in a matrix. The memory mat is a range in which the sub word line SWL and the bit line BL extend. A sub word driver area SW is provided between two memory mats MAT adjacent in the X direction. On the other hand, a sense amplifier area SAA is provided between two memory mats MAT adjacent in the Y direction.

  A subword cross region SX is provided in a region where a column of subword driver regions SW extending in the Y direction intersects with a column of sense amplifier regions SAA extending in the X direction. A sub-amplifier or the like is arranged in the sub-word cross region SX.

  FIG. 3 is a schematic plan view showing a part of the memory cell array 11 further enlarged.

  As shown in FIG. 3, local I / O lines LIOT and LIOB extending in the X direction and main I / O lines MIOT and MIOB extending in the Y direction are provided in the memory cell array 11. Local I / O lines LIOT and LIOB and main I / O lines MIOT and MIOB are hierarchically constructed I / O lines.

  Local I / O lines LIOT and LIOB are used to transmit read data read from the memory cell MC in the memory cell array. The local I / O lines LIOT and LIOB are differential I / O lines that transmit read data using a pair of wirings. The local I / O lines LIOT and LIOB are laid out in the X direction on the sense amplifier area SAA and the subword cross area SX.

  Main I / O lines MIOT and MIOB are used to transmit read data from the memory cell array 11 to the main amplifier AMP shown in FIG. The main I / O lines MIOT and MIOB are also differential I / O lines that transmit read data using a pair of wirings. Main I / O lines MIOT and MIOB are laid out in the Y direction on memory mat MAT and sense amplifier area SAA. A number of main I / O lines MIOT and MIOB extending in the Y direction are provided in parallel and connected to the main amplifier AMP.

  In the memory mat MAT, memory cells MC are arranged at the intersections of the sub word lines SWL and the bit lines BLT or BLB. The memory cell MC has a configuration in which a cell transistor Tr and a cell capacitor C are connected in series between a corresponding bit line BLT or BLB and a plate wiring (for example, a ground wiring). The cell transistor Tr is composed of an N-channel MOS transistor, and its gate electrode is connected to the corresponding sub word line SWL.

  A large number of sub word drivers SWD are provided in the sub word driver area SW. Each sub word driver SWD drives the corresponding sub word line SWL based on the row address.

  Further, a main word line MWL and a word driver selection line FXB are connected to the sub word driver SWD. For example, eight word driver selection lines FXB are wired on one sub word driver SWD, and one of the four sub word drivers SWD selected by one main word line MWL is selected by a pair of word driver selection lines FXB. By selecting one, one sub word line SWL is activated.

  In the sense amplifier area SAA, a plurality of units U including a sense amplifier SA, an equalize circuit EQ, and a column switch YSW are provided. Each sense amplifier SA and each equalize circuit EQ is connected to a corresponding bit line pair BLT, BLB. The sense amplifier SA amplifies the potential difference generated in these bit line pairs BLT and BLB, and the equalizing circuit EQ equalizes the bit line pair BLT and BLB to the same potential. The read data amplified by the sense amplifier SA is first transmitted to the local I / O lines LIOT and LIOB, and then further transmitted to the main I / O lines MIOT and MIOB.

  The column switch YSW is provided between the corresponding sense amplifier SA and the local I / O lines LIOT and LIOB, and connects the two when the corresponding column selection line YSL is activated to a high level. One end of the column selection line YSL is connected to the column decoder 13, and the column selection line YSL is activated based on the column address.

  In the sub word cross region SX, a plurality of sub amplifiers SUB are provided. A plurality of subamplifiers SUB are provided for each subword cross region SX, and drive corresponding main I / O lines MIOT and MIOB. The input terminal of each sub-amplifier SUB is connected to the corresponding local I / O line LIOT, LIOB pair, and the output terminal of each sub-amplifier SUB is connected to the corresponding main I / O line MIOT, MIOB. Each sub-amplifier SUB drives main I / O lines MIOT and MIOB based on data on corresponding local I / O lines LIOT and LIOB, respectively.

  As described above, the main I / O lines MIOT and MIOB are provided so as to cross the memory mat MAT. One end of each main I / O line MIOT, MIOB is connected to the main amplifier AMP. Thereby, the data read by the sense amplifier SA is transferred to the sub-amplifier SUB via the local I / O lines LIOT and LIOB, and further sent to the main amplifier AMP via the main I / O lines MIOT and MIOB. The main amplifier AMP further amplifies data supplied via the main I / O lines MIOT and MIOB and transfers the data to the FIFO circuit 15 shown in FIG.

  FIG. 4 is a circuit diagram of the sense amplifier SA and the equalize circuit EQ.

  As shown in FIG. 4, the sense amplifier SA includes p-channel MOS transistors 111 and 112 and n-channel MOS transistors 113 and 114. The transistors 111 and 113 are connected in series between the common source nodes a and b, their contacts are connected to one signal node c, and their gate electrodes are connected to the other signal node d. Similarly, the transistors 112 and 114 are also connected in series between the common source nodes a and b, their contacts are connected to one signal node d, and their gate electrodes are connected to the other signal node c. Yes. The signal node c is connected to the bit line BLT, and the signal node d is connected to the bit line BLB.

  With such a flip-flop structure, when a predetermined active potential is supplied to the high-level common source wiring PCS and the low-level common source wiring NCS, if a potential difference occurs in the bit line pair BLT, BLB, One of the pair is supplied with the potential of the higher-level common source wiring PCS, and the other of the bit line pair is supplied with the potential of the lower-level common source wiring NCS. The active potential of the higher common source line PCS is the array potential VARY, and the active potential of the lower common source line NCS is the ground potential VSS.

  At the time before the sensing operation is performed, the bit line pair BLT, BLB is previously equalized to the precharge potential VBLP by the equalizing circuit EQ. When a predetermined sub word line SWL is selected after the equalization is stopped, the electric charge held in the memory cell MC is released to the bit line BLT or BLB, and as a result, a potential difference is generated between the bit lines BLT and BLB. Thereafter, when an active potential is supplied to the common source lines PCS and NCS, the potential difference between the bit line pair BLT and BLB is amplified.

  The equalize circuit EQ is composed of three n-channel MOS transistors 121-123. The transistor 123 is connected between the bit line pair BLT and BLB, the transistor 121 is connected between the bit line BLT and the power supply line EQL, and the transistor 122 is connected between the bit line BLB and the power supply line EQL. Has been. The power supply line EQL is a line to which the precharge potential VBLP is supplied. A bit line equalize signal BLEQ is supplied to the gate electrodes of these transistors 121-123. With this configuration, when the bit line equalize signal BLEQ is activated to a high level, the bit line pair BLT and BLB is precharged to the precharge potential VBLP.

  FIG. 5 is a schematic plan view for explaining the layout of each functional block included in the sense amplifier area SAA.

  As shown in FIG. 5, in the sense amplifier area SAA, the column switch YSW, the pull-up circuit SAP, the pull-down circuit SAN, the equalizing circuit EQ, and the drive circuit DRV are in the Y direction, that is, in the extending direction of the bit lines BLT and BLB. It is arranged. Here, the pull-up circuit SAP is a circuit portion including the p-channel MOS transistors 111 and 112 shown in FIG. 4, and the pull-down circuit SAN is a circuit including the n-channel MOS transistors 113 and 114 shown in FIG. Part. The drive circuit DRV is a circuit for supplying an active potential (VSS) to the common source line NCS. A circuit for supplying an active potential (VARY) to the common source line PCS is arranged in the sub word cross region SX.

  Among these circuits arranged in the sense amplifier area SAA, the column switch YSW is arranged at both ends in the Y direction, and a pull-up circuit SAP, an equalize circuit EQ, a pull-down circuit SAN, and a drive circuit DRV are arranged in this order. Be placed.

  The circuit portion shown in FIG. 5 is a circuit portion corresponding to 12 pairs of bit lines, that is, 24 bit lines BLT and BLB. Of these, 12 bit lines BLT are assigned to one memory mat MAT, and the remaining 12 bit lines BLB are assigned to the other memory mat MAT. Since the width Wx in the X direction of the circuit portion shown in FIG. 5 is limited by the arrangement pitch of these bit lines BLT and BLB, the length in the Y direction of the sense amplifier area SAA is required to ensure a sufficient transistor size. There is no choice but to increase Wy, but this leads to an increase in chip size. For this reason, it is necessary to devise the layout of the transistors arranged in the sense amplifier area SAA in order to secure a sufficient transistor size while suppressing the length Wy of the sense amplifier area SAA in the Y direction.

  The semiconductor device according to the present embodiment realizes this by improving the layout of the transistors constituting the equalize circuit EQ. Hereinafter, the layout of the transistors constituting the equalize circuit EQ will be described in detail.

  FIG. 6 is a schematic plan view showing a layout of equalize circuit EQ, and corresponds to an enlarged view of region A shown in FIG.

  FIG. 6 shows a layout of two equalize circuits EQ1 and EQ2 corresponding to two pairs of bit lines BL1 and BL2 (first and second bit line pairs), respectively. A region surrounded by the element isolation region STI is an active region. Of the active region, the portion covered with the gate electrode G is the channel region of the n-channel MOS transistor, and the portion not covered with the gate electrode G is the source region or drain region (diffusion layer region) of the n-channel MOS transistor. ). Since the functions of the source region and the drain region are reversed depending on the direction of current flow, these are collectively referred to simply as a “diffusion layer region”. A bit line equalize signal BLEQ is supplied to the gate electrode G.

  As shown in FIG. 6, each equalize circuit EQ1, EQ2 is formed of three diffusion layer regions. Among these, the diffusion layer region SDT1 (first diffusion layer region) and the diffusion layer region SDT2 (fourth diffusion layer region) are connected to the bit lines BLT1 and BLT2 via the contact conductor CE1, respectively. Diffusion layer region SDB1 (second diffusion layer region) and diffusion layer region SDB2 (fifth diffusion layer region) are connected to bit lines BLB1 and BLB2 through contact conductor CE2, respectively. Further, the diffusion layer region SDEQ (third diffusion layer region) is connected to the power supply line EQL via a plurality of contact conductors CE3. Diffusion layer region SDEQ is common to equalize circuits EQ1 and EQ2. The gate electrode G is also common to the equalize circuits EQ1 and EQ2.

  In the present embodiment, the diffusion layer region SDEQ has a linear shape extending in the X direction (first direction), and the diffusion layer regions SDTi (i = 1, 2) and SDBi (i = 1, 4) are They are arranged alternately in the X direction. Further, the diffusion layer regions SDTi (i = 1, 2) and SDBi (i = 1, 4) both have a linear shape extending in the Y direction (second direction). The extending direction of the bit lines BLT and BLB is also the Y direction.

  The diffusion layer region SDT and the diffusion layer region SDB are separated from each other by the element isolation region STI. The gate electrode G extending in the X direction is formed at the boundary between the plurality of diffusion layer regions SDT, SBT and the diffusion layer region SDEQ. Hereinafter, in the gate electrode G, a channel region interposed between the diffusion layer region SDT1 and the diffusion layer region SDEQ is a first region 102, and a channel region interposed between the diffusion layer region SDB1 and the diffusion layer region SDEQ is a second region. 104, a channel region interposed between the first region 102 and the second region 104 is referred to as a third region 106.

  Here, paying attention to the equalize circuit EQ1, a channel CH1 (first channel) is formed between the diffusion layer region SDT1 and the diffusion layer region SDB1, thereby forming a transistor Tr1. Since the diffusion layer region SDT1 and the diffusion layer region SDB1 are separated by the element isolation region STI, the channel CH1 passes through the third region 106 as well as the first region 102 and the third region 106. Since the element isolation region STI enters the gate electrode G in the third region 106, the third region 106 is formed only in a part thereof immediately below the gate electrode G. The transistor Tr1 corresponds to the transistor 123 illustrated in FIG.

  A channel CH2 (second channel) is formed between the diffusion layer region SDT1 and the diffusion layer region SDEQ via the first region 102, thereby forming a transistor Tr2 (n-channel MOS transistor 121). . Similarly, a channel CH3 (third channel) is formed between the diffusion layer region SDB1 and the diffusion layer region SDEQ via the second region 104, whereby the transistor Tr3 (n-channel MOS transistor 122) is formed. It is formed.

  When the bit line equalize signal BLEQ supplied to the gate electrode G is activated to a high level (second potential), the transistors Tr1 to Tr3 are all turned on, and the bit lines BLT1 and BLB1 are both precharge potential VBLP ( First potential).

  The above is the configuration of the equalize circuit EQ1. The equalizer circuit EQ2 has a configuration similar to that of the equalizer circuit EQ1 described above, but some of the components overlap the equalizer circuit EQ1.

  In equalize circuit EQ2, channel CH4 is formed between diffusion layer region SDT2 and diffusion layer region SDB2, thereby forming transistor Tr4. A channel CH5 is formed between the diffusion layer region SDT2 and the diffusion layer region SDEQ, thereby forming a transistor Tr5. Similarly, a channel CH6 is formed between the diffusion layer region SDB2 and the diffusion layer region SDEQ, thereby forming a transistor Tr6.

  When the bit line equalize signal BLEQ supplied to the gate electrode G is activated to a high level, all the transistors Tr4 to Tr6 are turned on, and in addition to the bit lines BLT1 and BLB1, the bit lines BLT2 and BLB2 are also set to the precharge potential VBLP. Equalized.

  Further, a channel CH7 is also formed between the diffusion layer region SDB1 of the equalizing circuit EQ1 and the diffusion layer region SDT1 of the equalizing circuit EQ2, thereby forming a transistor Tr7. The channel CH7 is also formed via the third region 106, similarly to the channels CH1 and CH4. The transistor Tr7 equalizes the bit line BLB1 and the bit line BLT1.

  In the present embodiment, a contact conductor CE3 for connecting to the power supply line EQL is formed in the region B, and contact conductors CE1 and CE2 for connecting to the bit lines BLT and BLB are formed in the region C. Regions B and C are arranged in the Y direction. Since the contact conductor CE3 does not need to be arranged in the region C and is formed by two columns of the regions B and C, the size of the equalize circuit EQ in the Y direction and the width Wy of the sense amplifier region SAA (see FIG. 5) Shorter. In particular, the small-sized diffusion layer regions SDT1, SDB1, SDT2, and SDB2 are connected to only the long side (X side) of the diffusion layer region SDEQ, and the channels CH1, CH4, and CH7 are all third regions extending in the X direction. By forming via 106, the size of bit line contact diffusion layer regions SDT1, SDB1, SDT2, SDB2 in the Y direction is shortened.

  In addition, since each diffusion layer region and the gate electrode G have simple shapes, there is an advantage that manufacturing is easy even though the size is small.

  Channel CH1 has a longer channel length than channels CH2 and CH3. Therefore, the ability of the transistor Tr1 to equalize the bit lines BLT1 and BLB1 is weaker than the ability of the transistors Tr2 and Tr3 to precharge the bit lines BLT1 and BLB1. However, the bit line BLB1 is not only equalized with the bit line BLT1 via the transistor Tr1, but also equalized with the bit line BLT2 via the transistor Tr7. Thus, the transistor (transistor Tr7) formed between the adjacent equalize circuits EQ assists equalization of the bit line BL. Further, by equalizing the bit line BLB1 with the adjacent bit lines BLT1 and BLT2, variation in the precharge level of each bit line BL can be suppressed.

  FIG. 7 is an equivalent circuit diagram of the equalize circuit EQ.

  As shown in FIG. 7, in the equalize circuit EQ, a transistor Tr7 that connects the bit line BLB1 and the bit line BLT2 (a transistor Tr11 that connects the bit line BLB2 and the bit line BLT3, and a transistor that connects the bit line BLB3 and the bit line BLT4). Tr15) is formed. The transistor Tr7 is a transistor formed in the channel CH7 shown in FIG. 6, and connects the bit line BLB1 and the bit line BLT2. The transistor Tr7 functions to assist the precharge operation, thereby improving the precharge speed and reducing the offset of the precharge potential between the bit lines BLT and BLB.

  That is, the equalize circuit EQ according to the present embodiment has a smaller equalization capability than the precharge capability because the channel lengths of the transistors Tr2 and Tr3 are shorter than the channel length of the transistor Tr1 as shown in FIG. Due to the presence of the transistor Tr7, equalization capability can be assisted.

  Here, it will be described whether each diffusion layer region functions as a source or a drain.

  FIG. 8 is a diagram for explaining the relationship between the diffusion layer regions SDT1 and SDEQ constituting the transistor Tr2. FIG. 8A shows the precharge operation after the bit line BLT1 is driven to the high level (VRAY). (B) shows the case where the precharge operation is performed after the bit line BLT1 is driven to the low level (VSS).

  As shown in FIG. 8A, when the precharge operation is performed after the bit line BLT1 is driven to the high level (VRAY) by the sense amplifier SA, the diffusion layer region SDT1 is at the high level (VRAY). Since SDEQ is an intermediate level (VBLP), the former is the drain (D) and the latter is the source (S). For this reason, the on-current that flows in the channel region CH2 flows from the diffusion layer region SDT1 that is the drain toward the diffusion layer region SDEQ that is the source, as shown by the arrow in FIG.

  Conversely, when the precharge operation is performed after the bit line BLT1 is driven to the low level (VSS) by the sense amplifier SA, the diffusion layer region SDT1 is at the low level (VSS) and the diffusion layer region SDEQ is at the intermediate level (VBLP). Therefore, as shown in FIG. 8B, the former is the source (S) and the latter is the drain (D). For this reason, the on-current that flows in the channel region CH2 flows from the diffusion layer region SDEQ that is the drain toward the diffusion layer region SDT1 that is the source, as shown by the arrow in FIG.

  The same applies to channels CH3, CH5, and CH6.

  FIG. 9 is a diagram for explaining the relationship between the diffusion layer regions SDT1 and SDB1 constituting the transistor Tr3. FIG. 9A shows the bit line BLT1 at the high level (VRAY) and the bit line BLB1 at the low level (VSS). FIG. 6B shows a case where a precharge operation is performed after being driven, and FIG. 5B shows a case where a precharge operation is performed after the bit line BLT1 is driven to a low level (VSS) and the bit line BLB1 is driven to a high level (VARY). Show.

  As shown in FIG. 9A, when the precharge operation is performed after the bit lines BLT1 and BLB1 are driven to the high level (VRAY) and the low level (VSS) by the sense amplifier SA, the diffusion layer region SDT1 is Since the high level (VRAY) and the diffusion layer region SDB1 are at the low level (VSS), the former is the drain (D) and the latter is the source (S). For this reason, the on-current that flows in the channel region CH1 flows from the diffusion layer region SDT1 that is the drain toward the diffusion layer region SDB1 that is the source, as shown by the arrow in FIG.

  On the contrary, when the precharge operation is performed after the bit lines BLT1 and BLB1 are driven to the low level (VSS) and the high level (VARY) by the sense amplifier SA, respectively, the diffusion layer region SDT1 is low level (VSS) Since the layer region SDB1 is at the high level (VARY), the former is the source (S) and the latter is the drain (D) as shown in FIG. 9B. For this reason, the on-current flowing in the channel region CH1 flows from the diffusion layer region SDB1 as the drain toward the diffusion layer region SDT1 as the source, as indicated by an arrow in FIG. 9B.

  The same applies to channels CH4 and CH7. However, since the channel CH7 is a channel region formed between the diffusion layer regions SDB1 and SDT2 belonging to different bit line pairs, there is a case where the channel CH7 has the same potential before precharging. In this case, no current flows through the channel CH7 even if the precharge operation is performed.

  The configuration of the equalize circuit EQ of the semiconductor device 10 has been described above based on the embodiment. As shown in FIG. 6, since both the diffusion layer region and the gate electrode G are simple in shape, they can be easily manufactured even when the size is reduced. In particular, since the channel related to equalization is routed through the third region 106 extending in the X direction like the channel CH1, the Y width of the region C can be easily reduced.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Memory cell array 12 Row decoder 13 Column decoder 14 Mode register 15 FIFO circuit 16 Input / output circuit 21 Address terminal 22 Command terminal 23 Clock terminal 24 Data terminal 25 Power supply terminal 31 Address input circuit 32 Address latch circuit 33 Command input circuit 34 Command decode circuit 35 Refresh control circuit 36 Clock input circuit 37 Timing generator 38 Internal power generation circuit 100 DLL circuit 111, 112 p-channel type MOS transistor 113, 114, 121-123 n-channel type MOS transistor BL bit line SWL sub word line MC memory Cell MAT Memory mat SW Subword driver area SAA Sense amplifier area SX Subword cross area A P Main amplifier SWD Sub-word driver EQ Equalize circuit SA Sense amplifier U unit SUB Sub-amplifier PCS Common source wiring NCS Common source wiring VBLP Precharge potential EQL Power supply wiring BLEQ Bit line equalize signal SAP Pull-up circuit SAN Pull-down circuit DRV Drive circuit STI Element isolation region G Gate electrode SDT, SDB, SDEQ Diffusion layer region CE Contact conductor CH channel

Claims (11)

A first diffusion layer region to which the first bit line is connected;
A second diffusion layer region located in a first direction as viewed from the first diffusion layer region and connected to a second bit line;
A third diffusion layer region that is located in a second direction intersecting with the first direction when viewed from the first and second diffusion layer regions and is supplied with a first potential;
A gate electrode having a first portion, a second portion, and a third portion sandwiched in the first direction by the first and second portions;
A plurality of channel regions including first to third channel regions respectively covered by the first to third portions of the gate electrode,
The first diffusion layer region and the third diffusion layer region are connected via the first channel region,
The second diffusion layer region and the third diffusion layer region are connected via the second channel region,
The semiconductor device, wherein the first diffusion layer region and the second diffusion layer region are connected via the first to third channel regions.   The semiconductor device according to claim 1, wherein an element isolation region is provided between the first diffusion layer region and the second diffusion layer region. A fourth diffusion layer region located in the first direction as viewed from the second diffusion layer region and connected to a third bit line;
A fifth diffusion layer region located in the first direction as viewed from the third diffusion layer region and connected to a fourth bit line; and
The gate electrode includes a fourth portion, a fifth portion, a sixth portion sandwiched in the first direction by the fourth and fifth portions, and the second and fourth portions. And a seventh portion sandwiched in the first direction,
The plurality of channel regions further include fourth to seventh channel regions covered with the fourth to seventh portions of the gate electrode, respectively.
The fourth diffusion layer region and the third diffusion layer region are connected via the fourth channel region,
The fifth diffusion layer region and the third diffusion layer region are connected via the fifth channel region,
The fourth diffusion layer region and the fifth diffusion layer region are connected via the fourth to sixth channel regions,
3. The semiconductor device according to claim 1, wherein the second diffusion layer region and the fourth diffusion layer region are connected via the second, fourth, and seventh channel regions. .   The semiconductor device according to claim 1, wherein the gate electrode is a linear electrode extending in the first direction.   The first channel formed from the first diffusion layer region to the second diffusion layer region is the second channel formed from the first diffusion layer region to the third diffusion layer region. 5. The semiconductor device according to claim 1, wherein the semiconductor device is longer than any one of the third channels formed from the second diffusion layer region to the third diffusion layer region. 6. .   When the second potential is supplied to the gate electrode, the first and second bit lines are precharged to the first potential by connecting the second and third channels, and 6. The semiconductor device according to claim 5, wherein potentials of the first and second bit lines are equalized by connecting the first channel.   The semiconductor device according to claim 1, wherein the first and second bit lines extend in a second direction substantially orthogonal to the first direction.   The first and second diffusion layer regions are arranged in the first direction and have a shape extending in a second direction substantially orthogonal to the first direction. 8. A semiconductor device according to any one of 7 to 7.   When the second potential is supplied to the gate electrode, the third bit line is precharged to the first potential by connecting the fourth diffusion layer region and the third diffusion layer region. The fourth bit line is also precharged to the first potential by connecting the fifth diffusion layer region and the third diffusion layer region, and the fourth diffusion layer region 4. The semiconductor device according to claim 3, wherein the potentials of the third and fourth bit lines are equalized by connecting the fifth diffusion layer region.   When the second potential is supplied to the gate electrode, the potentials of the second and third bit lines are equalized by connecting the second diffusion layer region and the fourth diffusion layer region. The semiconductor device according to claim 9. A bit line pair in which one is driven to a first potential by a sense amplifier and the other is driven to a second potential different from the first potential;
A first transistor electrically connecting the one and the other of the bit line pair;
A second transistor for electrically connecting the one of the bit line pair and a node to which a predetermined potential is supplied;
A semiconductor device having a third transistor that electrically connects the other of the bit line pair and the node;
A first diffusion region connected to the one of the bit line pairs;
A second diffusion region connected to the other of the bit line pair;
A third diffusion region connected to the node;
A gate electrode for commonly performing electrical connection of the first to third transistors;
The first and second diffusion regions are arranged in the same area among the areas defined by the gate electrode, and the third diffusion region is the first and second diffusion areas defined by the gate electrode. A semiconductor device, wherein the semiconductor device is arranged in an area different from an area in which the second diffusion region is arranged.

Images