JP2016015185A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an improved sub-word driver.SOLUTION: A semiconductor device comprises: a main word line MWB; a sub-word line SWL; a word driver selection line FXT; first and second power supply wiring supplying potentials VKK1, VKK2, respectively; a first conductivity type transistor P1 connected between the word driver selection line FXT and the sub-word line SWL, and including a control electrode connected to the main word line MWB; a second conductivity type transistor N1 connected between the sub-word line SWL and the first power supply wiring; and a first conductivity type transistor P2 connected between the main word line MWB and the control electrode of the transistor N1, and including a control electrode connected to the second power supply wiring. The occupied area of a sub-word driver SWD can be reduced and off-leak current can also be reduced.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which word lines are hierarchized into a main word line and a sub word line.

  As described in Patent Documents 1 and 2, a semiconductor device such as a DRAM (Dynamic Random Access Memory) generally has a configuration in which word lines are hierarchized into main word lines and sub word lines.

  In the semiconductor devices described in Patent Documents 1 and 2, the selection level of the sub word line is a VPP level that is a boosted potential, and the non-selection level of the sub word line is a VKK level that is a negative potential. When the sub word line becomes the VPP level, the cell transistor connected to the sub word line is turned on. On the other hand, when the sub word line becomes VKK level, the cell transistors connected to the sub word line are turned off.

JP 2005-135461 A JP 2008-1335099 A

  Since many sub word drivers for driving the sub word lines are provided in the memory cell array, it is desirable that the occupied area is as small as possible. In addition, reduction of off-leakage current is also required.

  A semiconductor device according to an aspect of the present invention includes a main word line, a sub-word line, a word driver selection line, first and second power supply lines for supplying first and second potentials, respectively, and the word driver selection. And a control electrode connected between the first word line of the first conductivity type connected to the main word line, and between the sub word line and the first power line. The second conductivity type second transistor is connected between the main word line and the control electrode of the second transistor, and the control electrode is connected to the second power supply wiring. And a third transistor.

  According to another aspect of the present invention, a semiconductor device drives a main word line to an active level or an inactive level based on an address signal, and activates or deactivates a word driver select line based on the address signal A word selection driver for driving to a level; and a sub word driver for driving a sub word line connected to the main word line and the word driver selection line, wherein the sub word driver includes the main word line and the word driver selection line. Are driven to the active level in response to the active level, and the sub word line is set to the first inactive level in response to the main word line being at the inactive level. Driven, the main word line is at the active level, and the word And drives the different second inactive level and the sub-word lines in response said first inactive level to driver selection line is in the inactive level.

  A semiconductor device according to still another aspect of the present invention includes a plurality of main word lines including a first main word line, a plurality of word driver selection lines including first and second word driver selection lines, A plurality of sub word lines including a second sub word line; a plurality of sub word drivers including first and second sub word drivers; first and second power supply lines for supplying first and second potentials, respectively; The plurality of sub word drivers are connected between a corresponding one of the plurality of word driver selection lines and a corresponding one of the plurality of sub word lines, and a control electrode is connected to the corresponding main word line. The first conductivity type first transistor is connected between the corresponding sub-word line and the first power supply line, and the control electrode is connected to the corresponding main word line. A second transistor of a second conductivity type connected to each other, wherein the first sub-word driver is connected to the first main word line and the first word driver selection line to be connected to the first transistor. The second sub-word driver is connected to the first main word line and the second word driver selection line to drive the second sub-word line, and further, the plurality of main word lines are driven. A third transistor of the first conductivity type connected between a corresponding word line and the control electrode of the second transistor, the control electrode being connected to the second power supply wiring; Features.

  According to the present invention, the area occupied by the sub word driver can be reduced, and the off-leak current can be reduced.

1 is a block diagram showing an overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention. 3 is a block diagram showing a configuration of a row decoder 12. FIG. 2 is a schematic plan view showing a structure of a memory cell array 11. FIG. 2 is a schematic plan view showing a part of the memory cell array 11 in an enlarged manner. FIG. FIG. 3 is a circuit diagram showing a configuration of a sub word driver SWD according to the first embodiment. It is a wave form diagram for demonstrating the operation | movement of subword driver SWD, (a) shows the operation | movement when activated, (b)-(d) has shown the operation | movement when deactivated. It is a circuit diagram which shows the structure of subword driver SWD by 2nd Embodiment. It is a circuit diagram which shows the structure of subword driver SWD by 3rd Embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing the overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is a DRAM and includes a memory cell array 11 as shown in FIG. The memory cell array 11 is provided with a plurality of sub-word lines SWL and a plurality of bit lines BL that intersect with each other, and memory cells MC are arranged at the intersections thereof. Selection of the sub word line SWL is performed by the row decoder 12, and selection of the bit line BL is performed by the column decoder 13. The bit line BL is connected to the sense amplifier SA in the memory cell array 11, and the bit line BL selected by the column decoder 13 is connected to the main amplifier 14 via the sense amplifier SA.

  The operations of the row decoder 12, the column decoder 13 and the main amplifier 14 are controlled by the access control circuit 20. The access control circuit 20 is supplied with an address signal ADD through an address terminal 21 and a command signal CMD through a command terminal 22. The access control circuit 20 controls operations of the row decoder 12, the column decoder 13, the main amplifier 14, and the data input / output circuit 30 based on the address signal ADD and the command signal CMD.

  Specifically, when the command signal CMD indicates an active command, the address signal ADD is supplied to the row decoder 12. In response to this, the row decoder 12 selects the sub word line SWL indicated by the address signal ADD, whereby the corresponding memory cell MC is connected to the bit line BL.

  On the other hand, when the command signal CMD indicates a read command or a write command, the address signal ADD is supplied to the column decoder 13. In response to this, the column decoder 13 connects the bit line BL indicated by the address signal ADD to the main amplifier 14. Thereby, during the read operation, the read data DQ read from the memory cell array 11 via the sense amplifier SA is output from the data terminal 31 to the outside via the main amplifier 14 and the data input / output circuit 30. In the write operation, write data DQ supplied from the outside via the data terminal 31 and the data input / output circuit 30 is written into the memory cell MC via the main amplifier 14 and the sense amplifier SA.

Each of these circuit blocks uses a predetermined internal voltage as an operating power supply. These internal power supplies are generated by the power supply circuit 40 shown in FIG. The power supply circuit 40 receives the external potential VDD and the ground potential VSS supplied via the power supply terminals 41 and 42, and generates the internal potentials VPP, VKK1, VKK2, VKK3, VPERI, VARY, and the like based on these. The internal potential VPP is generated by boosting the external potential VDD, and the internal potentials VPERI and VARY are positive potentials generated by decreasing the external potential VDD. On the other hand, the internal potentials VKK1, VKK2, and VKK3 are all negative potentials, and their levels are
VSS>VKK1>VKK2> VKK3
It is. As an example,
VKK1 = -0.2V
VKK2 = -0.3V
VKK3 = -1.0V
It is.

  Internal potentials VPP, VKK1, VKK2, and VKK3 are potentials mainly used in the memory cell array 11 and the row decoder 12. The configurations of the memory cell array 11 and the row decoder 12 will be described later. The internal potential VARY is a potential mainly used in the sense amplifier SA. When the sense amplifier SA is activated, the read data read out is amplified by driving one of the bit line pairs to the VARY level and the other to the VSS level. The internal potential VPERI is used as an operating potential for most peripheral circuits such as the access control circuit 20. By using the internal potential VPERI, which is lower than the external potential VDD, as the operating potential of these peripheral circuits, the power consumption of the semiconductor device 10 is reduced.

  FIG. 2 is a block diagram showing a configuration of the row decoder 12.

  As shown in FIG. 2, the row decoder 12 includes a predecoder 50 that predecodes an address signal ADD, a main word driver 51 that drives a main word line MWB based on an output signal PD1 from the predecoder 50, and a predecoder. And a word selection driver 52 for driving the word driver selection line FXT based on the output signal PD2 from the output signal PD2. The predecoder 50 generates the output signal PD1 by decoding the first part of the address signal ADD, and generates the output signal PD2 by decoding the second part of the address signal ADD. Some bits may overlap in the first part and the second part of the address signal ADD.

  The main word driver 51 receives the output signal PD1 from the predecoder 50, and sets one or more main word lines MWB selected from the plurality of main word lines MWB to the active level based on the output signal PD1. Other main word lines MWB are set to an inactive level. In the present embodiment, the active level of the main word line MWB is VKK3, and the inactive level is VPP.

  The word selection driver 52 receives the output signal PD2 from the predecoder 50, and based on this, sets one or more word driver selection lines FXT selected from the plurality of word driver selection lines FXT to an active level. Other word driver selection lines FXT are set to an inactive level. In the present embodiment, the activation level of the word driver selection line FXT is VPP, and the inactivation level is VKK2.

  The main word line MWB and the word driver selection line FXT driven in this way are connected to the sub word drivers included in the memory cell array 11.

  FIG. 3 is a schematic plan view showing the structure of the memory cell array 11.

  As shown in FIG. 3, the memory cell array 11 has a plurality of memory mats MAT laid out in a matrix. A sub word driver area SW is provided between two memory mats MAT adjacent in the X direction. On the other hand, a sense amplifier area SAA is provided between two memory mats MAT adjacent in the Y direction. A subword cross region SX is provided in a region where a column of subword driver regions SW extending in the Y direction intersects with a column of sense amplifier regions SAA extending in the X direction. In the sub-word cross area SX, a sub-amplifier for driving a main input / output wiring described later is disposed.

  FIG. 4 is a schematic plan view showing a part of the memory cell array 11 further enlarged.

  As shown in FIG. 4, in the memory cell array 11, local input / output wiring pairs LIOT and LIOB extending in the X direction and main input / output wiring pairs MIOT and MIOB extending in the Y direction are provided. The local input / output wiring pair LIOT, LIOB and the main input / output wiring pair MIOT, MIOB are data input / output wirings constructed hierarchically.

  The local input / output line pair LIOT, LIOB is used to transmit the read data read from the memory cell MC and the write data to be written to the memory cell MC in the memory cell array 11. The local input / output wiring pair LIOT and LIOB are differential data input / output wirings that transmit read data and write data using a pair of wirings. The local input / output line pairs LIOT and LIOB are laid out in the X direction on the sense amplifier area SAA and the subword cross area SX.

  The main input / output wiring pair MIOT, MIOB is used for transmitting read data from the memory cell array 11 to the main amplifier 14 and transmitting write data from the main amplifier 14 to the memory cell array 11. The main input / output wiring pair MIOT and MIOB are also differential data input / output wirings that transmit read data and write data using a pair of wirings. The main input / output wiring pair MIOT, MIOB is laid out in the Y direction on the memory mat MAT and the sense amplifier area SAA. A large number of main input / output wiring pairs MIOT and MIOB extending in the Y direction are provided in parallel and connected to the main amplifier 14.

  In the memory mat MAT, memory cells MC are arranged at the intersections between the sub-word lines SWL extending in the X direction and the bit lines BLT or BLB extending in the Y direction. The memory cell MC has a configuration in which a cell transistor Tr and a cell capacitor C are connected in series between a corresponding bit line BLT or BLB and a plate wiring (for example, a precharge wiring). The cell transistor Tr is composed of an N-channel MOS transistor, and its gate electrode is connected to the corresponding sub word line SWL.

  A large number of sub word drivers SWD are provided in the sub word driver area SW. Each sub word driver SWD drives the corresponding sub word line SWL based on the row address.

  Further, the main word line MWB and the word driver selection line FXT are connected to the sub word driver SWD. A plurality of word driver selection lines FXT are wired on one sub word driver SWD, and one of the plurality of sub word drivers SWD selected by one main word line MWB is selected by one word driver selection line FXT. One sub word line SWL is activated by selecting.

  In the sense amplifier area SAA, a large number of sense amplifiers SA, an equalize circuit EQ, and a column switch YSW are provided. Each sense amplifier SA and each equalize circuit EQ is connected to a corresponding bit line pair BLT, BLB. The semiconductor device according to the present embodiment has a so-called open bit line structure, and therefore, the bit line pair BLT and BLB connected to the same sense amplifier SA has different memory mats MAT (that is, two memories adjacent in the Y direction). Mat). The sense amplifier SA amplifies the potential difference generated in these bit line pairs BLT and BLB, and the equalizing circuit EQ equalizes the bit line pair BLT and BLB to the same potential. The read data amplified by the sense amplifier SA is first transmitted to the local input / output line pair LIOT, LIOB, and further transmitted to the main input / output line pair MIOT, MIOB.

  The column switch YSW is provided between the corresponding sense amplifier SA and the local input / output wiring pair LIOT, LIOB, and connects the two when the corresponding column selection signal YS is activated to a high level. The column selection signal YS is generated by the column decoder 13 based on the column address.

  In the sub word cross region SX, a plurality of sub amplifiers SUB are provided. A plurality of sub-amplifiers SUB are provided for each sub-word cross region SX, and drive the corresponding main input / output wiring pair MIOT, MIOB. The input terminal of each sub-amplifier SUB is connected to the corresponding local input / output wiring pair LIOT, LIOB, and the output terminal of each sub-amplifier SUB is connected to the corresponding main input / output wiring pair MIOT, MIOB. Each sub-amplifier SUB drives the main input / output line pair MIOT, MIOB based on the data on the corresponding local input / output line pair LIOT, LIOB, respectively. Instead of the sub-amplifier SUB, a so-called pass gate in which the main input / output wiring pair MIOT, MIOB and the local input / output wiring pair LIOT, LIOB are connected by an N-channel MOS transistor may be used.

  As described above, the main input / output wiring pair MIOT, MIOB is provided so as to cross the memory mat MAT. One end of each main input / output wiring pair MIOT, MIOB is connected to the main amplifier 14. As a result, the data read using the sense amplifier SA is transferred to the sub-amplifier SUB via the local input / output wiring pair LIOT, LIOB, and further sent to the main amplifier 14 via the main input / output wiring pair MIOT, MIOB. It is done. The main amplifier 14 further amplifies data supplied via the main input / output wiring pair MIOT and MIOB.

  FIG. 5 is a circuit diagram showing a configuration of the sub word driver SWD according to the first embodiment.

  As shown in FIG. 5, the sub-word driver SWD according to the first embodiment includes P-channel MOS transistors P1 and P2 and an N-channel MOS transistor N1. The source of the transistor P1 is connected to the corresponding word driver selection line FXT, the drain is connected to the corresponding sub word line SWL, and the gate electrode is connected to the corresponding main word line MWB. An internal potential VKK1 is supplied to the source of the transistor N1 via a power supply line, a drain is connected to the corresponding sub word line SWL, and a gate electrode is connected to the corresponding main word line MWB via the transistor P2. The internal potential VKK2 is supplied to the gate electrode of the transistor P2 through the power supply wiring. The transistor P2 is used to reduce GIDL (Gate Induced Drain Leakage) by relaxing the gate-drain voltage of the transistor N1.

  With this configuration, each sub word driver SWD drives the corresponding sub word driver SWD to the VPP level when the corresponding main word line MWB and the corresponding word driver select line FXT are both at the active level. In other cases, the corresponding sub-word driver SWD is driven to the inactive level.

  Although not particularly limited, four word driver selection lines FXT are allocated to one main word line MWB in one memory mat MAT. For example, FIG. 5 shows three main word lines MWB0 to MWB2, and word driver selection lines FXT0 to FXT3 are commonly assigned to these main word lines MWB0 to MWB2.

  More specifically, the sub word drivers SWD0 to SWD3 to which the main word line MWB0 is assigned are connected to the word driver selection lines FXT0 to FXT3, respectively, thereby driving the sub word lines SWL0 to SWL3, respectively. The sub word drivers SWD4 to SWD7 to which the main word line MWB1 is assigned are connected to the word driver selection lines FXT0 to FXT3, respectively, thereby driving the sub word lines SWL4 to SWL7, respectively. Further, the sub word drivers SWD8 to SWD11 to which the main word line MWB2 is assigned are connected to the word driver selection lines FXT0 to FXT3, respectively, thereby driving the sub word lines SWL8 to SWL11, respectively.

  Then, the sub word drivers SWD0, SWD2, SWD4, SWD6, SWD8, and SWD10 connected to the word driver selection lines FXT0 and FXT2 are arranged on one side (left side) in the X direction of the memory mat MAT. On the other hand, the sub word drivers SWD1, SWD3, SWD5, SWD7, SWD9, SWD11 connected to the word driver selection lines FXT1, FXT3 are arranged on the other side (right side) in the X direction of the memory mat MAT.

  All the sub word lines SWL0 to SWL11 extend in the X direction and are arranged in this order in the Y direction. Therefore, the four sub word lines SWL corresponding to the same main word line MWB are continuously arranged in the Y direction.

  FIG. 6 is a waveform diagram for explaining the operation of the sub-word driver SWD according to the first embodiment. (A) shows the operation when activated, and (b) to (d) are deactivated. It shows the operation when it is done.

  First, as shown in FIG. 6A, when the corresponding main word line MWB and the corresponding word driver selection line FXT are both at the active level, the sub word driver SWD drives the corresponding sub word line SWL to the VPP level. To do. As described above, the activation level of the main word line MWB is VKK1, and the activation level of the word driver selection line FXT is VPP. In this case, since the transistor P1 is turned on, the sub word line SWL is driven to the VPP level. As a result, the cell transistor Tr connected to the sub word line SWL is turned on.

  At this time, the gate potential of the transistor N1 is suppressed to the VKK2 level by the intervention of the transistor P2. For this reason, it is possible to suppress GIDL despite using a lower potential (VKK3) as the activation level of the main word line MWB.

  On the other hand, there are three types of inactive states of the sub word driver SWD.

  As shown in FIG. 6B, the first inactive state is obtained when both the corresponding main word line MWB and the corresponding word driver selection line FXT are at the inactive level. As described above, the inactive level of main word line MWB is VPP, and the inactive level of word driver select line FXT is VKK2. In this case, since the transistor N1 is turned on, the sub word line SWL is driven to the VKK1 level. As a result, the cell transistor Tr connected to the sub word line SWL is kept off.

  The second inactive state is obtained when the corresponding main word line MWB is at the inactive level and the corresponding word driver selection line FXT is at the active level, as shown in FIG. 6C. As described above, the inactive level of main word line MWB is VPP, and the active level of word driver select line FXT is VPP. Also in this case, since the transistor N1 is turned on, the sub word line SWL is driven to the VKK1 level. As a result, the cell transistor Tr connected to the sub word line SWL is kept off.

  The third inactive state is obtained when the corresponding main word line MWB is at the active level and the corresponding word driver selection line FXT is at the inactive level, as shown in FIG. 6 (d). As described above, the activation level of the main word line MWB is VKK3, and the inactivation level of the word driver selection line FXT is VKK2. Here, since VKK2> VKK3, the transistor P1 is turned on even in the third inactive state. As a result, the sub word line SWL is driven to the VKK2 level, and the cell transistor Tr connected to the sub word line SWL enters a deeper off state.

  Thus, in the present embodiment, among the deactivated sub word drivers SWD, the corresponding main word line MWB is at the active level, that is, the third inactive sub word driver. For SWD, the corresponding sub word line SWL is driven to a VKK2 level lower than the VKK1 level.

  For example, considering the case where the sub word line SWL2 shown in FIG. 5 is selected, the sub word lines SWL4 to SWL11 not sharing the main word line MWB are at the VKK1 level and the sub word lines SWL0, SWL1, SWL3 sharing the main word line MWB are considered. Becomes VKK2 (<VKK1) level. As a result, the influence on the adjacent sub word lines SWL1 and SWL3 due to the sub word line SWL2 being driven to the VPP level is reduced.

  That is, for example, when the sub word line SWL2 is driven to the VPP level, the threshold value of the cell transistor Tr connected to the sub word lines SWL1 and SWL3 adjacent to the sub word line SWL2 decreases, and the leakage of the charge accumulated in the cell capacitor C occurs. May increase. However, in the present embodiment, since the inactivity level of the adjacent sub word lines SWL1 and SWL3 is set to a lower VKK2 level, charge leakage can be suppressed. In addition, in this embodiment, since only the non-selected sub word line SWL sharing the main word line MWB is set to the VKK2 level, an increase in GIDL due to the use of a lower negative potential is minimized. Is possible.

  Furthermore, in this embodiment, since the word driver selection line FXT transmits a single signal instead of a complementary signal, the number of word driver selection lines can be halved as compared with the conventional case, and the word driver selection line FXT The area occupied by the wiring layer is also reduced.

  FIG. 7 is a circuit diagram showing a configuration of a sub word driver SWD according to the second embodiment.

  As shown in FIG. 7, in the sub-word driver SWD according to the second embodiment, the P-channel MOS transistor P2 is shared by the two sub-word drivers SWD. The transistor P2 is connected to be interposed between the gate electrode of the transistor P1 and the main word line MWB. For example, the gate electrodes of the transistors P1 and N1 included in the sub word drivers SWD0 and SWD2 are all commonly connected, and the transistor P2 is inserted between the contact and the main word line MWB0.

  Since other configurations are the same as those of the first embodiment shown in FIG. 5, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  In the present embodiment, since the number of transistors P2 can be halved compared to the first embodiment described above, the area occupied on the chip by the sub word driver SWD is reduced in addition to the effects of the first embodiment described above. It becomes possible to reduce more.

  FIG. 8 is a circuit diagram showing a configuration of a sub word driver SWD according to the third embodiment.

  As shown in FIG. 8, in the third embodiment, FIG. 5 shows that different word driver selection lines FXT are assigned to a plurality of sub word drivers SWD corresponding to adjacent main word lines MWB. This is different from the first embodiment shown.

  For example, the word driver selection lines FXT0 to FXT3 are assigned to the sub word drivers SWD0 to SWD3 corresponding to the main word line MWB0, respectively, and the word driver selection lines FXT4 to FXT7 are respectively assigned to the sub word drivers SWD4 to SWD7 corresponding to the main word line MWB1. Are assigned, and word driver selection lines FXT0 to FXT3 are assigned to the sub word drivers SWD8 to SWD11 corresponding to the main word line MWB2, respectively. That is, word driver select lines FXT0 to FXT3 are assigned to the sub word drivers SWD corresponding to the even-numbered main word lines MWB0, MWB2,..., And the odd-numbered main word lines MWB1, MWB3,. Word driver selection lines FXT4 to FXT7 are assigned to the corresponding sub word driver SWD.

  Further, in the present embodiment, when a predetermined main word line MWB is selected based on the address signal ADD, the main word lines MWB on both sides adjacent to the main word line MWB are forcibly set to the active level. For example, when the main word line MWB1 is selected based on the address signal ADD, not only the main word line MWB1 but also the main word lines MWB0 and MWB2 on both sides adjacent thereto are activated to the VKK3 level. Such an operation is performed by the main word driver 51 shown in FIG.

  Thereby, for example, when any of the sub word drivers SWD4 to SWD7 corresponding to the main word line MWB1 is activated, the sub word drivers SWD0 to SWD3 corresponding to the main word line MWB0 and the sub word driver SWD8 corresponding to the main word line MWB2 are activated. All of .about.SWD11 are in the third inactive state. Therefore, in this embodiment, even when the selected sub word line SWL is located at the end of the group like the sub word lines SWL4 and SWL7, the unselected sub word lines SWL located on both sides thereof are arranged. Is always VKK2 level.

  As described above, in this embodiment, regardless of which sub word line SWL is selected, the unselected sub word lines SWL located on both sides of the sub word line SWL can always be set to the VKK2 level. Leakage can be suppressed more effectively.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Memory cell array 12 Row decoder 13 Column decoder 14 Main amplifier 20 Access control circuit 21 Address terminal 22 Command terminal 30 Data input / output circuit 31 Data terminal 40 Power supply circuit 41, 42 Power supply terminal 50 Predecoder 51 Main word driver 52 Word Selection driver BL Bit line BLT, BLB Bit line pair C Cell capacitor EQ Equalize circuit FXT Word driver selection line LIOT, LIOB Local input / output wiring pair MAT Memory mat MC Memory cell MIOT, MIOB Main input / output wiring pair MWB Main word line N1, P1, P2 Transistor SA Sense amplifier SAA Sense amplifier area SUB Sub amplifier SW Sub word driver area SWD Sub word driver SWL Sub word line SX Sub word Dokurosu region Tr cell transistor YSW column switch

Claims (19)

The main word line,
A sub word line;
A word driver select line;
First and second power supply lines for supplying first and second potentials, respectively;
A first transistor of a first conductivity type connected between the word driver select line and the sub word line and having a control electrode connected to the main word line;
A second transistor of a second conductivity type connected between the sub-word line and the first power supply wiring;
A third transistor of the first conductivity type connected between the main word line and a control electrode of the second transistor, the control electrode being connected to the second power supply wiring; Semiconductor device.   The semiconductor device according to claim 1, wherein the first and second potentials have different levels. A main word driver for driving the main word line to an active level or an inactive level based on an address signal;
The active level of the main word line is a third potential different in level from the first and second potentials,
3. The semiconductor device according to claim 2, wherein the inactive level of the main word line is a fourth potential having a level different from that of the first to third potentials. A word selection driver for driving the word driver selection line to an active level or an inactive level based on the address signal;
When the main word line is at the active level, the first transistor is turned on regardless of whether the word driver selection line is at the active level or the inactive level. The semiconductor device according to claim 3.   The semiconductor device according to claim 4, wherein the activation level of the word driver selection line is the fourth potential.   6. The semiconductor device according to claim 5, wherein the inactive level of the word driver selection line is the second potential.   The semiconductor device according to claim 3, wherein the first to third potentials are negative potentials, and the fourth potential is a positive potential.   8. The semiconductor device according to claim 7, wherein the second potential is lower than the first potential, and the third potential is lower than the second potential.   The control electrodes of the first and second transistors are connected in common, whereby the main word line is connected to the control electrode of the first transistor via the third transistor. The semiconductor device according to claim 1, wherein: A main word driver for driving a main word line to an active level or an inactive level based on an address signal;
A word selection driver that drives a word driver selection line to an active level or an inactive level based on the address signal;
A sub word driver connected to the main word line and the word driver selection line and driving a sub word line,
The sub word driver drives the sub word line to an active level in response to both the main word line and the word driver selection line being at the active level, and the main word line is at the inactive level. In response to driving the sub-word line to a first inactive level, in response to the main word line being at the active level and the word driver select line being at the inactive level. A semiconductor device, wherein a line is driven to a second inactive level different from the first inactive level.   11. The semiconductor device according to claim 10, wherein the second inactive level of the sub word line is equal to the inactive level of the word driver selection line. The first and second inactive levels of the sub word line are both negative potentials,
12. The semiconductor device according to claim 11, wherein the second inactivation level of the sub word line is lower than the first inactivity level of the sub word line.   13. The semiconductor device according to claim 12, wherein the inactive level of the main word line, the active level of the word driver selection line, and the active level of the sub word line are the same positive potential. A plurality of main word lines including a first main word line;
A plurality of word driver select lines including first and second word driver select lines;
A plurality of sub-word lines including first and second sub-word lines;
A plurality of sub-word drivers including first and second sub-word drivers;
First and second power supply lines for supplying first and second potentials, respectively,
The plurality of subword drivers are:
A first transistor of a first conductivity type connected between a corresponding one of the plurality of word driver selection lines and a corresponding one of the plurality of sub-word lines and having a control electrode connected to the corresponding main word line; When,
A second transistor of a second conductivity type connected between the corresponding sub-word line and the first power supply line and having a control electrode connected to the corresponding main word line,
The first sub-word driver is connected to the first main word line and the first word driver selection line to drive the first sub-word line,
The second sub-word driver is connected to the first main word line and the second word driver selection line to drive the second sub-word line,
Further, a third of the first conductivity type is connected between a corresponding one of the plurality of main word lines and the control electrode of the second transistor, and the control electrode is connected to the second power supply wiring. A semiconductor device comprising:   The semiconductor device according to claim 14, wherein the third transistor is assigned to each of the plurality of sub-word drivers.   15. The semiconductor device according to claim 14, wherein the third transistor is commonly assigned to the first and second subword drivers. The plurality of main word lines further include a second main word line provided adjacent to the first main word line,
The plurality of sub word lines further include the third and fourth sub word lines,
The plurality of subword drivers further include third and fourth subword drivers;
The third sub-word driver is connected to the second main word line and the first word driver selection line to drive the third sub-word line,
17. The fourth sub-word driver according to claim 14, wherein the fourth sub-word driver is connected to the second main word line and the second word driver selection line to drive the fourth sub-word line. The semiconductor device according to one item. The plurality of main word lines further include a second main word line provided adjacent to the first main word line,
The plurality of sub word lines further include the third and fourth sub word lines,
The plurality of word driver selection lines further include third and fourth word driver selection lines,
The plurality of subword drivers further include third and fourth subword drivers;
The third sub-word driver is connected to the second main word line and the third word driver selection line to drive the third sub-word line;
17. The fourth sub word driver is connected to the second main word line and the fourth word driver selection line to drive the fourth sub word line. The semiconductor device according to one item. Of the plurality of sub word drivers, a sub word driver connected to the first main word line includes a first group of words including the first and second word driver selection lines among the plurality of word driver selection lines. Connected to the driver selection line,
Among the plurality of sub word drivers, a sub word driver connected to the second main word line includes a second group of words including the third and fourth word driver selection lines among the plurality of word driver selection lines. Connected to the driver selection line,
The plurality of word driver selection lines constituting the first group of word driver selection lines do not overlap with the plurality of word driver selection lines constituting the second group of word driver selection lines. 18. The semiconductor device according to 18.

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