JP2005026703A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein a weak signal on a data line deteriorates, and the risk of amplifying a data accidentally is large, in which the coupling capacitance between the data line and a word line is imbalance between data line pairs, in a highly integrated DRAM which pursues microfabrication, if the coupling capacitance between the data line and the word line is imbalanced, the noise produced in the word line is large, when the data line is amplified. <P>SOLUTION: Two or more word lines connected to two or more memory cells connected to one data line, are connected to subword driver arrays, arranged on mutually opposite sides of the memory array, one by one or several lines, alternately. When the data line is amplified, positive and negative word line noises negate each other in the subword driver, and the word line noises can be reduced. Therefore, the deterioration of the signal read by a sense amplifier can be prevented, and the reliability of memory performance can be raised. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to memory array noise reduction in a semiconductor device including a memory array.

  Non-Patent Document 1 describes noise through a word line when a dynamic random access memory DRAM is amplified. Further, as one of noises through the word line, it is described that a noise voltage on a non-selected word line generated due to the coupling capacitance between the data line and the word line generates noise in the data pair line. The influence of the noise depends on the data pair line structure (open data pair line structure or folded data pair line structure) and the data line precharge system (VD precharge system or VD / 2 precharge system). . As a result, it is described that the noise is reduced when the folded data paired line structure is adopted and the VD / 2 precharge method is adopted. Non-patent document 2 is the original document cited in Non-patent document 1.

VLSI memory pp.214-217, Kiyoo Ito, Baifukan, November 5, 1994 First edition issued

K. Itoh, IEEE Journal of Solid State Circuit, Vol.25, No. 3, (1990), pp.778-789

  Prior to the present application, the inventors of the present application conducted a detailed study on the relationship between the structure of a 1 Gb DRAM array using a 0.16 to 0.13 μm microfabrication technique and the noise caused by the coupling capacity of data lines and word lines. FIG. 10 shows a planar layout of a DRAM array examined prior to the present application and a part of a corresponding circuit diagram. In the planar layout of (a), memory cells (MC) are arranged at predetermined intersections of data lines (DL) and word lines (WL). This data line structure is a so-called folded data line structure. Here, DL that reads signals from the memory cell, WL that becomes the gate of the selection transistor, diffusion layer region (ACT), data line contact that connects ACT and DL (DLCT), and storage node contact that connects ACT and the capacitor lower electrode Only (SNCT) is shown, and the capacitor lower electrode connected to SNCT is omitted. An upper sub word driver column (SWDA-U) and a lower sub word driver column (SWDA-D) are arranged above and below the memory array, and two word lines WL are alternately connected to the upper and lower sub word driver columns. Hereinafter, the subword driver is abbreviated as SWD as necessary. A left sense amplifier array (SAA-L) and a right sense amplifier array (SAA-R) are arranged on the left and right sides of the memory array, and two data lines DL are alternately connected to the left and right sense amplifier arrays. Hereinafter, the sense amplifier is abbreviated as SA as necessary.

  The reason why the SWDs and SAs are alternately arranged in this way is to relax the layout pitch of the SWDs and SAs. For example, looking at the boundary between SWDA-U and the memory array, WL passes through the boundary and enters SWD (WL1, WL2, WL5, WL6) and ends at the boundary (WL0, WL3, WL4, WL7) is repeated every second. When WL and SWD are connected in this way, the layout pitch in the data line direction for one SWD can be relaxed to a pitch of two WLs. As for the SA layout, the pitch in the word line direction is relaxed to a pitch corresponding to two pairs of DLs (4 DLs) by interleaving. In DRAM, since the memory cell is miniaturized, the pitch of WL and DL is very small. Accordingly, it is becoming difficult to lay out SWDs and SAs at a predetermined pitch, and the alternate arrangement is important.

  Here, attention is focused on the connection relationship between the WL and the SWD array. Focusing on two adjacent memory cells, MC0 and MC1, connected to DL0T, these cells share one DLCT, but WL0 and WL1, which are WL connected to these cells, are both Connected to SWDA-U. On the other hand, focusing on two adjacent memory cells MC2 and MC3 connected to DL0B, they also share a single DLCT, but WL2 and WL3 connected to these cells are both WL2 and WL3. Connected to SWDA-D. Therefore, in the layout of the memory array of FIG. 10, WLs connected to two memory cells sharing the DLCT are both connected to the same SWD column. Looking at the entire memory array, the pattern shown in Fig. 10 (a) is repeated vertically and horizontally, so the WL connected to the MC connected to DL0T (WL0, WL1, WL4, WL5 in the figure) is All WLDAs (WL2, WL3, WL6, WL7 in the figure) connected to SWDA-U and connected to MC connected to DL0B are all connected to SWDA-D. Accordingly, all the word lines connected to the memory cells connected to one data line are connected to the sub word driver column in the same column.

  This is shown in a circuit diagram in FIG. 10 (b). In the folded data line configuration, memory cells are connected to half of the intersections of the data lines and the word lines. For example, the memory cell MC0 is connected between DL0T and WL0, but there is no MC connected to DL0B and WL0. MC includes a selection transistor TG and a cell capacitor CS. One electrode of CS is a plate PL and is connected in common with other memory cells in the array. The other electrode of CS is connected to one of the source or drain of TG, and the other source or drain of TG is connected to DL. DL0T and DL0B are paired and connected to SA0 in SA column L, and DL1T and DL1B are connected to SA1 in SA column R. These SAs amplify a minute voltage difference generated in the DL pair by a signal from the memory cell, so that one DL is at a high level and the other DL is at a low level.

  Only the MC0, MC1, MC2, and MC3 portions of FIG. 10 are enlarged, and the layout is shown in FIG. 11 (a) and the circuit diagram is shown in FIG. 11 (b). In addition, the parasitic capacitors generated between WL and DL of these MCs are also shown. Parasitic capacitances C00 and C01 are generated between WL0, WL1 and DL0T, respectively. Parasitic capacitances C00B and C01B are generated between WL0, WL1 and DL0B, respectively. Further, parasitic capacitances C02 and C03 are generated between WL2 and WL3 and DL0B, respectively. Parasitic capacitances C02B and C03B are generated between WL2, WL3 and DL0T, respectively.

  Sections A, B, and C indicated by arrows in the layout of FIG. 11 (a) are shown in FIGS. 12 (a), (b), and (c), respectively. The cross-sectional view of FIG. 12 shows a cross section in the vicinity of the two word lines WL0 and WL1 in the direction of the arrow shown in FIG. The ACT region on the substrate is an active region of the MOS transistor, and the other portion of the substrate is an element isolation region. WL and DL are wired on it, and DL is connected to ACT by an elliptical DLCT. SN is a lower electrode of the cell capacitor CS and is connected to ACT by SNCT. The upper electrode PL of CS is commonly connected to cells in the array, and two layers of metal wirings M2 and M3 are wired above the upper electrode PL.

  Here, the sizes of C00 and C00B are compared. As shown in the sectional view A of FIG. 12 (a), DLCT0 connected to DL0T passes between WL0 and WL1 very closely. The distance between DLCT0 and WL0 is about 30 nm when a memory cell is manufactured by performing microfabrication of 0.13 μm. Accordingly, C00 which is the capacitance between DL0T and WL0 is almost formed between DLCT0 and WL0. On the other hand, as shown in the cross-sectional view B of FIG. 12 (b), DL0B only passes through the upper part of WL0, and C00B, which is the capacitance between DL0B and WL0, is determined by the distance between the DL and WL layers. In the μm generation, it is about 250 nm. Therefore, C00B is much smaller than C00, and a detailed capacity simulation showed that C00B was about 1% when C00 was 100%. That is, as shown in FIG. 11B, in the folded data line configuration, the coupling capacity of WL0 to DL0T and DL0B seems to be balanced at C00 and C00B at first glance, but in a highly integrated DRAM using fine memory cells. C00 is very large, and imbalance occurs. Similarly, C01, C02, and C03 are very large with respect to C01B, C02B, and C03B, respectively. In other words, the DL-WL coupling capacity is large when there is an MC between the DL and WL, and almost negligible when there is no MC.

  This imbalance in DL-WL coupling capacitance is due to the high integration of DRAM, and the thickness of the insulating film in the direction parallel to the substrate becomes thinner than the thickness of the interlayer insulating film in the direction perpendicular to the substrate. This is a new problem that has become apparent. Thus, in the memory array in which the DL-WL coupling capacitance is unbalanced, WL noise becomes a problem as described below.

  FIG. 13 shows the memory array of FIG. 10 and the data pattern when the word line noise becomes the largest. WL0 to WL7 are respectively connected to SWD0 to SWD7, SWD0, SWD1, SWD4, and SWD5 are arranged in SWDA-U, and SWD2, SWD3, SWD6, and SWD7 are arranged in SWDA-D. DL0T and DL0B are connected to SA0 in SA column L, and DL1T and DL1B are connected to SA1 in SA column R. The circuit diagram of SA is shown in FIG. 14 (a), and the operation waveform of the array is shown in FIG. 14 (b).

  Consider the case where WL0 is selected in FIG. WLs other than WL0 in the array are connected to VSSU or VSSD by N-channel MOS transistors in each SWD. As shown in Fig. 14 (b), all SWDs output 0V to WL during standby. In MC, the selection transistor is turned OFF, and a voltage of VDL (for example, 1.8 V) or VSS (for example, 0 V) is written in the capacitor according to information. In SA, SHRU and SHRD are VPP (eg, 3.5 V), CSP and CSN are VBLR (eg, 0.9 V), BLEQ is VPP, and YS is 0 V, and DL is precharged to the potential of VBLR.

  When a bank activate command and address are input to the DRAM and the memory array shown in the figure is selected, SHRL and BLEQ are dropped to 0V during SA0, and precharge is interrupted. Subsequently, WL0 is activated to 3.5V in SWD0. Then, the MC selection transistor connected to WL0 is turned ON, and a signal is output from the cell capacitor to DL0, DL1, etc. precharged to 0.9V. At this time, for example, a low level (L) signal comes out on all T side DLs from DL0T to DL1023T except DLnT among 1024 pairs and 2048 DLs, and a high level (H) signal only on DLnT Think about when it comes out. At this time, since no signal is output from DL0B to DL1023B, which is the other DL, it remains 0.9V. This pattern or a pattern obtained by reversing H and L is the worst condition in which the WL noise becomes the largest. Subsequently, when SA is activated by driving CSN to 0V and CSP to 1.8V, DL0T to DL1023T other than DLnT are amplified to 0V, and DL0B to DL1023B other than DLnB are amplified to 1.8V.

  This is shown in FIG. DL0T and DL1T indicate that DL0T and DL1T are amplified to 0V by circled L, and DL0B and DL1B indicate that DL0B and DL1B are amplified to 1.8V by circled H. At this time, the noise generated in WL0 is as follows. WL0 receives negative noise from the data lines other than DLnT from DL0T to DL1023T via the coupling capacitance. On the other hand, WL0 receives positive noise from the data lines DL0B to DL1023B other than DLnB via the coupling capacitance. The noise generated in WL0 is the sum of these noises, but as mentioned above, WL0 is connected to the MC connected to the DL on the T side from DL0T to DL1023T. For example, between WL0 and DL0B The coupling capacity is about 1% of the coupling capacity between WL0 and DL0T. That is, the coupling capacity between the WL0 and B side data lines is negligibly small compared to the coupling capacity between the WL0 and T side data lines. Therefore, with respect to WL0, negative noise is generated with almost no cancellation. This is shown by the minus sign circled on WL0. Similarly, negative noise is generated in WL1, WL4, and WL5. On the other hand, WL2, WL3, WL6, WL7 are connected to the MC connected to the DL on the B side from DL0B to DL1023B. For example, the coupling capacity between WL2 and DL0T is the coupling between WL2 and DL0B. Smaller than the capacity, about 1 percent. That is, the coupling capacitance between the WL2 and T side data lines is negligibly small compared to the coupling capacitance between the WL2 and B side data lines. Therefore, positive noise is generated in these WLs, and this is indicated by a plus sign circled on the WL. The waveform of FIG. 14 (b) also shows WL noise to WL0, WL1, and WL2.

Here, the noise generated in WL flows as an electric charge into the VSS wired on the SWD through the N-channel MOS transistor in the SWD. This VSS wiring has a high impedance because it is wired over several millimeters on the SWD from the power pad in the center of the chip to the chip edge in DRAM. Therefore, the noise generated on the word line
Will happen to VSS on D.

  As for the WL noise of the entire array, positive noise is generated in half of the WL and negative noise is generated in the other half of the array. Negative noise is generated in all WLs connected to SWDA-U, and positive noise is generated in all WLs connected to SWDA-D. Therefore, negative noise generated in VSSU that is the VSS wiring on SWDA-U works in a mutually reinforcing direction, and positive noise generated in VSSD that is the VSS wiring on SWDA-D also works in a mutually reinforcing direction. Therefore, these noises are very large. As a result of detailed circuit simulation, it was found that each became about 100mV. In addition, the noise generated in the WL is transmitted to the power pad in the center of the chip and is finally canceled out, so that the decay time is long.

  The WL noise at the time of DL amplification returns to DL again via the coupling capacitance between WL and DL, causing malfunction. As shown in FIG. 13, when an H level signal is output only in DLnT, negative noise is returned from DL0, WL1, WL4, WL5, etc. to DLnT. Also, positive noise returns from DL2, WL3, WL6, WL7, etc. to DLnB. That is, when viewed from the DLn pair, noise in the opposite direction to the original signal is returned, and the signal amount is reduced. If the charge accumulated in the cell capacitor of the memory cell at the intersection of WL0 and DLnT decreases due to leakage, etc., the H level signal that appears on DLnT when WL0 is activated decreases. This WL noise causes the data to be inverted during amplification. FIG. 14 shows this state. DLnT and DLnB are amplified in the direction opposite to the minute potential difference generated in DLnT and DLnB at the time of WL activation, and data is erroneously read out.

  That is, in the memory array of FIG. 10 examined prior to the present application, in the worst case, the word line WL noise works in a direction in which the sense amplifier driver SWD reinforces each other. This degrades the signal read by the sense amplifier, which makes the memory operation unstable.

  Accordingly, an object of the present invention is to provide a highly reliable memory array by reducing noise generated in a word line when a data line is amplified in a highly integrated DRAM pursuing fine processing.

  Representative means of the present invention are as follows. Arranged so that multiple word lines connected to multiple memory cells connected to a single data line are connected to sub-word driver columns arranged on the opposite side of the memory array every other line or every few lines. To do. With this arrangement, in the worst pattern of word line noise in which all other data line pairs except the set of data line pairs of interest described above read out data opposite to the data line pairs of interest, one of the memory arrays Half of the word lines connected to the sub-word driver row placed on the side of the side receive positive noise, and the other half receives negative noise. Therefore, these word line noises are connected to the ground power supply wiring in the sub-word driver row. Cancel each other out and reduce. Similarly, in the sub-word driver column arranged on the other side of the memory array, half of the word lines connected receive positive noise and the other half receive negative noise. The ground power supply wiring in the driver array cancels each other and is reduced.

  The reliability of memory operation including DRAM can be improved.

  Embodiments of the present invention will be described below in detail with reference to the drawings. The circuit elements constituting each block of the embodiment are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as CMOS (complementary MOS transistor). A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) circuit symbol without an arrow represents an N-type MOSFET (NMOS), and is distinguished from a P-type MOSFET (PMOS) with an arrow. Hereinafter, in order to call MOSFET, it may be simplified and called MOS. However, the present invention is not limited to a field effect transistor including an oxide film insulating film provided between a metal gate and a semiconductor layer, and a general FET such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is used. Applied to the circuit.

(Example 1)
FIG. 1 shows a planar layout of a first word line noise reduction array of the present invention and a part of a corresponding circuit diagram. In the planar layout of (a), memory cells (MC) are arranged at predetermined intersections of data lines (DL) and word lines (WL). Here, DL that reads signals from the memory cell, WL that becomes the gate of the selection transistor, diffusion layer region (ACT), data line contact that connects ACT and DL (DLCT), and storage node contact that connects ACT and the capacitor lower electrode Only (SNCT) is shown, and the capacitor lower electrode connected to SNCT is omitted. Originally, there are about 2048 DLs and about 512 WLs in one array, but only a part of them is shown here. An upper sub word driver column SWDA-U and a lower sub word driver column SWDA-D are arranged above and below the memory array, and two word lines WL are alternately connected to the upper and lower sub word driver columns. A left sense amplifier array SAA-L and a right sense amplifier array SAA-R are arranged on the left and right sides of the memory array, and two data lines DL are alternately connected to the left and right sense amplifier arrays.

  The reason why the SWDs and SAs are alternately arranged in this way is to relax the layout pitch of the SWDs and SAs. For example, looking at the boundary between SWDA-U and the memory array, WL passes through the boundary and enters SWD (WL1, WL2, WL5, WL6) and ends at the boundary (WL0, WL3, WL4, WL7) is repeated two by two. When WL and SWD are connected in this way, the layout pitch in the data line direction for one SWD can be relaxed to a pitch of two WLs. In addition, when patterning WL, super-resolution lithography such as phase shift method or annular illumination is required, but if two adjacent WLs are connected to SWD, the two light phases are reversed. Since the WL can be connected to the SWD, the SWD layout is easy.

  As for the SA layout, the pitch in the word line direction is relaxed to a pitch corresponding to two pairs of DLs (4 DLs) by interleaving. In DRAM, since the memory cell is miniaturized, the pitch of WL and DL is very small. Accordingly, it is becoming difficult to lay out SWDs and SAs at a predetermined pitch, and the alternate arrangement is important.

  Here, attention is focused on the connection relationship between the WL and the SWD array. The present invention is characterized by the connection relationship between the alternately arranged SWD rows and the WL. Focusing on MC0 and MC1, which are two adjacent memory cells connected to DL0T, these MCs share one DLCT, but WL0 of these connected to WL0 is SWDA-D. While connected, WL1 is connected to SWDA-U. On the other hand, focusing on two adjacent memory cells MC2 and MC3 connected to DL0B, they also share one DLCT, but WL2 of WLs connected to these cells is connected to SWDA-U. While connected, WL3 is connected to SWDA-D. Therefore, in the layout of the word line noise reduction array of the first embodiment, WLs connected to two memory cells sharing the DLCT are connected to different SWD columns.

  Looking at the entire memory array, the pattern shown in Fig. 1 (a) is repeated vertically and horizontally, so half of the WLs (WL1 and WL5 in the figure) connected to the MC connected to DL0T are SWDA-U. Connect the other half (WL0, WL4 in the figure) to SWDA-D. Also, half of the WLs (WL2 and WL6 in the figure) connected to the MC connected to DL0B are connected to SWDA-U, and the other half (WL3 and WL7 in the figure) are connected to SWDA-D. . Therefore, half of the word lines connected to the memory cells connected to one data line are connected to the sub word driver column of one column, and the other half are connected to the sub word driver column of the other column. Yes. Furthermore, SWDs in SWDA-U are connected to a common VSS wiring VSSU. Similarly, SWDs in SWDA-D are also connected to a common VSS wiring VSSD. By wiring VSS in this way, it is possible to cancel WL noise in VSS.

  This is shown in a circuit diagram in FIG. In the folded data line configuration, memory cells are connected to half of the intersections of the data lines and the word lines. For example, the memory cell MC0 is connected between DL0T and WL0, but the MC is not connected between DL0B and WL0. MC includes a selection transistor TG and a cell capacitor CS. One electrode of CS is a plate PL and is connected in common with other memory cells in the array. The other electrode of CS is connected to one of the source or drain of TG, and the other source or drain of TG is connected to DL. DL0T and DL0B are connected to SA0 in SA column L as a pair, and DL1T and DL1B are connected to SA1 in SA column R. These SAs amplify a minute voltage difference generated in the DL pair by a signal from the memory cell, so that one DL is at a high level and the other DL is at a low level.

  As will be described in detail later, when DL0T is amplified to a low level by DL0B and to a high level to DL0B, negative noise is applied to WL0 and WL1, and positive noise is applied to WL2 and WL3. However, the positive and negative noise added to WL1 and WL2 cancels each other on VSSU, which is the power supply wiring on SWDA-U. Similarly, positive and negative noise applied to WL0 and WL3 cancel each other on VSSD, which is the power supply wiring on SWDA-D. In the memory array of the present invention, WL noises from one data line pair are canceled each other, so that no matter what data pattern is generated in other data line pairs in the array, a noise canceling effect is produced.

  A configuration of a DRAM using the word line noise reduction array of the present invention will be described. FIG. 2 shows a configuration diagram of the DRAM chip. A bonding pad (PAD) and indirect peripheral circuits (PERI1, PERI2) are arranged in the center and long side direction of the chip. An address / data input / output circuit, a power supply circuit, a refresh control circuit, a main amplifier, and the like are arranged here. An array control circuit (A-CTL) that controls SWD and SA is arranged in the short side direction. The above circuit divides the chip into four blocks, each surrounded by a row decoder (R-DEC) connected to the main word line and a column decoder (C-DEC) connected to the column selection line. Yes. The memory array (MA) shown in FIG. 1 is the portion surrounded by the SA and SWD columns, where each block is divided by the sense amplifier column (SAA) in the row direction and the sub word driver column (SWDA) in the column direction. It is.

  FIG. 3 shows a first subword driver used in the word line noise reduction array of the present invention shown in FIG. In this SWD, all SWDs in the same SWD row are connected to a common ground wiring VSSU. Also, since SWDs are arranged alternately with respect to the memory array, looking at the boundary between SWDA-U and the memory array, WL (WL1, WL2, WL5, WL6) that enters the SWD through the boundary, WLs (WL0, WL3, WL4, WL7) ending at the boundary are repeated two by two. In the WL noise reduction array of the present invention, the WL (WL1, WL5) connected to the MC connected to DL0T in FIG. 1 and the WL (WL2, WL6) connected to the MC connected to DL0B are halved by SWD in SWDA-U. It is characterized by being connected.

  Taking SWD1 as an example, one SWD is composed of two N-channel MOS transistors MN1 and MN2 and one P-channel MOS transistor MP1. MN1 and MN2 have sources connected to VSSU and drains connected to WL1. The gate of MN1 is connected to the main word line (MWLB), and the gate of MN2 is connected to FX1B. The substrates (back gate or well potential) of both MN1 and MN2 may be connected to VSSU as shown in the figure, or may be connected to VBB wiring provided separately. For MP1, connect the source to FX1, the drain to WL1, and the gate to MWLB. The substrate (back gate or well potential) of MP1 is connected to VPP (for example, 3.5V). Note that the WL of the memory array arranged on the upper side of the SWDA-U and the WL of the memory array arranged on the lower side are connected to each other through the SWDA-U.

  Here, the operation when MWLB and FX1 are activated and WL1 is selected will be described. In this case, MWLB is 0V, FX1 is 3.5V, FX2, FX5, FX6 is 0V, FX1B is 0V, FX2B, FX5B, FX6B is 3.5V. In SWD1, MP1 is turned on, MN1 and MN2 are turned off, and WL1 is activated to 3.5V. On the other hand, in SWD2, SWD5, and SWD6, the transistor corresponding to MN1 is turned off, the transistor corresponding to MN2 is turned on, and WL2, WL5, and WL6 are connected to VSSU (0 V). The gate of the transistor corresponding to MP1 is 0V, but since the source is also 0V, it is not turned on. Therefore, WL2, WL5, and WL6 that are non-selected WLs are connected to VSSU only by transistors corresponding to MN2.

  Other WL1 operation modes include: (1) Both MWLB and FX1 are not selected, (2) MWLB is not selected and FX1 is selected, but in (1), both MN1 and MN2 are turned on to VSSU In (2), only MN1 is turned on and connected to VSSU. The same applies to other SWDs.

  Next, with respect to the word line noise reduction array of the present invention, the WL noise reduction effect in the worst pattern in which the WL noise is greatest will be shown. As shown in Fig. 4, low-level (L) signals are output to all T-side DLs from DL0T to DL1023T except for DLnT among 1024 pairs and 2048 DLs, and high level (H ) When the signal comes out. This pattern or a pattern obtained by reversing H and L is the worst condition in which the WL noise becomes the largest. When SA is activated, DL0T to DL1023T other than DLnT are amplified to 0V, and DL0B to DL1023B other than DLnB are amplified to 1.8V. DL0T and DL1T indicate that DL0T and DL1T are amplified to 0V by circled L, and DL0B and DL1B indicate that DL0B and DL1B are amplified to 1.8V by circled H. At this time, the noise generated in WL0 is as follows. WL0 receives negative noise from the data lines other than DLnT from DL0T to DL1023T via the coupling capacitance. On the other hand, WL0 receives positive noise from the data lines DL0B to DL1023B other than DLnB via the coupling capacitance. The noise generated in WL0 is the sum of these noises, but as mentioned above, WL0 is connected to the MC connected to the DL on the T side from DL0T to DL1023T. For example, the cup between WL0 and DL0B The ring capacity is about 1% of the coupling capacity between WL0 and DL0T. That is, the coupling capacity between the WL0 and B side data lines is negligibly small compared to the coupling capacity between the WL0 and T side data lines. Therefore, with respect to WL0, negative noise is generated with almost no cancellation. This is shown by the minus sign circled on WL0. Similarly, negative noise is generated in WL1, WL4, and WL5. On the other hand, WL2, WL3, WL6, WL7 are connected to the MC connected to the DL on the B side from DL0B to DL1023B. For example, the coupling capacity between WL2 and DL0T is the coupling between WL2 and DL0B. Smaller than the capacity, about 1 percent. That is, the coupling capacitance between the WL2 and T side data lines is negligibly small compared to the coupling capacitance between the WL2 and B side data lines. Therefore, positive noise is generated in these WLs, and this is indicated by a plus sign circled on the WL.

  As shown in FIG. 4, in the word line noise reduction array of the present invention, unlike the memory array examined prior to the present application shown in FIG. 13, negative noise occurs in half of the WLs connected to SWDA-U, Positive noise occurs in half of the WLs. Therefore, positive and negative noises cancel each other out at VSSU, which is a power supply wiring on SWDA-U, and WL noise is reduced. Similarly, in SWDA-D, negative noise is generated in half of the connected WLs, and positive noise is generated in half of the WLs. Therefore, positive and negative noises cancel each other out at VSSD, which is a power supply wiring on SWDA-D, so that WL noise is reduced.

  As described above, in the word line noise reduction array of the present invention, no matter what pattern signal appears on the data line, the positive and negative WL noises work in a direction to cancel each other in the SWD during data line amplification. WL noise can be reduced. Therefore, it is possible to prevent the signal read by the sense amplifier from being deteriorated and to improve the reliability of the memory operation.

  Further, if attention is paid to the amount of signal output from the memory cell, it is possible to accurately sense signals smaller than the memory array in FIG. It is possible to widen the operation margin when the charge stored in the cell capacitor is reduced.

  In addition, this array unbalances the coupling capacitance between one data line and one word line of the data lines operating as a pair and the coupling capacitance between the other data line and the same word line. The tolerance for is large. Therefore, the data line contact of the memory cell can be elliptical as shown in FIG. 1, and the diffusion layer can be laid out in a straight line, facilitating the process.

  That is, the refresh characteristics of the DRAM can be improved by using the array of the present invention. In addition, the DRAM manufacturing process can be simplified.

(Example 2)
FIG. 5 shows a layout and circuit diagram of the second word line noise reduction array of the present invention. The present embodiment is different from the first embodiment in that the WL ending at the boundary and the WL connected to the SWD array are repeated one by one at the boundary between the SWD array and the memory array.

  Also in this example, attention is paid to the connection relationship between the WL and the SWD row. Focusing on MC0 and MC1, which are two adjacent memory cells connected to DL0T, these MCs share one DLCT, but WL0 of WLs connected to these cells is in SWD column U. While connected, WL1 is connected to SWD row D. On the other hand, focusing on two adjacent memory cells MC2 and MC3 connected to DL0B, these also share one DLCT, but WL2 of WLs connected to these cells is in SWD column U. Whereas WL3 is connected to SWD row D. Therefore, in the layout of the word line noise reduction array of the second embodiment, WLs connected to two memory cells sharing the DLCT are connected to different SWD columns.

  Even in this example, when looking at the entire memory array, the pattern shown in Fig. 5 (a) is repeated vertically and horizontally, so half of the WLs connected to the MC connected to DL0T (WL0, WL4 in the figure) Connect to SWD row U and connect the other half (WL1, WL5 in the figure) to SWD row D. Also, half of the WLs (WL2, WL6 in the figure) connected to the MC connected to DL0B are connected to the SWD column U, and the other half (WL3, WL7 in the diagram) are connected to the SWD column D. . Therefore, half of the word lines connected to the memory cells connected to one data line are connected to the sub word driver column of one column, and the other half are connected to the sub word driver column of the other column. Yes. Further, the SWDs in the SWD row U are connected to a common VSS wiring VSSU. Similarly, the SWDs in the SWD row D are also connected to the common VSS wiring VSSD. By wiring VSS in this way, it is possible to cancel WL noise in VSS.

  Also in the second word line noise reduction array of the present invention, the positive and negative WL noise at the time of data line amplification can be canceled each other in the SWD, and the WL noise can be reduced. Therefore, it is possible to prevent the signal read by the sense amplifier from being deteriorated and to improve the reliability of the memory operation.

(Example 3)
FIG. 6 shows a layout and circuit diagram of the third word line noise reduction array of the present invention. This embodiment is different from Embodiments 1 and 2 in that the WL connected to the SWD row and the WL ending at the boundary portion are repeated four by four at the boundary portion between the SWD row and the memory array.

  Also in this example, attention is paid to the connection relationship between the WL and the SWD row. WL0 and WL1 connected to DL0T and connected to two adjacent memory cells MC0 and MC1 are both connected to the SWD row U. On the other hand, WL2 and WL3 connected to DL0B and connected to two adjacent memory cells MC2 and MC3 are also connected to SWD row U. Therefore, in this embodiment, the noise generated in WL0 and WL1 is canceled on VSSU by the noise generated in WL2 and WL3. Similarly, noise generated in WL4 and WL5 is canceled on VSSD by noise generated in WL6 and WL7.

  In this example as well, the pattern shown in Fig. 6 (a) is repeated vertically and horizontally when looking at the entire memory array, so half of the WLs connected to the MC connected to DL0T (WL0, WL1 in the figure) Connect to SWD row U and connect the other half (WL4, WL5 in the figure) to SWD row D. Also, half of the WLs connected to the MC connected to DL0B (WL2, WL3 in the figure) are connected to SWD row U, and the other half (WL6, WL7 in the figure) are connected to SWD row D. . Therefore, half of the word lines connected to the memory cells connected to one data line are connected to the sub word driver column of one column, and the other half are connected to the sub word driver column of the other column. Yes.

  Also in the third word line noise reduction array of the present invention, the positive and negative WL noise at the time of data line amplification can be canceled each other in the SWD, and the WL noise can be reduced. Therefore, it is possible to prevent the signal read by the sense amplifier from being deteriorated and to improve the reliability of the memory operation.

(Example 4)
FIG. 7 shows a layout and circuit diagram of the fourth word line noise reduction array of the present invention. In this embodiment, the boundary between the SWD column and the memory array is the same as in FIG. 11, but the direction of the data line contact DLCT of the memory cell arrays MC4, MC5, MC6, MC7 is changed and the diffusion layers are arranged in the DL direction. The difference from Embodiments 1, 2, and 3 is that memory cells are alternately connected to different DLs.

  WL0 and WL1 connected to DL0T and connected to two adjacent memory cells MC0 and MC1 are both connected to SWDA-U. On the other hand, WL2 and WL3 connected to DL0B and connected to two adjacent memory cells MC2 and MC3 are both connected to SWDA-D. MC4 and MC5, which are two adjacent memory cells, have an elliptical DLCT placed under the diffusion layer and connected to DL0B. WL4 and WL5 connected to these are connected to SWDA-U. is doing. Similarly, two adjacent memory cells MC6 and MC7 have an elliptical DLCT placed below the diffusion layer and connected to DL0T. WL6 and WL7 connected to these are connected to SWDA-U. Connected.

  Therefore, in this embodiment, the noise generated in WL0 and WL1 is canceled on VSSU by the noise generated in WL4 and WL5. Similarly, noise generated in WL2 and WL3 is canceled on VSSD by noise generated in WL6 and WL7.

  In this example as well, since the pattern shown in Fig. 7 (a) is repeated vertically and horizontally when looking at the entire memory array, half of the WLs connected to the MC connected to DL0T (WL0, WL1 in the figure) Connect to SWDA-U and connect the other half (WL6, WL7 in the figure) to SWDA-D. Also, half of the WLs connected to the MC connected to DL0B (WL4, WL5 in the figure) are connected to SWDA-U, and the other half (WL2, WL3 in the figure) are connected to SWDA-D. . Therefore, half of the word lines connected to the memory cells connected to one data line are connected to the sub word driver column of one column, and the other half are connected to the sub word driver column of the other column. Yes.

  Also in the fourth word line noise reduction array of the present invention, the positive and negative WL noise at the time of data line amplification can be canceled each other in the SWD, and the WL noise can be reduced. Therefore, it is possible to prevent the signal read by the sense amplifier from being deteriorated and to improve the reliability of the memory operation.

(Example 5)
This embodiment is a second sub word driver (SWD) for use in the word line noise reduction array of the present invention. Here, the case of combining with the first word line noise reduction array of the present invention is shown, but the present invention can be applied to other word line noise reduction arrays.

  In the SWD shown in FIG. 8, the MWLB in FIG. 3 is divided into MWLB0 and MWLB1, and the number of FX is reduced by half. If this method is used, the layout area of the SWD may be reduced. The SWD is arranged in two upper and lower stages, and VSS is divided into two parts, VSSU1 and VSSU2.

  When using such SWD, in order to cancel WL noise, for each VSSU, SWD corresponding to both WL connected to MC connected to DL0T and WL connected to MC connected to DL0B Need to be connected. That is, in FIG. 8, WL1 and WL5 are connected to the MC connected to DL0T as in FIG. WL2 and WL6 are connected to the MC connected to DL0B. In such a case, by connecting SWD1 to which WL1 is connected and SWD6 to which WL6 is connected to VSSU1, WL noise in these WLs can be canceled in VSSU1. Also, by connecting SWD2 to which WL2 is connected and SWD5 to which WL5 is connected to VSSU2, WL noise in these WLs can be canceled in VSSU2.

  Therefore, by using a combination of the sub-word driver of the present invention and the word line noise reduction array of the present invention, the positive and negative WL noise at the time of data line amplification can be canceled each other in the SWD, and the WL noise can be reduced. Therefore, it is possible to prevent the signal read by the sense amplifier from being deteriorated and to improve the reliability of the memory operation.

(Example 6)
This embodiment is a third sub word driver (SWD) for use in the word line noise reduction array of the present invention. Here, the case of combining with the first word line noise reduction array of the present invention is shown, but the present invention can be applied to other word line noise reduction arrays.

  In the SWD shown in FIG. 9, a transistor corresponding to MN2 of SWD1 in FIG. 8 is shared by SWD1 and SWD6, and the WLs are connected to each other. This method can reduce the number of transistors used in the SWD, thereby reducing the SWD layout area. The SWD is arranged in two upper and lower stages, and VSS is divided into two parts, VSSU1 and VSSU2, as in FIG.

  When using such SWD, in order to cancel WL noise, for each VSSU, SWD corresponding to both WL connected to MC connected to DL0T and WL connected to MC connected to DL0B Need to be connected. That is, in FIG. 9, WL1 and WL5 are connected to the MC connected to DL0T as in FIG. WL2 and WL6 are connected to the MC connected to DL0B. In such a case, by connecting SWD1 to which WL1 is connected and SWD6 to which WL6 is connected to VSSU1, WL noise in these WLs can be canceled in VSSU1. Also, by connecting SWD2 to which WL2 is connected and SWD5 to which WL5 is connected to VSSU2, WL noise in these WLs can be canceled in VSSU2.

Therefore, by using a combination of the sub-word driver of the present invention and the word line noise reduction array of the present invention, the positive and negative WL noise at the time of data line amplification can be canceled each other in the SWD, and the WL noise can be reduced. Therefore, it is possible to prevent deterioration of the signal read by the sense amplifier, and to improve the reliability of the memory operation.
As described above, the word line noise reduction array DRAM works in a direction in which positive and negative word line noises cancel each other out in the sub word driver when the data line is amplified regardless of the pattern of the signal output on the data line. Therefore, word line noise can be reduced. Therefore, it is possible to prevent the signal read by the sense amplifier from being deteriorated and to improve the reliability of the memory operation.

  Also, focusing on the amount of signal coming out of the memory cell, it is possible to accurately sense even a signal smaller than that of a memory array in which the coupling capacitance between the data line and the word line is poorly balanced. It is possible to widen the operation margin when the charge is not sufficiently obtained or when the charge accumulated in the memory cell capacitor is reduced by the leakage current. Therefore, the refresh characteristics of the DRAM can be improved by using the array of the present invention. In addition, the DRAM manufacturing process can be simplified.

It is a layout and circuit diagram of the first word line noise reduction array of the present invention. It is a block diagram of a DRAM chip. It is a circuit diagram of the 1st subword driver used for the word line noise reduction array of this invention. It is a figure which shows the principle of the noise reduction in the 1st word line noise reduction array of this invention. It is a layout and circuit diagram of the 2nd word line noise reduction array of this invention. It is a layout and circuit diagram of the 3rd word line noise reduction array of this invention. It is a layout and circuit diagram of the 4th word line noise reduction array of this invention. It is a circuit diagram of the 2nd subword driver used for the word line noise reduction array of this invention. It is a circuit diagram of the 3rd subword driver used for the word line noise reduction array of this invention. It is a layout and circuit diagram of a DRAM memory array examined prior to the present application. FIG. 11 is an enlarged view of the layout and circuit diagram of the memory cell of FIG. FIG. 12 is a cross-sectional view of a main part of the memory array of FIG. FIG. 11 is a diagram showing the principle of word line noise generation in the memory array of FIG. FIG. 11 is a circuit diagram and operation waveforms of a sense amplifier of the memory array of FIG.

Explanation of symbols

WL: Word line, SWD: Sub word driver, DL: Data line, SA: Sense amplifier, MC ... Memory cell, ACT ... Active region of MOS transistor, SNCT ... Storage node contact, DLCT ... Data line contact, TG ... Selection transistor, CS ... cell capacitor, PL ... plate, SN ... cell capacitor lower electrode, MWLB ... main word line, FX ... subword driver selection line, SHR ... shared SA selection line, CSP ... PMOS common source, CSN ... NMOS common source, BLEQ ... Data line equalize line, VBLR ... data line reference power supply, SIO, SIOB ... sub I / O line, M2, M3 ... wiring layer.

Claims (18)

A first data line and a second data line provided adjacent to each other;
A plurality of word lines intersecting the first and second data lines;
A plurality of memory cells;
A plurality of word drivers connected to the plurality of word lines;
A sense amplifier connected to the first and second data lines as a pair;
The memory cell is connected to one of the intersections of one word line and the first data line and the second data line of the plurality of word lines,
The plurality of word drivers connected to the plurality of word lines connected to the memory cells connected to the first data line are on the opposite side across the data line, approximately the same number,
A plurality of word drivers connected to a plurality of word lines connected to the memory cells connected to the second data line are located on the opposite side across the data line by approximately the same number. apparatus. In claim 1,
The first, second, third, and fourth intersections of the first, second, third, and fourth word lines, which are four adjacent word lines of the plurality of word lines, and the first data line, respectively. The fourth intersection,
If the intersections of the first, second, third, and fourth word lines and the second data line are the fifth, sixth, seventh, and eighth intersections, respectively,
A semiconductor device, wherein a memory cell is connected to the first, second, seventh, and eighth intersections. In claim 2,
First, second, third, and fourth word drivers are connected to the first, second, third, and fourth word lines, respectively.
The first and fourth word drivers are on the same side with respect to the first and second data lines,
The second and third word drivers are on the same side with respect to the first and second data lines,
The semiconductor device according to claim 1, wherein the first and fourth word drivers and the second and third word drivers are on opposite sides of the first and second data lines. In claim 2,
First, second, third, and fourth word drivers are connected to the first, second, third, and fourth word lines, respectively.
The first and third word drivers are on the same side with respect to the first and second data lines,
The second and fourth word drivers are on the same side with respect to the first and second data lines,
The semiconductor device according to claim 1, wherein the first and third word drivers and the second and fourth word drivers are on opposite sides of the first and second data lines. In claim 2,
First, second, third, and fourth word drivers are connected to the first, second, third, and fourth word lines, respectively.
A semiconductor device, wherein the first, second, third, and fourth word drivers are on the same side with respect to the first and second data lines. In claim 1,
The first, second, third, fourth, fifth, sixth, seventh, and eighth word lines, which are adjacent eight of the plurality of word lines, and the first data line The intersection points are the first, second, third, fourth, fifth, sixth, seventh, and eighth intersection points, respectively.
The intersections of the first, second, third, fourth, fifth, sixth, seventh, and eighth word lines and the second data line are defined as the ninth, tenth, eleventh, twelfth, 13th, 14th, 15th and 16th intersection points
Memory cells are connected to the first, second, seventh, eighth, eleventh, twelfth, thirteenth, and fourteenth intersection points,
The first, second, third, fourth, fifth, sixth, seventh, and eighth word lines are respectively connected to the first, second, third, fourth, fifth, sixth, seventh, An eighth word driver is connected, and the first, second, fifth and sixth word drivers are on the same side with respect to the first and second data lines;
The third, fourth, seventh, and eighth word drivers are on the same side of the first and second data lines;
The first, second, fifth, and sixth word drivers and the third, fourth, seventh, and eighth word drivers are opposite to each other across the first and second data lines. A semiconductor device. A first data line and a second data line provided adjacent to each other;
A plurality of word lines intersecting the first and second data lines;
A plurality of memory cells;
A plurality of word drivers connected to the plurality of word lines;
A sense amplifier connected to the first and second data lines as a pair;
The memory cell is connected to one of the intersections of one word line and the first data line and the second data line of the plurality of word lines,
The plurality of memory cells are connected to the first or second data line via a data line contact;
Among the plurality of memory cells, the first and second memory cells, which are adjacent two memory cells, are connected to the data line by a common data line contact,
The word driver connected to the word line connected to the first memory cell and the word driver connected to the word line connected to the second memory cell are opposite to each other across the data line. A semiconductor device. In claim 7,
The first, second, third, and fourth intersections of the first, second, third, and fourth word lines, which are four adjacent word lines of the plurality of word lines, and the first data line, respectively. The fourth intersection,
If the intersections of the first, second, third, and fourth word lines and the second data line are the fifth, sixth, seventh, and eighth intersections, respectively,
Memory cells are connected to the first, second, seventh, and eighth intersections,
A memory device connected to the first and second intersections shares a data line contact, and a memory cell connected to the seventh and eighth intersections shares a data line contact. In claim 8,
First, second, third, and fourth word drivers are connected to the first, second, third, and fourth word lines, respectively.
The first and fourth word drivers are on the same side with respect to the first and second data lines,
The second and third word drivers are on the same side with respect to the first and second data lines,
The semiconductor device according to claim 1, wherein the first and fourth word drivers and the second and third word drivers are on opposite sides of the first and second data lines. In claim 8,
First, second, third, and fourth word drivers are connected to the first, second, third, and fourth word lines, respectively.
The first and third word drivers are on the same side with respect to the first and second data lines,
The second and fourth word drivers are on the same side with respect to the first and second data lines,
The semiconductor device according to claim 1, wherein the first and third word drivers and the second and fourth word drivers are on opposite sides of the first and second data lines. A first data line and a second data line provided adjacent to each other;
A plurality of word lines intersecting the first and second data lines;
A plurality of memory cells;
A plurality of word drivers connected to the plurality of word lines;
A sense amplifier connected to the first and second data lines as a pair;
The memory cell is connected to one of the intersections of one word line and the first data line and the second data line of the plurality of word lines,
The memory cell comprises a switch MOSFET and an information storage capacitor.
The gate of the MOSFET is connected to the word line,
The first diffusion layer of the MOSFET is connected to one electrode of the information storage capacitor via a storage node contact,
A second diffusion layer of the MOSFET is connected to the first or second data line via a data line contact;
A second diffusion layer of the MOSFET included in two adjacent memory cells in the plurality of memory cells is connected to the data line by a common data line contact,
The plurality of word drivers connected to the plurality of word lines connected to the memory cells connected to the first data line are on the opposite side across the data line, approximately the same number,
A plurality of word drivers connected to a plurality of word lines connected to the memory cells connected to the second data line are located on the opposite side across the data line by approximately the same number. apparatus. In claim 11,
The first, second, third, and fourth intersections of the first, second, third, and fourth word lines, which are four adjacent word lines of the plurality of word lines, and the first data line, respectively. The fourth intersection,
If the intersections of the first, second, third, and fourth word lines and the second data line are the fifth, sixth, seventh, and eighth intersections, respectively,
Memory cells are connected to the first, second, seventh, and eighth intersections,
A second diffusion layer included in the memory cell connected to the first and second intersections shares a data line contact;
A semiconductor device, wherein a second diffusion layer included in a memory cell connected to the seventh and eighth intersections shares a data line contact. In claim 12,
First, second, third, and fourth word drivers are connected to the first, second, third, and fourth word lines, respectively.
The first and fourth word drivers are on the same side with respect to the first and second data lines,
The second and third word drivers are on the same side with respect to the first and second data lines,
The semiconductor device according to claim 1, wherein the first and fourth word drivers and the second and third word drivers are on opposite sides of the first and second data lines. In claim 12,
First, second, third, and fourth word drivers are connected to the first, second, third, and fourth word lines, respectively.
The first and third word drivers are on the same side with respect to the first and second data lines,
The second and fourth word drivers are on the same side with respect to the first and second data lines,
The semiconductor device according to claim 1, wherein the first and third word drivers and the second and fourth word drivers are on opposite sides of the first and second data lines. In claim 12,
First, second, third, and fourth word drivers are connected to the first, second, third, and fourth word lines, respectively.
A semiconductor device, wherein the first, second, third, and fourth word drivers are on the same side with respect to the first and second data lines. In claim 11,
The first, second, third, fourth, fifth, sixth, seventh, and eighth word lines, which are adjacent eight of the plurality of word lines, and the first data line The intersection points are the first, second, third, fourth, fifth, sixth, seventh, and eighth intersection points, respectively.
The intersections of the first, second, third, fourth, fifth, sixth, seventh, and eighth word lines and the second data line are defined as the ninth, tenth, eleventh, twelfth, 13th, 14th, 15th and 16th intersection points
Memory cells are connected to the first, second, seventh, eighth, eleventh, twelfth, thirteenth, and fourteenth intersection points,
A second diffusion layer included in the memory cell connected to the first and second intersections shares a data line contact;
A second diffusion layer included in a memory cell connected to the seventh and eighth intersections shares a data line contact;
A second diffusion layer included in a memory cell connected to the eleventh and twelfth intersections shares a data line contact;
A second diffusion layer included in a memory cell connected to the thirteenth and fourteenth intersections shares a data line contact;
The first, second, third, fourth, fifth, sixth, seventh, and eighth word lines are respectively connected to the first, second, third, fourth, fifth, sixth, seventh, An eighth word driver is connected, and the first, second, fifth and sixth word drivers are on the same side with respect to the first and second data lines;
The third, fourth, seventh, and eighth word drivers are on the same side of the first and second data lines;
The first, second, fifth, and sixth word drivers and the third, fourth, seventh, and eighth word drivers are opposite to each other across the first and second data lines. A semiconductor device. A first data line and a second data line provided adjacent to each other;
A plurality of word lines intersecting the first and second data lines;
A plurality of memory cells;
A plurality of word drivers connected to the plurality of word lines;
A sense amplifier connected to the first and second data lines as a pair;
The memory cell is connected to one of the intersections of one word line and the first data line and the second data line of the plurality of word lines,
The plurality of word drivers connected to the plurality of word lines connected to the memory cells connected to the first data line are on the opposite side across the data line, approximately the same number,
The plurality of word drivers connected to the plurality of word lines connected to the memory cells connected to the second data line are on the opposite side across the data line, approximately the same number,
Among the plurality of word drivers, word drivers on the same side with respect to the data line constitute first and second word driver columns, respectively.
The first and second word driver columns are respectively wired with first and second non-selection level power supply lines in order to give a non-selection level of the word line,
The first non-selection level power supply line is commonly connected to the word drivers in the first word driver row,
2. The semiconductor device according to claim 1, wherein the second non-selected level power supply line is commonly connected to the word drivers in the second word driver row. A first data line and a second data line provided adjacent to each other;
A plurality of word lines intersecting the first and second data lines;
A plurality of memory cells;
A plurality of word drivers connected to the plurality of word lines;
A sense amplifier connected to the first and second data lines as a pair;
The memory cell is connected to one of the intersections of one word line and the first data line and the second data line of the plurality of word lines,
The plurality of word drivers connected to the plurality of word lines connected to the memory cells connected to the first data line are on the opposite side across the data line, approximately the same number,
The plurality of word drivers connected to the plurality of word lines connected to the memory cells connected to the second data line are on the opposite side across the data line, approximately the same number,
Among the plurality of word drivers, word drivers on the same side with respect to the data line constitute first and second word driver columns, respectively.
In order to give a non-selection level of the word line to the first word driver column, first and second non-selection level power supply lines which are two non-selection level power supply lines are wired.
In order to give the non-selection level of the word line to the second word driver column, third and fourth non-selection level power supply lines which are two non-selection level power supply lines are wired,
The first, second, third, and fourth non-selection level power supply lines each include a word driver connected to a plurality of word lines connected to a memory cell connected to the first data line, and the second A semiconductor device characterized in that substantially the same number of word drivers connected to a plurality of word lines connected to memory cells connected to data lines are connected.

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