JPS601710B2 - semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a memory array in a semiconductor memory.

Conventional memory consists of one bit with one transistor,
For example, MOS (Me evil 1 10 phantom de 1 Semicon
The circuits shown in Figures 1 and 2 were used in memory.

That is, in FIG. 1, when reading out a memory cell MCo, for example, a word line Wo and another data line Do are connected.
At the same time, a pulse is applied to the dummy word line DW, belonging to
As read signals from memory cells MCo and DM,
The minute differential signal output appearing on the two data lines Do, Do is amplified by operating the preamplifier PAo by turning on the set signal Set of the preamplifier AAo, and is output to one of the data lines Do, Do. It detected the voltage that appeared and discriminated between information "1" and "0". The reason why differential signal output is generated here is as follows. Since the voltage stored in the capacitance Co of the dummy cell DM is set to approximately the middle of the voltages corresponding to the information "1" and "0" stored in the memory cell Co, the data line is The voltage that appears is approximately halfway between the data line voltages resulting from reading "1" and "0" from the memory cell. Therefore, the difference between this intermediate value and the "1" and "0" outputs becomes a differential signal output with different polarity.

Figure 2 shows a plurality of circuits shown in Figure 1 (for example, 6 here).
4) It is a diagram schematically showing a circuit in consideration of the geometrical arrangement when it is mounted in a BI chip and constitutes one memory.

In the figure, the white circles are memory cells, and the black circles are dummy cells.
For example, in order to take out the signal appearing on the data line Do as described above, turn on the transistor Qo according to the address signal, input the signal on the data line Do to the main amplifier MA, amplify it, and output the data. Remove it from the chip as a melon. Now, the drawbacks of such a configuration can be summarized as follows. In other words, ■Data lines Do, Do
Only one of the differential signals appearing in the main up MA
Since it is amplified by , it is inferior in terms of high speed. ■In order to extract one signal, electrical imbalance between P and Do tends to occur, causing malfunction. ■Because the data lines Do and Do, whose electrical characteristics should be balanced, are not mechanically close to each other in the chip, unbalanced noise easily couples to Do and Do, causing malfunctions when the preamplifier is turned on. It causes Due to these drawbacks, high speed and highly stable LSI
Memory design has traditionally had limitations. One object of the present invention is to provide a layout method between memory cells that allows for high integration. To this end, one embodiment of the present invention provides a method for connecting memory cells to two adjacent data lines in a dynamic random access memory by alternately connecting one data line every two memory cells. A highly integrated memory layout is achieved by connecting the memory to the memory.

This will be explained in detail in Examples below.

FIG. 3 shows an example of the circuit.

That is, the data line pair Do, where differential read signals appear,
Do are arranged close to each other in parallel as shown in the figure, and one each of the word lines (Wo to W63, DWo, DW,) and Do
, Do, a memory cell is connected to only one of the intersections. When reading a certain memory cell (for example, MC63), the data line (D
The dummy cells (D) connected to the data lines Do and Do are simultaneously read out, and the differential voltage appearing on the data lines Do and Do is effectively used by the preamplifier PAo. Further, the differential signal amplified by the preamplifier P is inputted to the differential amplifier MA through the transistor Qo by application of the address signal Ao which is the output of the decoder, and is amplified again by the lid operation. In this way, in the present invention, <Do, D
The electrical balance of o is not disturbed in any way. Fourth
The figure is a schematic diagram of a method of connecting memory cells (8 bits) while maintaining electrical balance between Do and Do. In the figure a,
b, c are Do, Do every 1st, 2nd, respectively,
This method connects memory cells every fourth. Figure 5a
, FIG. 6 is a silicon gate process using a silicon gate process.
This is an example of a layout that realizes c. Figure 5b is Figure 5a
It is a sectional view of the AA' section of. In the figure, a storage capacitor forming electrode CP made of polysilicon is used to form a storage capacity Co in a memory cell as shown in FIG. 4
00,41 Kawama is formed in the silicon substrate 600 and is a drain and source (or source and drain) for forming a transistor Q, and 420 corresponds to 4101.
This is a drain (or source) for forming Co.

The storage capacitor forming electrode Cp and the word lines W59, etc. are formed of polysilicon, and the data lines D, etc. are formed of aluminum.

The data line D, etc. and the word line W59, etc. are separated by an insulating film 200. Reference numeral 100 indicates a contact portion between the data lines Do, Do, etc. and the diffusion layer 400.

In N-channel MOS, the storage capacity Co is formed by cp
When a high voltage is applied to , the capacitance between the channel formed directly below and CP becomes Co.

To briefly explain the operation using FIG. 5, when a pulse voltage is applied to the word line, for example, W6o, the transistor Q (
(corresponding to Q in MCo in FIG. 1) is turned on, and the voltage recorded on Co is divided by the capacitance of data line Do and Co, and a voltage appears on Do. On the other hand, since the transistor Q does not exist on the data line Do paired with this, no output appears. The output appearing at Do is only the output from the dummy cell (not shown), as described above. As is clear from FIG. 5, the distance between the diffusion layers of the contact portions at Do and O can be increased due to the presence of the AI wiring in the middle. Therefore, there is an advantage that punch-through between Do and D can be avoided. Furthermore, another advantage of FIG. 3 is that the layout of the preamplifier PAo is easier than that of the slave. In other words, in the conventional Figures 1 and 2, it is necessary to lay out P, which occupies a much larger area than the memory cell and has a complicated circuit configuration, between Do and Do, which are laid out in a straight line with each other. However, considering the pitch of the data lines, this was extremely difficult. However, in Figure 3, there is a layout area margin that is approximately twice that of the subordinate in the data line pitch direction, so
Layout becomes extremely easy. Also preamplifier PA
o may be placed on the MA side as shown in FIG. 3, or on the other end (W63 side) of Do, Do.

By arranging P on the W63 side, control circuits that are relatively difficult to layout (P, Qo, etc.) will not be concentrated at one end, as shown in FIG. Depending on the case, preamplifiers may be arranged alternately on the MA side and the W63 side on the data line. As described above, according to the present invention, the degree of freedom in layout can be greatly increased. In addition, in FIGS. 5 and 6, the word line is made of poly-Si, but the word line is made of A
A similar layout is possible in the case of an I gate, and the same is true in the case of an AI gate.

Also, in this example, one bit is configured with one transistor, but in order to extract signals differentially from the data pair lines, a memory cell is connected only to one of the two intersections with the word line, and It is clear that all memories can be applied to 1 by applying the concept shown in FIGS. 3 and 4 using dummy cells.

In FIG. 3, CD and CD are common data lines for data writing and logical output. From the above, a memory with high speed and highly stable operation can be realized.

[Brief explanation of the drawing]

Figures 1 and 2 show a conventional memory configuration in which one bit is configured with one transistor, Figure 3 shows an embodiment of the present invention in which a read signal is output from only one side of a pair of data lines, and Figure 4 shows a memory configuration. 5 and 6 show an example of a layout using a Si gate as an example. Do, Do, D,...Data line, Wo/"W62...Word line, DWo, DW...Dummy cell word line, M
C. , M.C. ...Memory cell, DM. , D.M. ...Dummy cell, Co...Storage capacity, Q transistor in memory cell, WD...Word driver, Q〇,Q. ~Q3...data line selection transistor, Ao~A63...address signal, PAo~PA63...preamplifier, MA...main amplifier, Set...set signal, CP...C3
Electrode for formation. Figure 1 Figure 2 Figure 3 Figure 4 Figure 6 Figure 5

Claims (1)

[Claims] 1. In a semiconductor memory in which multiple memory cells are arranged in rows and columns, two adjacent data lines form one set, and between the two data lines of each set, there is a line corresponding to the intersection with each word line. A semiconductor memory characterized in that two memory cells are arranged alternately at each position.