JPS601711B2 - semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a memory array in a semiconductor memory.

Conventional memory consists of one bit with one transistor,
For example, MOS (Mene110 phantom de-Semicon
The circuits shown in Figures 1 and 2 were used in memory.

That is, in FIG. 1, when reading out a memory cell MCo, for example, a word line Wo and another data line Do are connected.
A pulse is simultaneously applied to the dummy word line DW, which belongs to the memory cells MCo and DM, and the minute differential signal output appearing on the two data lines Do, Do is sent as a read signal from the memory cells MCo and DM, to a set signal to the preamplifier P. By turning on Set, the preamplifier P is activated and amplified.
Information "1" and "0" were discriminated by detecting the voltage appearing on one of the data lines. The reason why the differential signal output occurs here is as follows. Since the voltage stored in the capacitor Co of the dummy cell DM is set to approximately the middle of the voltage corresponding to the information "1" and "0" stored in the memory cell Co, the data line is The voltage appearing on the memory cell “
The data line voltage is approximately halfway between the data line voltages when reading 1 and 0. Therefore, the difference between this intermediate value and the 1 and 0 outputs becomes a differential signal output with different polarity.

Figure 2 shows a plurality of circuits shown in Figure 1 (for example, 6 here).
4) is a diagram showing a circuit that takes into consideration the geometrical arrangement when a BI memory is configured in one chip.

In the figure, the white circles are memory cells, and the black circles are dummy cells.
For example, in order to take out the signal appearing on the data line Do as described above, turn on the transistor Qo according to the address signal, input the data Do signal to the main amplifier MA and amplify it, and output the data output Dout. and take it out of the chip. Now, the drawbacks of such a configuration can be summarized as follows. In other words, ■Data lines Do, D
Main amplifier MA outputs only one side of the differential signal appearing at
Since it is amplified by , it is inferior in terms of high speed. (2) Since one signal is taken out, electrical imbalance between Do and Do tends to occur, causing malfunction. ■Because the data lines Do and Do, whose electrical characteristics should be balanced, are not geometrically close to each other within the chip, unbalanced noise easily couples to Do and Do, which can cause malfunctions when the preamplifier is turned on. Cause. Due to these drawbacks, high speed and highly stable LS
I-memory designs have traditionally had limitations. One object of the present invention is to provide an amplifier circuit that can remove common mode noise that enters a common data line between a preamplifier and a main amplifier. One object of the present invention is to provide a readout circuit that does not require a reference voltage, as is the case when using a differential amplifier that uses a single output of a preamplifier as an input. One object of the present invention is to provide a memory read circuit that is simple and capable of high-speed operation.

To this end, an embodiment of the present invention connects the complementary outputs of the pre-sense amplifiers through column switches in the dynamic random access memory output circuit.
By supplying it to the main amplifier, high-speed and low-noise operation is possible.

This will be explained in detail in Examples below.

FIG. 3 shows an example of the circuit.

In other words, the data lines Do, D on which differential read signals appear
o are arranged close to each other in parallel as shown in the figure, and one each of the word lines (Wo to W63, DWo, DW.) and Do,
A memory cell is connected to only one of the intersections of Do. When reading a certain memory cell (for example, MC63), the data line (D
The dummy cells (DMo) connected to the data lines Do and 0o are simultaneously read out and the differential voltage appearing on the data lines Do and 0o is effectively used in the preamplifier PAo.
The differential signal amplified by the transistors Qo and Qo is applied to the address signal Ao which is the output of the decoder.
The signal is passed through and input to the amplifier MA in between, where it is amplified again by the hair movement. As described above, in the present invention, the electrical balance between Do and Do is not disturbed in any way as compared to the case of FIG. FIG. 4 is a schematic diagram of a method of connecting memory cells (8 bits) while maintaining electrical balance between Do and Do. In the figure, a, b, and c are placed every other Do and Do, respectively, and 2
In this method, memory cells are connected every four cells.
5A and 6 are layout examples for realizing FIGS. 4B and 4C using a silicon gate process. FIG. 5b is a cross-sectional view of section AA' in FIG. 5a. In the figure, a storage capacitor forming electrode CP made of polysilicon is used to form a storage capacity Co in a memory cell as shown in FIG. 400 and 410 are drains and sources (or sources and drains) formed in the silicon substrate 600 to form the transistor Q, and 420 is a drain (or source) to form Co in contrast to 410'. be.

The storage capacitor forming electrode Cp and the word lines W59, etc. are formed of polysilicon, and the data lines D, etc. are formed of aluminum. Data line D, etc. and word line W5
9 etc. are separated by an insulating film 200. Reference numeral 100 indicates a contact portion between the data lines Do, Do, etc. and the diffusion film 400.

In N-channel MOS, the storage capacity Co is formed by cp
When a high voltage is applied to , the capacitance between the channel formed directly below and CP becomes Co.

To briefly explain the operation using FIG. 5, when a pulse voltage is applied to the word line, for example, W6o, the transistor Q (
(corresponding to Q in MCo in Figure 1) is turned on, and the memory voltage of Co is divided by the capacitance of data line Do and Co.
A voltage will appear. On the other hand, since the transistor Q does not exist on the data line Do paired with this, no output appears. The output appearing at Do is only the output from the dummy cell (not shown), as described above. As is clear from Fig. 5, the distance between the diffusion layers of the contact portions at Do and D can be increased due to the presence of the AI wiring in the middle.Therefore, there is also the advantage that punch-through between Do and D can be avoided. Furthermore, another advantage of Fig. 3 is that the layout of the preamplifier PAo is easier than in the past.In other words, in the conventional Figs. In the middle of the memory cell, it was necessary to lay out a P cell that occupied a much larger area than the memory cell and had a more complex circuit configuration, which was extremely difficult considering the pitch of the data lines.However, in Figure 3, , in the data line pitch direction, there is a layout area that is approximately twice as large as that of the slave, making the layout extremely easy.Also, the preamplifier P
Ao may be placed on the MA side as shown in FIG. 3, or on Do, another machine on Do (W63 side).

By arranging P on the W63 side, control circuits that are relatively difficult to layout (P, Qo, etc.) will not be concentrated at one end, as shown in FIG. In some cases, preamplifiers can be alternately placed on the MA side and the W63 side on the data line. As described above, according to the present invention, the degree of freedom in layout can be greatly increased. In addition, in FIGS. 5 and 6, the word line is made of poly-Si, but the word line is made of A
The same layout is possible in the case of I, and the same machine can be used in the case of AI gate.

Also, in this example, one bit is configured with one transistor, but in order to extract the signal from the data pair line to the reed, the memory cell is connected only to one of the two points with the word line. It is clear that if the concept of FIGS. 3 and 4 using dummy cells is applied, it can be applied to all memory BIs.

In FIG. 8, CD and AD are common data lines for writing and outputting data. From the above, a memory with high speed and highly stable operation can be realized.

[Brief explanation of drawings]

Figures 1 and 2 show a conventional memory configuration in which one bit is configured with one transistor, Figure 3 shows an embodiment of the present invention in which a read signal is output from only one side of a pair of data lines, and Figure 4 shows a memory configuration. 5 and 6 show an example of a layout using a Si gate as an example. Do, Do, D,...data line, Wo/"W63/" word line, DWo, DW. ...Dummy cell word line, MC. , M.C. ...Memory cell, DMo, DM. ...Dummy cell, Co...Storage capacity, Q transistor in memory cell, WD...Word driver, Q〇,Q. ~Q3...Data line selection transistor, to ~A63...address signal, PAo~PA63...preamplifier, MA...main amplifier, Set...set signal, CP...Co
Electrode for formation. Figure 1 Figure 2 Figure 3 Figure 4 Figure 6 Figure 5

Claims (1)

[Claims] 1. A first data line to which a plurality of memory cells are coupled, a second data line to which a plurality of memory cells are coupled and paired with the first data line, and the first data line. means for applying a reference potential to the second data line, a preamplifier coupled to the second data line and forming a pair of complementary outputs in response to a comparison between the potential applied from the memory cell and the reference potential; A semiconductor memory comprising a capacitor and one transistor, the main amplifier comprising a differential amplifier having a pair of inputs receiving the complementary outputs. memory. 2. The semiconductor memory according to claim 1, wherein the first and second data lines are arranged in parallel in adjacent columns.