JPS6010393B2 - semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a memory array in a semiconductor memory IJI.

Conventional memory consists of one bit made up of one transistor.

For example, MOS (Metal-Odde-Semic-
OM skin tor) memory employed circuits like those shown in Figures 1 and 2. That is, in FIG. 1, when reading out the memory cell MCo, for example, the word line Wo
and dummy word lines DW, belonging to other data lines Do.
A pulse is simultaneously applied to the two data lines Do and Do as read signals from the memory cells MCo and DM.
By turning on the set signal Set of the preamplifier PAo, the preamplifier P is operated and amplified, and the voltage appearing on either the data line of Do or Do is detected. Information “1”, “0”
The reason why a differential signal output is generated here is as follows.The voltage stored in the capacitor Co of the dummy cell DM is the same as the information "1" stored in the memory cell Co. , is set to approximately the middle of the voltage corresponding to "0", so the voltage appearing on the data line from reading the dummy cell is approximately midway between the data line voltage resulting from reading "1" and "0" from the memory cell. Therefore, the difference between this intermediate value and the "1" and "0" outputs becomes a differential signal output with different polarity.

Figure 2 shows a plurality of circuits shown in Figure 1 (for example, 6 here).
4) It is a diagram schematically showing a circuit in consideration of the geometrical arrangement when it is mounted in a BI chip and constitutes one memory.

In the figure, the white circles are memory cells, and the black circles are dummy cells.
For example, to take out the signal appearing on the data line Do as described above, turn on the transistor Qo by the address signal Ao, input the signal on the data line Do to the main amplifier MA, amplify it, and output the data. Take it out of the chip as a Do pile. Now, the drawbacks of such a configuration can be summarized as follows. That is, ■Data line Do, 0
Main amplifier M outputs only one side of the differential signal appearing at
Since it is amplified by A, it is inferior in terms of high speed. ■In order to extract one signal, the Do and Do errors tend to occur, causing malfunctions.

■The data lines Do, Do whose electrical characteristics should be balanced are
Due to the lack of geometrical proximity within the chip, Do,D
Unbalanced noise is likely to couple to the preamplifier, causing malfunction when the preamplifier is turned on. Due to these drawbacks,
Conventionally, there were limits to the design of high-speed, highly stable UR1 memory. Accordingly, one object of the present invention is to provide a sense amplifier layout in which the output circuitry can be distributed. One object of the present invention is to provide a sense amplifier layout that allows effective use of chip area.

One object of the present invention is to provide a circuit technology suitable for a semiconductor memory that compares and compares adjacent data lines.

To this end, one embodiment of the present invention uses a pre-sense amplifier as a memory.

By arranging the mat at one end opposite to the column switch, that is, the data line selection transistor, a data line layout with a high density pitch is made possible. FIG. 7 shows a layout of a sense amplifier according to an embodiment of the present invention.

In the same figure, MA is the main amplifier, CD is the common data line, CS is the column switch or data line selection transistor, D and D are complementary data lines, and MM is the common data line.
is a memory mat, that is, a cell array, and PA is a preamplifier. This will be explained in detail in Examples below.

FIG. 8 shows an example of the circuit.

That is, the data line pair Do, where differential read signals appear,
Do are arranged close to each other in parallel as shown in the figure, and one each of the word lines Wo to W, DWo, DW, and Do, D
A memory cell is connected to only one of the intersections of o. When reading a certain memory cell (for example, an MC line), the dummy cell DMo connected to the data line Do to which that cell is not connected is read out at the same time, and the differential voltage appearing on the data lines Do and Do is sent to the preamplifier PA.
Make effective use of o. The differential signal amplified by the preamplifier P passes through transistors Qo and Qo by application of an address signal Ao, which is the output of the decoder, and is input to the differential amplifier MA, where it is differentially amplified again. As described above, in the present invention, unlike the case of FIG. 2, the electrical balance between Do and Do is not disturbed in any way. Figure 4 shows D
A memory cell that maintains the electrical balance of o and Do (
8 bits) is a schematic diagram of a connection method. In the figure, a, b, and c are Do and D. In this method, memory cells are connected every other memory cell, every second memory cell, and every fourth memory cell. 5A and 6 are layout examples for realizing FIGS. 4B and 4C using a silicon gate process. FIG. 5b is a cross-sectional view of section AA' in FIG. 5a.

In the figure, a storage capacitor forming electrode cp made of polysilicon
is for forming the storage capacitance Co in the memory cell as shown in FIG. 400 and 410 are drains and sources (or sources and drains) formed in the silicon substrate 600 to form the transistor Q;
20 corresponds to 410 and is a drain (or source) for forming Co.

The storage capacitor forming electrode Cp and the word line W stage, W59, etc. are formed of polysilicon, and the data line D, etc. are formed of aluminum. Data line D, etc. and word line W5
9 etc. are separated from the insulating film 20. 100 is a contact portion between the data lines Do, Do, etc. and the diffusion layer 400.

In N-channel MOS, the storage capacity Co is formed by cp
When a high voltage is applied to the capacitive force between the channel and cp formed directly below it.

becomes. To briefly explain the operation using FIG. 5, when a pulse voltage is applied to the word line, for example, W6o, the transistor Q (corresponding to Q in MCo in FIG. 1) turns on, and C
The storage voltage of o is divided by the capacitance of data line Do and Co, and a voltage appears on Do. On the other hand, since the transistor Q does not exist on the data line Do paired with this, no output appears. The output appearing at Do is only the output from the dummy cell (not shown), as described above. As is clear from FIG. 5, the distance between the diffusion layers of the contact portions Do and D can be increased due to the presence of the AI wiring in the middle. Therefore, there is an advantage that punch-through between Do and D can be avoided. Furthermore, another advantage of FIG. 3 is that the layout for the preamplifier P is easier than that for the slave. In other words, in the conventional figures 1 and 2,
Between Do and Do, which are laid out in a straight line with each other, P must be laid out, which occupies a much larger area than the memory cell and has a more complex circuit configuration, and it is extremely difficult to consider the pitch of the data lines. It was difficult.
However, in FIG. 3, there is an area margin approximately twice as large as that of the conventional layout in the data line pitch direction, making the layout extremely easy. Further, the preamplifier PAo may be placed on the MA side as shown in FIG. 3, or on the other end (W63 side) of Do, Do.

By arranging P on the W63 side, control circuits whose layout is relatively difficult (PAo, Qo, etc.) are not concentrated only at one end, as shown in FIG. Depending on the case, preamplifiers may be arranged alternately on the MA side and the W63 side on the data line. As described above, according to the present invention, the degree of freedom in layout can be greatly increased. Also, Figures 5 and 6
Although the figure shows an example in which the word line is made of poly-Si, the layout can be similarly performed if the word line is made of AI, and the same applies to the case of an AI gate.

Also, in this example, one bit is configured with one transistor, but in order to extract signals differentially from the data pair lines, a memory cell is connected only to one of the two intersections with the word line, and It is clear that all memories can be applied to 1 by applying the concept shown in FIGS. 3 and 4 using dummy cells.

In FIG. 3, CD and CD are common data lines for writing and outputting data. From the above, a memory with high speed and highly stable operation can be realized.

[Brief explanation of drawings]

Figures 1 and 2 show a conventional memory configuration in which one bit is configured with one transistor, Figure 3 shows an embodiment of the present invention in which a read signal is output from only one side of a pair of data lines, and Figure 4 shows a memory configuration. 5 and 6 show an example of a layout using a Si gate as an example, and FIG. 7 shows a layout of a sense amplifier according to an embodiment of the present invention. Do, Do, D,: Data line, Wo………W62
: Word line, DW of DW, : Word line of dummy cell,
MCo, MC,: memory cell, DMo, DM,: dummy cell, Co: storage capacity, transistor in Q memory cell,
WD: Word driver, Q. ,Q. ~Q3: Data line selection transistor, Ao~A
Mother: Address signal, PAo to PA63: Preamplifier, M
A: Main amplifier, Set: Set signal, CP: C. Electrode for formation. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1 a memory matrix in which a plurality of semiconductor memory cells are arranged in rows and columns; a word line running in the vertical direction and a data line running in the horizontal direction to be electrically coupled to the memory cells in the matrix; A sense sensor that uses two of the lines as a pair and reads the stored signal of the memory cell appearing on the other data line using the potential of one data line as a reference.
and an amplifier, wherein the pairs of data lines are arranged in parallel in adjacent columns, and the sense amplifier is arranged at an end of the memory matrix opposite to the data line selection transistor. A semiconductor memory characterized by comprising: