JPS6252954A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize high integrity as a whole by a method wherein a part which performs high speed logic operation and a buffer circuit part which needs a larger occupying area are separately composed and they are overlapped and unified. CONSTITUTION:A logic circuit in a GaAs integrated circuit chip 11 contains an output buffer which has the minimum driving capability required for exchanging signals with the external circuits. An output buffer circuit 5 and an input buffer circuit 16, which practice exchange of signals between the logic circuit in the GaAs integrated circuit chip and other circuits, are formed in an Si integrated circuit chip 12. The GaAs integrated circuit chip 11 and the Si integrated circuit chip 12 are overlapped and unified by a face-down flip chip method. The I/O terminals of the complex semiconductor device unified like this are the I/O pads 17 formed on the Si integrated circuit chip 12. The exchange of signals between the GaAs integrated circuit chip 11 and the Si integrated circuit chip 12 is performed through solder bumps 14.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device mounted with high-speed logic elements.

(Technical Background of the Invention and Problems Thereof) Recently, there has been remarkable progress in research and development regarding high-speed logic operation of semiconductor devices. In particular, G has higher electron mobility than Si.
Development of high-speed logic integrated circuits using compound semiconductors such as aAs is active. MESFET using GaAs)-
High-speed memory and gate arrays based on IEMT are attracting particular attention.

However, in such GaAs integrated circuits, although the logic circuit itself has a very high operating speed, has low power consumption, and can be integrated, it is difficult to actually configure a system by combining multiple integrated circuit chips. In many cases, these characteristics cannot be fully utilized. This is inside the integrated circuit.
In order to exchange signals with external circuits, an output buffer 7 with a driving capacity several times larger than that when driving internal wiring is used.
This is because it requires a circuit. For example, GaAs MESF
In an integrated circuit using ET, the output impedance of the internal logic gate is about 10Ω, but the output impedance of the output buffer 7 for exchanging signals with the outside is usually designed to be lowered to about 50Ω. Also, the existing T
When combined with the TL or ECL family, a logic level conversion circuit is required within the output buffer 7 circuit to match the logic levels. An output buffer 7 with an output impedance of 50 Ω requires a larger area than an internal gate with an output impedance of the order of 10 Ω,
The area occupied by the output buffer group at the periphery of the chip becomes almost the same as the area occupied by the internal gate group, which impedes higher integration of GaAs integrated circuits. Further, since the output buffer consumes a large amount of power, the advantage of low power consumption of the GaAs single product circuit is hardly utilized. Furthermore, since the thermal conductivity of GaAs is lower than that of Sl, it is difficult to dissipate heat during mounting. Also, since the signal @ delay in the output buffer is large, GaA
The high speed of the s logic gate will not be fully utilized.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device with a composite structure that solves the above-mentioned problems.

[Summary of the invention]

A semiconductor device according to the present invention includes a first integrated circuit chip that integrates a logic circuit that operates at high speed, and a second integrated circuit chip that integrates a buffer circuit that transmits and receives signals between the logic circuit and other circuits. , are constructed by stacking and integrating.

〔Effect of the invention〕

According to the present invention, by configuring a part that performs high-speed logic operations and a buffer circuit part that requires a large area as separate parts, and then stacking them and integrating them, even the buffer circuit can be integrated into one chip. Overall, higher integration can be achieved than in the case of In this case, the second integrated circuit chip on which the buffer circuit is integrated is, for example, an 81
If it is formed from a substrate, heat dissipation is also improved. Also the second
By including a logic level converting circuit in the buffer circuit formed on the integrated circuit chip, various changes can be made by simply changing the design of the second integrated circuit chip without changing the design of the logic circuit of the first integrated circuit chip. system.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a composite semiconductor device according to one embodiment, in which (a) is a plan view and (b) is a side view. Reference numeral 11 denotes a GaAs integrated circuit chip (first integrated circuit chip) on which a logic circuit that performs high-speed logic operation is integrated. The internal gate 13 of this GaAs integrated circuit chip 11 is composed of, for example, a MESFET having high input/output impedance. The logic circuit within this GaAs single product circuit chip 11 includes an output buffer having a minimum driving ability for exchanging signals with the outside. 12 is a Si integrated circuit chip (second integrated circuit chip), which includes an output buffer 7 circuit 15 and an input buffer circuit for exchanging signals between the logic circuit in the GaAs integrated circuit chip and other circuits. ? A circuit 16 is formed. These buffer circuits 15.16
has a level conversion function for matching the input/output logic level of the logic circuit within the GaAs integrated circuit chip to the logic level of the external circuit to which it is connected.

GaAs integrated circuit chip 11 and Si integrated circuit chip 12
are stacked and integrated using a face-down seven-lip chip method. The input/output terminals of the composite semiconductor device thus integrated are input/output pads 17 formed on the Si integrated circuit chip 12. Signals are exchanged between the GaAs integrated circuit chip 11 and the Si integrated circuit chip 12 via solder bumps 14.

FIG. 2 shows a specific circuit example in which the output buffer 7 circuit 15 of the Si integrated circuit chip 12 is designed to the ECL level.

The GaAs integrated circuit chip 11 is a MESFE as described above.
It is an integrated high-speed logic circuit using T, and its output is sent to the output buffer 7 circuit 15 on the 5i integrated circuit chip 12.
The signal is converted to an ECL logic level and supplied to the outside. The same goes for the input section; an external input signal having an ECL logic level is converted to the logic level of the GaAs logic circuit by the input buffer circuit 16 on the Si integrated circuit chip 12, and the internal logic of the GaAs integrated circuit chip 11 is converted to the logic level of the GaAs logic circuit. It will be entered into the gate.

According to this embodiment, the buffer circuit portion, which occupies a large area, is separated from a GaAs integrated circuit chip that performs high-speed logic operation and is configured on a separate chip, and these chips are stacked and integrated, so that the elements can be integrated. High integration can be achieved with the same effect as three-dimensional integration. Furthermore, the output buffer circuit needs to have a sufficiently large driving capacity corresponding to the number of connected fan-outs, and this portion requires larger power consumption than the portion that performs logic operations. In this example, by integrating the buffer circuit section with high power consumption on the Si substrate with high thermal conductivity, the heat dissipation of the entire system is improved while maintaining the low power consumption of the logic circuit section. can be taken as a thing.

Furthermore, the environment in which high-speed logic integrated circuits are used is not necessarily limited to logic integrated circuits of the same type, but also ECL.

TTL, CMO8I! Connection with product circuits, etc. is often required. In the case of this embodiment, by providing a logic level conversion function to the buffer circuit configured as an S1 integrated circuit, only the design of the Si integrated circuit can be changed without changing the design of the GaAs integrated circuit in which high-speed logic circuits are integrated. This makes it possible to support various external circuits. This is a significant advantage considering that GaAs integrated circuits still have lower yields than 81 integrated circuits.

Further, in this embodiment, the Ga, As integrated circuit chip and the 81 integrated circuit chip are integrated by a flip-chip method. For example, such integration is possible by wire bonding, but in this case, signal waveform distortion may occur due to the inductance component of the wire during high-speed operation.
Wires may cause crosstalk. This embodiment does not have such problems and requires less footprint for interconnections.

Note that the present invention is not limited to the above-mentioned embodiments,
Various modifications can be made without departing from the spirit of the invention. For example, other compound semiconductor materials such as InP can be used for the first integrated circuit chip, and the second
Similar effects can be obtained when a semiconductor material having a higher thermal conductivity than that of the first integrated circuit chip is used in addition to the Si substrate as the integrated circuit chip.

[Brief explanation of drawings]

1A and 1B are a plan view and a side view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the internal circuit configuration thereof. 11...GaAs integrated circuit chip (first integrated circuit chip), 12...81 integrated circuit chip (second tJ,
integrated circuit chip), 13... internal logic gate, 14...
・Solder bump, 15... Output buffer 7 circuit, 16...
- Input buffer circuit, 17... input/output pad. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (5)

[Claims] (1) A first integrated circuit chip that integrates a logic circuit that operates at high speed and a second integrated circuit chip that integrates a buffer circuit that exchanges signals between the logic circuit and other circuits are stacked and integrated. A semiconductor device characterized by comprising: (2) The semiconductor device according to claim 1, wherein the first integrated circuit chip is constructed using a GaAs substrate. (3) The semiconductor device according to claim 1, wherein the second integrated circuit chip is constructed using a Si substrate. (4) The buffer circuit of the second integrated circuit chip includes a level conversion circuit that matches the logic level of another circuit to which the logic circuit of the first integrated circuit chip is connected. Semiconductor equipment. (5) The semiconductor device according to claim 1, wherein the first integrated circuit chip and the second integrated circuit chip are integrated by a face-down flip-chip method.