JPH01220859A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To keep the ratio of effective channel width constant, and enable the constituting of a circuit with stable characteristics by forming the P-type diffusion layer and the N-type diffusion layer of a P-channel MOS transistor and an N-channel MOS transistor which have a common gate' by using masks having the same channel width. CONSTITUTION:A P-type diffusion layer 2 of a P-channel MOS transistor Q1 and N-type diffusion layers 3 of two N-channel MOS transistors Q2, Q3 are formed by using the respective masks having the same channel width, and a gate 1 is formed across the diffusion layers 2, 3. In the N-type diffusion layer 3, two gates 1 are arranged parallel, and two N-channel MOS transistors Q1, Q2 connected in parallel are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a CMOS (complementary insulated gate transistor) structure.

[Conventional technology]

A conventional semiconductor integrated circuit having a CMOS structure will be explained using an inverter circuit as an example. Figure 3 (a) and (b) are CM
1 is a circuit diagram of an inverter having an OS structure and a plan view of its structure; FIG.

This inverter circuit includes a P-channel MOS transistor Q7 and an N-channel MO3! - transistor Q8, each having a common gate and drain, the source of the P-channel MOS transistor Q7 is used as a power supply, and the source of the N-channel MOS transistor Q8 is grounded.

And P Channel Neno LI'PJ! OS transistor Q
7 has a P-type diffusion layer 12, and N-channel MOS transistor Q8 has an N-type diffusion layer 13, and a gate 11 is formed across these diffusion layers.

Here, the effective channel width (Weff) in these MOS transistors is determined by the channel width (Wsask) on the mask, which is usually shown by the solid line in the figure, and the reduction in channel width due to penetration of the field into the diffusion layer (ΔW). . That is, Weff=Wmask 2・ΔW
The following formula holds true.

Therefore, when designing a mask, Wmask is determined by taking into consideration the channel width decrease ΔW described above in advance.
For example, a P-channel MOS transistor Q7 with an effective channel width WPeff of 5 μm and an effective channel width WN
N-channel O3 transistor Q8 of efflOμm
When configuring the inverter circuit shown in FIG. 3(a), if the standard value of the decrease ΔW is 0.3 μm, and the channel width WP+ask on the mask of the P-channel MOS transistor Q7 is 5.6 μm, the N-channel MOS transistor Q7 is Interval O3
Channel width WNmas on the mask of transistor Q8
k will be designed to be 10.6 μm.

[Problem to be solved by the invention]

In the conventional CMO3 structure semiconductor integrated circuit described above, the actual decrease ΔW is 0.1. cI
It has a width of about m to 0.5 μm. Therefore, the effective channel width WPeff of the P-channel MO3I transistor Q7 is 4.6 μm to 5.4 μm, and the effective channel width WNe of the N-channel O3 transistor Q8 is 4.6 μm to 5.4 μm.
ff produces a variation in the range of 9.6 p m - 10.4 p m. In other words, in the conventional CMOS inverter mask design method, the ratio of both effective channel widths (WP
eff/WN eff) is 4.6/9.6 to 5.4 compared to the standard value of 0.5, depending on the variation of the decrease ΔW.
/10.4.

Therefore, there is a problem in that the characteristics of the inverter circuit change in accordance with changes in this ratio, making it impossible to construct a stable inverter circuit.

The present invention is a CMO that maintains the ratio of the effective channel widths of a P-channel MOS transistor and an N-channel MO3I-transistor constant, making it possible to configure a circuit with stable characteristics.
The purpose is to provide a semiconductor integrated circuit with three structures.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention is a P-channel MOS having a common gate in a CMO3 structure semiconductor integrated circuit.
A structure in which the P-type diffusion layer and the N-type diffusion layer of the transistor and the N-channel MOS transistor are formed using masks with the same channel width, and the MOS transistors of each channel are connected in series or in parallel in multiple stages to set their effective channel width. There is.

[Effect]

In the above-described structure, since each of the P-type and N-type diffusion layers is formed using a mask having the same channel width, it is possible to always keep the ratio of their effective channel widths constant due to the decrease in channel width.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention, and FIG.
is a circuit diagram, and FIG. In addition,
Here, in order to make the explanation easier to understand, P
The effective channel width of each channel and N-channel MOS transistor is WP eff = 5 μm,
A case is illustrated in which an inverter is configured with WN eff = 10 am.

In this embodiment, the inverter circuit is constructed using a P-channel MOS transistor Q with an effective channel width Weff-5 μm.
l, and two N-channel inter-channel O3 transistors Q2.1 with an effective channel width Weff=5 μm. It consists of Q3.

That is, the P-type diffusion layer 2 of the P-channel MOS transistor Q1 and the two N-channel MO3I-transistors Q2.
．． The N-type diffusion layers 3 of Q3 are formed using masks having the same channel width, and the gate 1 is formed across these diffusion layers 2.3.

In the N-type diffusion layer 3, two N-channel inter-O3 transistors Q2 . Q3 is formed, and the overall effective channel width WNeff is set to 10 μm.

According to this configuration, if the standard value of the decrease ΔW with respect to the channel width of the mask is 0.3 μm, the CMO of FIG.
The S inverter is composed of a P-channel MOS transistor with a channel width of 5.6 μm on a mask and two N-channel inter-channel O3 transistors connected in parallel with a channel width of 5.6 μm on the mask.

Therefore, the ratio of the effective channel width of the P-channel MOS transistor to the effective channel width of the N-channel O3 transistor is expressed by the formula (5,6-ΔW)/2 (5,6-ΔW), and the decrease ΔW is fixed at 0.5 regardless of the value of . In other words, P channel.

The effective channel width ratio of each N-channel MOS transistor can always be kept constant, and an 0M03 circuit with stable characteristics can be constructed.

FIG. 2 shows a second embodiment of the present invention, in which (a) is a circuit diagram of an inverter circuit, and (b) is a plan view of the structure.

In this embodiment, as in the first embodiment, the effective channel widths of the P-channel and N-channel MOS transistors are WPeff=5 pm and WNeff=1, respectively.
In this example, which illustrates a case where an inverter is configured with a width of 0t1m, the effective channel width W eff = 10μ
m two P-channel MOS transistors Q4. Q5
P with an effective channel width Weff = 5 μm by connecting them in series.
A channel MOS transistor is connected to an N-channel MOS transistor Q6 having an effective channel width WN eff =10 μm to form an inverter circuit.

Therefore, in this example as well, the P type diffusion layer 2 and the N type diffusion layer 3 are formed using masks having the same channel width.

Here, if the standard value of the decrease ΔW is 0.3 μm, the ratio of the effective channel widths of the P-channel MOS transistor and the N-channel MOS transistor in the inverter circuit is (10,6-2·6w) 12. / (10,6-2・
ΔW), and the decrease is 0 regardless of the value of ΔW.
It is fixed at 5.

Note that the present invention is applicable not only to the above-mentioned inverter circuit (, C
It is clear that the present invention can be applied to any circuit composed of MO3.

〔Effect of the invention〕

As explained above, in the present invention, the P-type diffusion layer and the N-type diffusion layer of the P-channel MOS transistor and the N-channel MOS transistor having a common gate are formed using masks with the same channel width. The effective channel width ratio can be kept constant regardless of the variation in the decrease ΔW from the mask channel width, which has the effect of stabilizing the characteristics of the CMO8 circuit.

[Brief explanation of the drawing]

FIG. 1 shows a first embodiment of the present invention, FIG. 1(a) is a circuit diagram, FIG.
3 shows a conventional CMOS inverter circuit, FIG. 3(a) is a circuit diagram, FIG. 3(b) is a planar structural diagram, and FIG. is a plan view of the structure. 1.11...Gate, 2.12...P-type diffusion layer, 3
．． 13...N type diffusion layer. Figure 1 (a) (b) Figure 2 Figure 3

Claims (1)

[Claims] 1. P-channel MOS transistor and N-channel M
In a semiconductor integrated circuit with a CMOS structure having an OS transistor, a P-channel MOS with a common gate
The P-type diffusion layer and the N-type diffusion layer of the transistor and the N-channel MOS transistor are formed using masks with the same channel width, and the MOS transistors of each channel are connected in series or in parallel in multiple stages to set their effective channel width. Features of semiconductor integrated circuits.