JPS61260668A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61260668A
JPS61260668A JP60102856A JP10285685A JPS61260668A JP S61260668 A JPS61260668 A JP S61260668A JP 60102856 A JP60102856 A JP 60102856A JP 10285685 A JP10285685 A JP 10285685A JP S61260668 A JPS61260668 A JP S61260668A
Authority
JP
Japan
Prior art keywords
mos
transistor
circuit
mos transistor
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60102856A
Other languages
Japanese (ja)
Inventor
Yoshifumi Yamazaki
嘉文 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP60102856A priority Critical patent/JPS61260668A/en
Publication of JPS61260668A publication Critical patent/JPS61260668A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the degree of integration structurally, and to simplify a manufacturing process by forming a complementary type field-effect type transistor in two layers or multilayers and shaping a circuit in three dimensions. CONSTITUTION:A thin-film transistor is prepared onto an N-MOS formed to a P well, and a P-MOS is shaped, thus allowing the sharing of a gate section 3. Since a gate section 8 is shared and drain in the N-MOS and an electrode 11 for a drain section in the P-MOS are made common, an inverter can be shaped easily by constituting a transistor consisting of two layers. An electrode not made common on a pattern can be extracted by extending a diffusion layer source in the transistor N-MOS as a lower section. The same can also be applied to a NAND circuit and a NOR circuit.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に半導体装置の構造に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a semiconductor device.

〔従来の技術〕[Conventional technology]

従来の半導体装置の構造、特に集積回路では、第1図の
ように平面状に素子を配列させ素子や素子間の線巾を縮
小することにより微細化が行なわれている。このような
微細化が進むにつれて有効な点がある一方では弊害もあ
る。
Conventional semiconductor device structures, particularly integrated circuits, are miniaturized by arranging elements in a plane as shown in FIG. 1 and reducing the line width between the elements and the elements. As such miniaturization progresses, while there are advantages, there are also disadvantages.

例えば集積回路の製造工程ではステッパを用いて解像度
を上げているが、より微細化するのに伴い、光の波動性
による回折効果による解像度の低下を避けられない。士
た素子間分離においても現在MOS型集積回路CMO8
−IC)の製造工程で主流である選択酸化による素子間
分離を用いた場合、微細化が進むにつれてリース・ドレ
イン間耐圧が低下するなど、ある程度以上の微細化によ
る半導体装置の萬集積化には限界があるという問題点が
あった。
For example, in the manufacturing process of integrated circuits, steppers are used to increase the resolution, but as devices become smaller, the resolution inevitably deteriorates due to the diffraction effect caused by the wave nature of light. Currently, MOS type integrated circuit CMO8 is also used for isolation between elements.
- When using isolation between elements by selective oxidation, which is the mainstream in the manufacturing process of ICs, the breakdown voltage between the lease and drain decreases as the size of the device becomes smaller. The problem was that there were limits.

〔目的〕〔the purpose〕

本発明はこのような問題点を解決するもので、その目的
とするところは構造的な集積度の向上と製造工程の簡素
化を提供することにある。
The present invention is intended to solve these problems, and its purpose is to improve the degree of structural integration and simplify the manufacturing process.

〔概要〕〔overview〕

この半導体装置の特徴は相補型電界効果型トランジスタ
を二層あるいは多)−にして立体的に回路を構成するこ
とにより電極部を共用あるいは共通にしたことにある。
The feature of this semiconductor device is that complementary field effect transistors are formed in two or more layers to form a three-dimensional circuit, thereby making the electrode portions common or common.

〔実施例〕〔Example〕

第2図に本発明の基本構造を示す。Pwellに形成さ
れたN−MOS(1,2,3で構成〕上に薄膜トランジ
スタ(TPT)(3,5,6で構成)を作成しP−MO
Sを構成することによりゲート部分(3)を共用するこ
とが可能である。第2図の実際の回路構成を第5図に示
す。第6図はインバータを構成しておりゲート部(8)
を共用し、かつN−MOSのドレインとP−MOSのド
レイン部の電極(11)を共通としているため、第2図
のように二層のトランジスタを構成することにより容易
にインバータが構成できる。パターン上では共通としな
い電極は第4図のように、下になるトランジスタ(N−
MOS)の拡散層(ソース〕を広げて吸り出すことがで
きる。
FIG. 2 shows the basic structure of the present invention. A thin film transistor (TPT) (consisting of 3, 5, 6) is created on the N-MOS (consisting of 1, 2, 3) formed in Pwell, and P-MO
By configuring S, it is possible to share the gate portion (3). The actual circuit configuration of FIG. 2 is shown in FIG. Figure 6 shows the gate part (8) that constitutes the inverter.
Since the N-MOS drain and the P-MOS drain part electrode (11) are common, an inverter can be easily constructed by constructing a two-layer transistor as shown in FIG. As shown in Figure 4, the electrodes that are not common on the pattern are connected to the lower transistor (N-
It can be sucked out by expanding the diffusion layer (source) of the MOS.

同様′VC第5図のNAIJD回路、第6図ノNOI’
を回路にも適用することができる。@5図のトランジス
タい)とトランジスタ(3)のゲー) (a) 、 ト
ランジスタ(2)とトランジスタ(4)のゲート(0)
はそれぞれ共通のゲートとして構成することができる。
Similarly 'VC NAIJD circuit in Figure 5, NOI in Figure 6'
can also be applied to circuits. @5 The gate of transistor (2) and the gate of transistor (3) in Figure 5) (a), the gate (0) of transistor (2) and transistor (4)
can be configured as a common gate.

実際の断面図を第7図に示す。トランジスタ(1)及び
(2)のドレイン部を共通とし、かつ、トランジスタ(
3)のドレイン部の電極を共用することができる。図で
は簡易的に配線を示しである。
An actual cross-sectional view is shown in FIG. The drain parts of transistors (1) and (2) are common, and the transistor (
The electrode of the drain part of 3) can be shared. The diagram simply shows the wiring.

またこの図ではトランジスタは直列(異なるゲートが拡
散層をはさむ形)に配列された状態を示しているが、第
8図に並列(異なるゲー′トが隣接する状態〕に配列し
たときの配線全1紹易的に示す。
In addition, this figure shows the transistors arranged in series (different gates sandwiching the diffusion layer), but Figure 8 shows the entire wiring when they are arranged in parallel (different gates are adjacent to each other). 1 A simple introduction.

第8図を第5図と対応させると、トランジスタ(5)の
ソースとトランジスタ(4)のドレインを共通にするこ
とができる。
When FIG. 8 is made to correspond to FIG. 5, the source of the transistor (5) and the drain of the transistor (4) can be made common.

第6図はNOR回路であるが、第5図と同様にトランジ
スタい)とトランジスタ(4〕のゲート(b)トランジ
スタ(2)とトランジスタ(3〕のゲート(a)はそれ
ぞれ共通にすることができる。また断面図についてはN
AND回路(第5図〕の構成よシ配線を入れ換えること
によりNORが構成できる。
Figure 6 is a NOR circuit, but as in Figure 5, the gates (b) of transistors (2) and (4) and the gates (a) of transistors (2) and (3) can be made common to each other. You can also see N for cross-sectional views.
A NOR can be constructed by replacing the wiring in the configuration of the AND circuit (FIG. 5).

〔効果〕〔effect〕

以上述べたように、本発明によれば従来2つの領域(W
eii構造〕を必要としていたものを立体的にトランジ
スタを構成することによシ高集積化がより促進させるこ
とが可能である。またこのような構造にすることによシ
、ラッチアップなどWellが隣接していたことによる
弊害をなくすことができる。さらにP−Well 、N
−WalNを形成する必要がないため工程の簡素化する
ことが可能である。P−MOSをTFTで構成するので
、多結晶シリコン、非晶質シリコンなどを用いれば、よ
り低消費電力を実現することが可能であるなどの効果を
有するものである。
As described above, according to the present invention, two areas (W
By configuring transistors three-dimensionally, it is possible to further promote high integration even though transistors that require a three-dimensional structure (eii structure). Further, by adopting such a structure, it is possible to eliminate problems such as latch-up caused by adjacent wells. Furthermore, P-Well, N
- Since there is no need to form WalN, the process can be simplified. Since the P-MOS is composed of TFTs, it is possible to achieve lower power consumption by using polycrystalline silicon, amorphous silicon, or the like.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来用いられているMO8構造を表わす図であ
る。第2図は本発明における基本構造を表わす図である
。第3図は第2図の回路的構成を表わす図である。また
第4図は第2図のパターン例を表わす図である。第5図
はNAND回路図及び第6図は1JOR回路図を表し、
第7図、第8図はNAN11回路の実施例を表わす図で
ある。図中の番号は以下のとおしです。 第1図 1・・・P−あるいはN″”Well 2・・・P“あるいはN+拡散層 3・・・ゲート 4・・・絶縁膜 第2図 1・・・半導体基板 2・・・N′″拡散層 3・・・ゲート電極 4・・・絶縁膜 5・・・P+拡散層 6・・・N−拡散層 第3図及び第4図 8・・・ゲート入力 ?・・・電源(VDD) 10・・・電源(Vss) 11・・・出力 第5〜第8図 1及び2・・・Pチャンネルトランジスタ3及び4・・
・Nチャンネルトランジスタa及びb・・・入力 C・・・出力 e・・・電源(VDD) f・・・電源(VSS) 以   上
FIG. 1 is a diagram showing a conventionally used MO8 structure. FIG. 2 is a diagram showing the basic structure of the present invention. FIG. 3 is a diagram showing the circuit configuration of FIG. 2. Further, FIG. 4 is a diagram showing an example of the pattern shown in FIG. 2. Figure 5 shows the NAND circuit diagram and Figure 6 shows the 1JOR circuit diagram.
FIGS. 7 and 8 are diagrams showing embodiments of the NAN11 circuit. The numbers in the diagram are as follows. Fig. 1 1... P- or N'' Well 2... P'' or N+ diffusion layer 3... Gate 4... Insulating film Fig. 2 1... Semiconductor substrate 2... N' ``Diffusion layer 3... Gate electrode 4... Insulating film 5... P+ diffusion layer 6... N- diffusion layer Figures 3 and 4 8... Gate input? ... Power supply (VDD) 10... Power supply (Vss) 11... Outputs 5 to 8 Figures 1 and 2... P channel transistors 3 and 4...
・N-channel transistors a and b...Input C...Output e...Power supply (VDD) f...Power supply (VSS) Above

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に作成された第1のMOSトランジスタと
前記第1のMOSトランジスタと相補であり、前記第1
のMOSトランジスタと積層構造を成す第2のMOSト
ランジスタから成り、前記第1、第2のMOSトランジ
スタがゲートを共通にし、かつ、前記第1のMOSトラ
ンジスタの拡散領域(ソースあるいはドレイン)上に前
記第2のMOSトランジスタの拡散領域が形成された構
造をもつ前記第1、第2のMOSトランジスタ対より構
成された相補電界効果型MOSトランジスタの集積回路
において前記第1、第2のMOSトランジスタ対を用い
て、INVERTER回路、NAND回路、NOR回路
を構成したことを特徴とする半導体装置。
A first MOS transistor formed on a semiconductor substrate is complementary to the first MOS transistor, and the first MOS transistor is complementary to the first MOS transistor.
MOS transistor and a second MOS transistor forming a laminated structure, the first and second MOS transistors share a gate, and the diffusion region (source or drain) of the first MOS transistor is In an integrated circuit of complementary field effect MOS transistors, the first and second MOS transistor pairs are configured to have a structure in which a diffusion region of the second MOS transistor is formed. 1. A semiconductor device characterized in that an INVERTER circuit, a NAND circuit, and a NOR circuit are constructed using the above-described semiconductor device.
JP60102856A 1985-05-15 1985-05-15 Semiconductor device Pending JPS61260668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60102856A JPS61260668A (en) 1985-05-15 1985-05-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60102856A JPS61260668A (en) 1985-05-15 1985-05-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61260668A true JPS61260668A (en) 1986-11-18

Family

ID=14338564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60102856A Pending JPS61260668A (en) 1985-05-15 1985-05-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61260668A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0375226A2 (en) * 1988-12-21 1990-06-27 Texas Instruments Incorporated An seu hardened memory cell
EP0516335A2 (en) * 1991-05-31 1992-12-02 AT&T Corp. Fabrication method in vertical transistor integration
JPH05274899A (en) * 1991-10-14 1993-10-22 Samsung Electron Co Ltd Use semiconductor integrated circuit for memory with built-in test circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0375226A2 (en) * 1988-12-21 1990-06-27 Texas Instruments Incorporated An seu hardened memory cell
EP0516335A2 (en) * 1991-05-31 1992-12-02 AT&T Corp. Fabrication method in vertical transistor integration
JPH05274899A (en) * 1991-10-14 1993-10-22 Samsung Electron Co Ltd Use semiconductor integrated circuit for memory with built-in test circuit

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