JPS61260668A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the degree of integration structurally, and to simplify a manufacturing process by forming a complementary type field-effect type transistor in two layers or multilayers and shaping a circuit in three dimensions. CONSTITUTION:A thin-film transistor is prepared onto an N-MOS formed to a P well, and a P-MOS is shaped, thus allowing the sharing of a gate section 3. Since a gate section 8 is shared and drain in the N-MOS and an electrode 11 for a drain section in the P-MOS are made common, an inverter can be shaped easily by constituting a transistor consisting of two layers. An electrode not made common on a pattern can be extracted by extending a diffusion layer source in the transistor N-MOS as a lower section. The same can also be applied to a NAND circuit and a NOR circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a semiconductor device.

[Conventional technology]

Conventional semiconductor device structures, particularly integrated circuits, are miniaturized by arranging elements in a plane as shown in FIG. 1 and reducing the line width between the elements and the elements. As such miniaturization progresses, while there are advantages, there are also disadvantages.

For example, in the manufacturing process of integrated circuits, steppers are used to increase the resolution, but as devices become smaller, the resolution inevitably deteriorates due to the diffraction effect caused by the wave nature of light. Currently, MOS type integrated circuit CMO8 is also used for isolation between elements.
- When using isolation between elements by selective oxidation, which is the mainstream in the manufacturing process of ICs, the breakdown voltage between the lease and drain decreases as the size of the device becomes smaller. The problem was that there were limits.

〔the purpose〕

The present invention is intended to solve these problems, and its purpose is to improve the degree of structural integration and simplify the manufacturing process.

〔overview〕

The feature of this semiconductor device is that complementary field effect transistors are formed in two or more layers to form a three-dimensional circuit, thereby making the electrode portions common or common.

〔Example〕

FIG. 2 shows the basic structure of the present invention. A thin film transistor (TPT) (consisting of 3, 5, 6) is created on the N-MOS (consisting of 1, 2, 3) formed in Pwell, and P-MO
By configuring S, it is possible to share the gate portion (3). The actual circuit configuration of FIG. 2 is shown in FIG. Figure 6 shows the gate part (8) that constitutes the inverter.
Since the N-MOS drain and the P-MOS drain part electrode (11) are common, an inverter can be easily constructed by constructing a two-layer transistor as shown in FIG. As shown in Figure 4, the electrodes that are not common on the pattern are connected to the lower transistor (N-
It can be sucked out by expanding the diffusion layer (source) of the MOS.

Similarly 'VC NAIJD circuit in Figure 5, NOI in Figure 6'
can also be applied to circuits. @5 The gate of transistor (2) and the gate of transistor (3) in Figure 5) (a), the gate (0) of transistor (2) and transistor (4)
can be configured as a common gate.

An actual cross-sectional view is shown in FIG. The drain parts of transistors (1) and (2) are common, and the transistor (
The electrode of the drain part of 3) can be shared. The diagram simply shows the wiring.

In addition, this figure shows the transistors arranged in series (different gates sandwiching the diffusion layer), but Figure 8 shows the entire wiring when they are arranged in parallel (different gates are adjacent to each other). 1 A simple introduction.

When FIG. 8 is made to correspond to FIG. 5, the source of the transistor (5) and the drain of the transistor (4) can be made common.

Figure 6 is a NOR circuit, but as in Figure 5, the gates (b) of transistors (2) and (4) and the gates (a) of transistors (2) and (3) can be made common to each other. You can also see N for cross-sectional views.
A NOR can be constructed by replacing the wiring in the configuration of the AND circuit (FIG. 5).

〔effect〕

As described above, according to the present invention, two areas (W
By configuring transistors three-dimensionally, it is possible to further promote high integration even though transistors that require a three-dimensional structure (eii structure). Further, by adopting such a structure, it is possible to eliminate problems such as latch-up caused by adjacent wells. Furthermore, P-Well, N
- Since there is no need to form WalN, the process can be simplified. Since the P-MOS is composed of TFTs, it is possible to achieve lower power consumption by using polycrystalline silicon, amorphous silicon, or the like.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventionally used MO8 structure. FIG. 2 is a diagram showing the basic structure of the present invention. FIG. 3 is a diagram showing the circuit configuration of FIG. 2. Further, FIG. 4 is a diagram showing an example of the pattern shown in FIG. 2. Figure 5 shows the NAND circuit diagram and Figure 6 shows the 1JOR circuit diagram.
FIGS. 7 and 8 are diagrams showing embodiments of the NAN11 circuit. The numbers in the diagram are as follows. Fig. 1 1... P- or N'' Well 2... P'' or N+ diffusion layer 3... Gate 4... Insulating film Fig. 2 1... Semiconductor substrate 2... N' ``Diffusion layer 3... Gate electrode 4... Insulating film 5... P+ diffusion layer 6... N- diffusion layer Figures 3 and 4 8... Gate input? ... Power supply (VDD) 10... Power supply (Vss) 11... Outputs 5 to 8 Figures 1 and 2... P channel transistors 3 and 4...
・N-channel transistors a and b...Input C...Output e...Power supply (VDD) f...Power supply (VSS) Above

Claims (1)

[Claims] A first MOS transistor formed on a semiconductor substrate is complementary to the first MOS transistor, and the first MOS transistor is complementary to the first MOS transistor.
MOS transistor and a second MOS transistor forming a laminated structure, the first and second MOS transistors share a gate, and the diffusion region (source or drain) of the first MOS transistor is In an integrated circuit of complementary field effect MOS transistors, the first and second MOS transistor pairs are configured to have a structure in which a diffusion region of the second MOS transistor is formed. 1. A semiconductor device characterized in that an INVERTER circuit, a NAND circuit, and a NOR circuit are constructed using the above-described semiconductor device.