JPS6350850Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a master slice type integrated circuit device.

In recent years, the use of IC in communication devices and computers has progressed, and this
Master slice type integrated circuit devices are often used for IC implementation. In a master slice integrated circuit device, MOS transistors are arranged regularly on a semiconductor substrate, and their source and drain contact holes and gate polysilicon contact holes are arranged on lattices called X and Y lattices, which are perpendicular to the sides of the chip. A circuit is realized by placing an aluminum conductive film only on this lattice.

FIG. 1 is a plan view of an example of a conventional CMOS type master slice.

A p-well layer 2 is formed on an n-type silicon substrate 1, a thin gate oxide film 10 is formed, gate polysilicon layers 3a, 3b and a feedthrough polysilicon layer 3c are formed, and an n ⁺ source/drain layer 4 is formed. , n ⁺ contact layer 7 for applying substrate voltage, p ⁺
This is accomplished by forming a source/drain layer 6, a contact hole 5 for applying a p ⁺ substrate voltage, and a contact hole 8, and then forming an aluminum conductive film 9.

In the following description, for the sake of simplicity, the equivalent layout diagram of FIG. 2, which is a simplified representation of FIG. 1, will be used.

FIG. 3a is a block diagram of an example of a dynamic flip-flop circuit, and FIG. 3b is a layout diagram when the circuit of FIG. 3a is realized using the master slice of FIG. 2.

In FIG. 3b, thick lines indicate aluminum connections. If this type of connection is made, the gate polysilicon layer shown by X and Y will be wasted, and 12 transistors will be used instead of 8 transistors. As described above, the conventional CMOS type master slice type integrated circuit device has a drawback of poor cell utilization.

The present invention eliminates the above drawbacks and provides a master slice type integrated circuit device with high cell utilization.

The integrated circuit device of the present invention includes two second conductivity type MOS transistors connected in series, each of which has three second conductivity type regions provided in parallel at regular intervals on a first conductivity type semiconductor substrate as source and drain regions. and,
two first conductivity type MOSs connected in series with three first conductivity type regions provided in parallel at regular intervals in a second conductivity type well provided next to the MOS transistor as source and drain regions; In the integrated circuit device including the transistor, the first
A gate polysilicon layer constituting one gate of the conductivity type MOS transistor and one gate of the second conductivity type MOS transistor are connected to each other.
A common gate polysilicon layer is formed which is terminated with two contact holes, and the other gate of each of the first conductivity type MOS transistor and the second conductivity type MOS transistor is terminated with two contact holes. one of the contact holes in each of the two independent gate polysilicon layers is at a constant angle with a straight line connecting the two contact holes in the common gate polysilicon layer. The first contact hole is located on the Y lattice, which is one straight line intersecting at the gate polysilicon layer, and the other contact hole is located on the same Y lattice as each of the two contact holes in the gate polysilicon layer.

Embodiments of the present invention will be described with reference to the drawings.

FIG. 4 is a plan view of an embodiment of the present invention.

A p-well 2 is provided in an n-type silicon substrate 1, three p-regions 6a to 6c are provided at regular intervals in a region adjacent to the p-well 2, and thin gate oxide films 10c and 10d are provided in regions at these intervals. . p-well 2
Three n-type regions 4a to 4c are also provided at regular intervals within the interior, and a thin gate oxide film 10 is formed in the areas at these intervals.
a and 10b are provided. A contact layer 7 for applying an n ⁺ type substrate voltage is provided on the substrate 1 and a contact layer 5 for applying a p ⁺ type substrate voltage is provided in the well 2 . Cover the substrate surface other than the gate area with a thick field oxide film. Deposit polysilicon and selectively remove it to form gates.
Polysilicon layers 3a, 3b, 3b' and field-through polysilicon layer 3c are formed. What is important here is that the polysilicon layer 3a is connected to the gate oxide films 10a and 10c to form a common gate polysilicon layer, which terminates in the contact hole 8, and is connected to the polysilicon layer 3b through the gate oxide films 10a and 10c. 3b' passes over the gate oxide films 10b and 10d, and forms gate polysilicon layers independently, each terminating in a contact hole 8, and the outside of the gate polysilicon layers 3b and 3b'. The contact holes are on the same Y lattice as the contact holes in the common gate polysilicon layer 3a, and the contact holes inside the gate polysilicon layers 3b, 3b' are on the same Y lattice. Contact holes in the gate polysilicon layers 10a, 10b, 10b' and the feedthrough polysilicon layer are formed by covering these polysilicon layers with an oxide film and then etching the oxide film. At this time, contact holes for p ⁺ regions 6a to 6c and n ⁺ regions 4a to 4c are also formed. As a result, a series-connected p-channel MOS transistor is formed in the substrate region, with the n ⁺ regions 6a to 6c serving as source/drain regions and the gate/polysilicon layers 3a and 3b' serving as gates. n-channel type MOS in which the n ⁺ regions 4a to 4c are source and drain regions, and the gate polysilicon layers 3a and 3b are gates
A transistor is configured. Finally, the V _DD line 9a and the V _SS line 9c are formed using an aluminum conductive film, etc.
A master slice type integrated circuit according to the present invention is obtained.

To simplify the explanation, the explanation will be made using the equivalent layout diagram of FIG. 5, which is a simplified representation of FIG. 4.

The contact holes in the gate polysilicon layers 3b and 3b' are on the same Y lattice 11b, and the contact holes in the gate polysilicon layers 3b and 3a and 3b' and 3a are on the same Y lattice 11c and 11a.

Next, an application example of the integrated circuit device of the present invention will be explained.

FIG. 6 is a layout diagram when the circuit shown in FIG. 3a is realized using an embodiment of the present invention.

In FIG. 6, thick lines indicate connections. use
There are eight MOS transistors. Figures 3 and 6
As is clear from a comparison with the figure, if the integrated circuit device of the present invention is used, MOS transistors are not wasted, so the cell utilization rate is improved.

As explained above, the present invention has the effect of increasing the cell utilization rate by dividing the gate polysilicon layer into a common part and an independent part.

[Brief explanation of the drawing]

Figure 1 is a plan view of an example of a conventional CMOS type master slice, Figure 2 is an equivalent layout diagram of Figure 1, Figure 3a is a circuit diagram of a dynamic flip-flop circuit, and Figure 3b is a diagram of Figure 2. A layout diagram when the circuit of FIG. 3a is realized using the master slice shown in FIG. 4, and FIG. 4 is a plan view of an embodiment of the present invention.
5 is an equivalent layout diagram of FIG. 4, and FIG. 6 is a layout diagram when the circuit shown in FIG. 3a is realized using an embodiment of the present invention. 1...n-type silicon substrate, 2...p-well, 3
a, 3b, 3b'...gate polysilicon layer, 3
c...Feedthrough polysilicon layer, 4...
n ⁺ source/drain layer, 5...p ⁺ contact layer for applying substrate voltage, 6...p ⁺ source/drain layer,
7...n ⁺ contact layer for applying substrate voltage, 8...
Contact hole, 9...Aluminum conductive film, 10
...Thin gate oxide film, 11...Y lattice.

Claims (1)

[Scope of utility model registration request] Two second conductivity type semiconductor substrates connected in series with three second conductivity type regions provided in parallel at regular intervals on a first conductivity type semiconductor substrate serving as source and drain regions.
a MOS transistor, and two series-connected MOS transistors whose source and drain regions are three first conductivity type regions provided in parallel at regular intervals in a second conductivity type well provided next to the MOS transistor. In an integrated circuit device including a single conductivity type MOS transistor, two gate polysilicon layers constituting one gate of the first conductivity type MOS transistor and one gate of the second conductivity type MOS transistor are connected. The first conductivity type MOS transistor and the second conductivity type MOS transistor form a common gate polysilicon layer terminated with a contact hole.
The other remaining gate of each of the MOS transistors is an independent gate polysilicon layer terminated with two contact holes, and one of the contact holes of each of the two independent gate polysilicon layers is The other contact hole is located on a Y lattice, which is a straight line that intersects at a constant angle with a straight line connecting the two contact holes in the common gate polysilicon layer, and the other contact hole An integrated circuit device, characterized in that the integrated circuit device is on the same Y grid as each of the contact holes.