WO2004013909A1

WO2004013909A1 - Semiconductor integrated circuit incorporating memory

Info

Publication number: WO2004013909A1
Application number: PCT/JP2002/007889
Authority: WO
Inventors: Keinosuke Toriyama; Masatoshi Hasegawa; Yuji Yokoyama
Original assignee: Hitachi, Ltd.
Priority date: 2002-08-02
Filing date: 2002-08-02
Publication date: 2004-02-12
Also published as: JPWO2004013909A1; JP4450380B2

Abstract

A semiconductor integrated circuit incorporating a memory in which a power supply generating circuit for memory and a memory circuit except the power supply generating circuit are previously designed as individual macro cells at the time of development. At the time of developing a hybrid logic/memory LSI, the number of memory macro cells to be mounted is determined in order to attain a desired storage capacity, and the memory macro cells are arranged on a chip such that the word lines are directed in the same direction. Furthermore, a macro cell including the power supply generating circuit is arranged at the end of a chip as a cell common to the plurality of memory macro cells.

Description

Description Semiconductor integrated circuits with built-in memory

The present invention relates to a technology that is effective when used in a semiconductor integrated circuit with a built-in memory in which a logic circuit and a memory circuit are provided on a single semiconductor chip (hereinafter referred to as a logic-memory integrated LSI). . Background art

Conventionally, as a method of developing a logic-memory hybrid LSI that requires a memory with a large storage capacity, a memory power supply generation circuit test together with a so-called memory circuit consisting of peripheral circuits such as a memory array and decoder with a predetermined storage capacity There is a method of designing an LSI by designing what is called a memory macro cell including a circuit and mounting the required number of memory macro cells (for example, Japanese Patent Application Laid-Open No. H11-110963, 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 to 1 should be obtained, such as those described in Japanese Patent Application Laid-Open No. H10-65124.

By adopting such a design method, it is easy to design a logic-memory embedded LSI. Note that the memory power supply generation circuit uses a voltage higher than the power supply voltage VDD, such as the word line selection voltage, the data line precharge voltage, the substrate voltage of the memory cell, and the reference voltage used to generate these voltages. This is a circuit that generates a voltage lower than the potential VSS.

However, in the above-mentioned design method, it is easy to secure the necessary storage capacity.However, there are a plurality of power supply circuits and test circuits for memory that only need one chip. Therefore, the chip area becomes unnecessarily large and the power consumption also increases. Regarding power consumption, power consumption during standby is a particular problem.

Also, a power supply circuit for memory is provided for each memory macro cell. In this case, a plurality of memory power generation circuits are distributed on the chip, and the oscillator circuits as clock generation circuits in each power supply circuit operate independently, thus simulating circuit operation. This makes it difficult to perform operations, and may cause undesired situations such as instability due to interference.

Further, if a plurality of power supply circuits for memory are dispersed on a chip, the reference voltages generated by the reference voltage circuits in each power supply circuit for memory are shifted from each other due to manufacturing variations. It became clear that there was a problem that the operation of the system could not be expected.

An object of the present invention is to provide a semiconductor integrated circuit with a built-in memory having a small chip area and low power consumption.

Another object of the present invention is to provide a semiconductor integrated circuit with a built-in memory that can easily simulate a circuit operation, does not become unstable, and can perform a desired operation on the entire chip. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The outline of a typical invention disclosed in the present application is briefly described as follows.

That is, when developing a semiconductor integrated circuit with a built-in memory, the power supply circuit for the memory and the memory circuit excluding this power supply circuit are designed as separate macro cells in advance, and The number of memory macrocells to be mounted is determined so that the storage capacity can be obtained, these are arranged side by side on the chip, and the macrocell including the power generation circuit is one or two common to these memory macrocells. It is arranged at the end of the chip as individual cells.

Here, preferably, the memory macro cells are connected to each other by word lines. In the same direction. When two power supply macrocells are used, the power supply macrocells are arranged on the upper, lower, left and right sides of the memory macrocell row arranged as described above. Further, the power supply macrocell may be provided with a common dest circuit for a plurality of memory macrocells.

According to the above-described means, a common power supply macrocell is provided for a plurality of memory macrocells, and the voltage generated there is supplied to the memory macrocell. Therefore, a power supply circuit is provided for each memory macrocell. In addition to a smaller chip area than conventional methods, the power consumption of the entire chip can be reduced. In addition, since there is only one power supply circuit and the same voltage is supplied to each memory macro cell, it is easy to simulate the circuit operation, and the operation does not become unstable due to interference of signals from a large number of oscillators. There is no danger that the generated voltage will fluctuate and the entire chip will not perform the desired operation.

In addition, a wiring (hereinafter, referred to as a memory power supply wiring) for supplying a voltage generated by the power generation circuit from the macro cell including the power generation circuit to the memory macro cell and a wiring for supplying a signal output from the test circuit (hereinafter, referred to as a memory power supply wiring). , DFT signal wiring) are arranged in a region where a guard ring provided around the chip is formed in order to prevent intrusion of moisture and the like. At this time, preferably, the wiring for supplying the reference voltage is arranged so as to be surrounded by power supply wiring, DFT signal wiring, and the like arranged in the guard ring region.

When a memory power generation circuit and a test circuit are provided in common for a plurality of memory cells, the wiring that supplies the voltage and signals generated by these circuits must be connected to the memory macrocells and logic circuits in the conventional general design method. The signal line area may be narrowed because it runs above the ground.However, by arranging it in the guarding area, it is possible to avoid the area where the original signal line is arranged from being narrowed. it can. It is also possible to shield by surrounding the wiring supplying the reference voltage with the wiring used for the guard ring. The reference voltage can be stabilized without providing a separate shield structure. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing an embodiment of a logic / memory embedded LSI to which the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration example of a memory macro cell.

FIG. 3 is an explanatory diagram showing a first embodiment of a layout configuration of a logic / memory mixed LSI to which the present invention is applied.

FIG. 4 is an explanatory diagram showing a second embodiment of a layout structure of a logical memory embedded LSI to which the present invention is applied.

FIG. 5 is an explanatory diagram showing an example of how to increase the storage capacity in the logic / memory embedded LSI of the second embodiment.

FIG. 6 is an explanatory diagram showing a third embodiment of a layout structure of a logical memory embedded LSI to which the present invention is applied.

FIG. 7 is an explanatory diagram showing an example of how to increase the storage capacity in the logical-memory embedded LSI of the third embodiment.

FIG. 8 is an explanatory diagram showing a fourth embodiment of a layout structure of a logical memory embedded LSI to which the present invention is applied.

FIG. 9 is an explanatory diagram showing an embodiment in which the present invention is applied to a multichip module.

FIG. 10 is an enlarged cross-sectional plan view showing a part (corner of a chip) of a guard ring region where a wiring for supplying a voltage from a power supply & DFT macrocell to a memory macrocell is formed.

FIG. 11 is a sectional side view showing a sectional structure of the guard ring region. BEST MODE FOR CARRYING OUT THE INVENTION

Figure 1 shows a block diagram of an embodiment of a logic-memory mixed SI to which the present invention is applied. 2 shows the configuration of the network.

In FIG. 1, reference numeral 100 denotes a semiconductor chip such as single-crystal silicon, 200 denotes a logic circuit portion formed on the semiconductor chip, 300A to 300H denote memory macro cells, and 400 denotes a power generation circuit and a test circuit. Power supply & DFT macro cell. As shown in FIG. 1, in this embodiment, a voltage and a signal generated by one common power supply & D FT macro cell 400 are supplied to a plurality of memory macro cells 300 A to 300 H, respectively. Is done. The power supply & DFT macro cell 400 includes a test circuit 410, a reference voltage circuit 420, and a? ? It comprises a generating circuit 430 and a VBB generating circuit 440.

Each of the memory macro cells 300 A to 30 OH has one or more memory mats in which a plurality of memory cells are arranged in a matrix, and each memory mat is commonly connected to a selection terminal of memory cells in the same row. The plurality of read lines (WL) are arranged in parallel with each other, and the data input / output terminals of the memory cells in the same column are connected in common, and the plurality of data lines (DL) extend in a direction orthogonal to the read lines. Are arranged in parallel with each other. Since the memory circuit having such a configuration is the same as a general-purpose SRAM or DRAM memory mat, illustration and detailed description are omitted.

The VPP generation circuit 430 is composed of a charge pump circuit, etc., and generates a boosted lead line selection voltage VPP such as 3.3 V based on an external power supply voltage VDD such as 1.5 V. A plurality of VPP voltage generation circuits 431, a VPP oscillator 432 that generates a clock signal required for the boost operation of the VPP voltage generation circuit 431, and a VP generated by the VPP voltage generation circuit 431 By comparing the P voltage with a reference voltage VREF, such as 0.75 V, supplied from the reference voltage circuit 420, a VPP sensor circuit 433 comprising an error amplifier or the like for controlling the oscillation frequency of the VPP oscillator 432 is used. A VPP voltage having a desired potential is generated based on the reference voltage VREF and supplied to the memory macro cells 300A to 30OH. Similarly, the VBB generation circuit 440 includes a charge pump circuit and the like, and includes a plurality of VBB voltage generation circuits 441 that generate a reduced memory substrate voltage VBB such as 0.7 V, and a VBB voltage generation circuit 441. The VBB oscillator 442, which generates the oscillation signal necessary for the boost operation, compares the VBB voltage generated by the VBB voltage generation circuit 441 with the reference voltage VREF supplied from the reference voltage circuit 420, and VB B A VBB detection circuit (VBB sensor) 443, which includes an error amplifier for controlling the oscillation frequency of the oscillator 442, generates a VBB voltage of a desired potential based on the reference voltage VREF. Supply to 30 OH. Although not shown in FIG. 1, the voltage generated by the power supply & D FT macro cell 400 and supplied to the memory macro cells 300 A to 300 H includes a voltage VB LR for precharging the data line, There is also a plate voltage VPL applied to a common electrode called a memory cell plate provided as one terminal of a capacitance element for storing information charge in a memory cell, and the like. The generated voltage is supplied to the memory macro cells 300A to 300H.

Each of the memory macro cells 300 A to 30 OH has an input / output buffer 311 1 for inputting and outputting address data and control signals to and from the memory mat section 310 in which memory cells are spread, and the logic circuit section 200. An input decoder 312 for decoding an address specifying a word line WL, a word driver 313 for selectively driving a word line according to a decoding result, and a sense amplifier 3 14 connected to the data line DL and amplifying a signal on the data line. , A column decoder that decodes the column address that specifies the data line, a main amplifier that amplifies the read signal of the sense amplifier selected by the column decoder, and a memory control that controls the inside of the memory macro cell It is composed of circuits 317 and so on. When the gate line is composed of a main word line and a sub-word line connected to the main word line, the word driver 313 is also composed of a main word driver and a sub-word driver. As shown in FIG. 2, the lead line selection voltage VPP is supplied to the lead driver 313 in each memory macrocell 300, and the memory cell substrate voltage VBB is the level of the memory mat 310 as a substrate. Supplied to the area. Although not shown, the voltage VBLR for precharging the data line is supplied to the sense amplifier 316, and the memory cell plate voltage VPL is supplied to the memory mat 310. It should be noted that the embodiment shown in FIG. 2 shows the concept, and the above-mentioned voltages VPP and VBB generated by the power supply & D FT macro cell 400 are supplied to circuits other than those shown in the figure. It does not deny.

The test circuit 410 generates and supplies a signal for setting a circuit inside the memory macro cell 300 to a state suitable for a test. The DFT signal generated by the test circuit 410 is supplied to most circuits in the memory macro cell 300. The embodiments of the present invention can also be applied to a case where the test circuit 410 includes an ALPG that generates a test pattern and is configured to be capable of performing a self-test.

FIGS. 3 to 9 show the layout of the memory / logic embedded LSI of FIG. In the first embodiment of the layout of the logic-memory embedded LSI to which the present invention is applied, as shown in FIG. 3, the logic circuit section 200 is arranged almost at the center of the chip 100, and both sides (FIG. A plurality of memory macro cells 300 are arranged on the upper and lower sides, and the power supply & D FT macro cell 400 is arranged at the end (upper end in the figure) of the logic circuit section 200 opposite one of the memory macro cells 300A to 300D. I have. This allows the power & D FT macro cell 400 to have a longer wiring length used for transmitting and receiving signals between the logic circuit section 200 and the memory macro cell 300 than the layout arranged between the memory macro cell 300 and the logic circuit section 200. , The signal delay time is shortened, and high-speed operation becomes possible.

In this embodiment, the memory macro cell 300 has an internal word line WL parallel to the arrangement direction of the memory macro cells 300 A to 30 OD (horizontal in the figure). Direction), the data lines DL are arranged so as to be orthogonal to the parallel direction of the memory macro cells 300A to 300D. Thereby, the word line WL is orthogonal to the parallel direction of the memory macro cells 300A to 300D, and the data line DL is parallel to the parallel direction of the memory macro cells 300A to 300D. Furthermore, the data input / output line I / o used for transmitting and receiving signals between the logic circuit section 200 and the memory macro cell 300 becomes short, and the signal delay time is shortened, thereby increasing the data speed. Write and read operations can be performed.

Furthermore, in the present embodiment, a structure called a guard ring is formed along which the voltage and the signal generated by the power supply & DFT macrocell 400 are provided along the periphery of the chip to prevent the intrusion of moisture and the like. It is configured to be supplied to each memory macro cell 300 by the wiring arranged in the region 500.

More specifically, the main wiring is arranged in a ring shape in the guard ring region 500, and the memory macro cell 3 is placed between the wirings arranged on the opposite sides (left and right in FIG. 3) of the main wiring. A plurality of branch wirings 501 are provided in parallel with the word lines WL in the memory cell 0, and the memory macro cell 3 is provided through a through hole provided at an appropriate portion of a route of the branch wiring 501 and a contact hole. A voltage or a DFT signal is supplied to a desired location in 00.

As described above, by adopting a method of supplying a desired voltage into each memory cell through the branch wiring 501 arranged in parallel with the lead line WL, the logic circuit unit 200 and the memory macro cell 300 The branch wiring 501 can be provided without reducing the degree of freedom in the wiring design of the data input / output lines I / O used for transmitting and receiving signals during the transmission. This is because, in a semiconductor integrated circuit employing the multilayer wiring technology, wirings which are orthogonal to each other are often formed of different conductive layers. In FIG. 3, a single line for supplying the signal generated by the test circuit 410 to each memory macro cell AO0 is shown, but this does not exclude the case where there are a plurality of signal lines. As described above, in the embodiment of FIG. Since a common power supply & D FT macro cell 400 is provided for 00 and the voltage generated there is distributed to the memory macro cells 300, compared to the conventional method in which a power supply circuit and test circuit are provided for each memory macro cell As a result, the chip area can be reduced, and the power consumption of the entire chip can be reduced. In addition, since there is only one power supply circuit and the same voltage is supplied to each memory macro cell, it is easy to simulate the circuit operation, and the operation does not become unstable due to the interference of a large number of oscillator signals. There is no danger that the generated voltage will vary and the entire chip will not perform the desired operation.

Further, since the voltage generated by the power supply & D FT macro cell 400 is supplied to each memory macro cell 300 by the wiring 500 arranged in the guard ring area, a signal is transmitted between the logic circuit section 200 and the memory macro cell 300. The signal line region does not become narrow. Also, among the voltages generated in the power supply & DFT macrocell 400, the lead line selection voltage VPP requires the largest current supply capability, and if the wiring supplying this is long, the voltage may decrease due to the wiring resistance. is there. However, in the embodiment of FIG. 3, in the centralized power supply & D FT macro cell 400, the VPP generation circuit 430 for generating the word line selection voltage VPP is divided into two, and the test circuit 410, VREF generation circuit 420 and VBB generation circuit 440 are arranged on both sides of them. Therefore, the wiring length to the target memory macro cell is the shortest when the power is supplied to the VPP, and there is the advantage that the voltage drop due to the wiring resistance can be reduced.

FIG. 4 shows a second embodiment of a layout of a logic / memory embedded LSI to which the present invention is applied. The layout of this embodiment is different from the layout of FIG. 3 in that the VPP generation circuit 430 and the VBB generation circuit are also provided on the opposite side (lower end in the figure) of the chip with the logic circuit section 200 and the memory macro cell 300 interposed therebetween. A power supply & D FT macrocell 400, with a circuit 440, is installed. And the same type of voltage generated in each power supply & DFT macro cell 400 is connected in common to the corresponding one of the wirings provided in the guard ring region 500.

Note that the VPP generation circuit 430 and the 88 generation circuit 440 receive the reference voltage VREF generated by the VREF generation circuit 420 of the power supply & D FT macro cell 400 on the opposite side (the upper end in the figure), respectively. It is configured to generate the boosted voltages VPP and VBB of. The other configuration is the same as that of FIG.

As shown in FIG. 4, in this embodiment, the £ generating circuit 420 is 1 ^ 3, and the boosted voltages VPP and VBB are generated by the two power supplies & D FT macro cells 400 based on the same reference voltage VREF. Since the same type of generated voltage is connected to the same wiring in common, even if the two power supplies & DFT macrocells 400 have manufacturing variations, almost the same level of voltage is applied to each memory macrocell 300. Will be supplied. As a result, it is possible to avoid a state in which a desired operation cannot be expected for the entire chip. Also, since the same voltage level is supplied to each memory macrocell, it is easy to simulate the circuit operation, the operation does not become unstable due to the interference of many oscillator signals, and the generated voltage There is no danger that the chip will not perform the desired operation due to variations in the chip.

When the VPP generation circuit 430 and the VBB generation circuit 440 are provided on the opposing sides as shown in Fig. 4, the circuits on the opposing sides are driven by clocks whose phases are mutually shifted from each other. It is desirable to control so as to perform the boost operation. If the booster circuit is composed of a charge pump, the generated voltage will have ripples (pulsations), but the ripples will be reduced by applying the generated voltages whose periods are complementary to each other to the same wiring. This is because a more stable voltage can be supplied.

Further, in the embodiment of FIGS. 3 and 4, a plurality of memory macro cells 30 0 are arranged on the chip such that the lead lines are in the same direction. Therefore, when it is desired to increase the storage capacity of the memory built in the chip, the number of read lines of each memory macro cell must be increased, or when the memory macro cell is composed of multiple memory mats, By increasing the number of memory mats, it is possible to respond without changing the power supply & DFT macrocell 400.

In other words, there are two ways to increase the storage capacity of a memory macro cell: a method of increasing the number of word lines (memory rows) and a method of increasing the number of data lines (memory columns). When a memory macro cell having an increased number of data lines is used in the layout, the width of the memory macro cells 300 A to 300 D and the width of the power supply & DFT macro cell 400 do not match, and a useless area is generated.

In order to eliminate such a wasteful area, it is necessary to redesign the power supply & DFT macro cell 400, but there is a problem that the number of memory cells of the memory macro cell is increased or the If the number is increased, the number of word lines can be increased without changing the power supply & DFT macrocell 400. However, the VPP generation circuit 430 and VBB generation circuit 440 provided in the power supply & DFT macrocell 400 are designed in advance to have a large power supply capability, or they are activated simultaneously. It is necessary to adopt a design method that limits the number of data. This is because the load on the power supply circuit increases as the number of word lines increases.

It should be noted that designing the VPP generation circuit 430 and the VBB generation circuit 440 in advance as having a large power supply capability is required in a test mode in which a test is performed using the test circuit 410 or the like. This is a necessary design when it is desired to implement a test in parallel with a plurality of memory macrocells, so the design burden of applying this embodiment to a chip designed under such an idea Increase in chip area Can be

FIG. 5 shows, as an example, a configuration in which the storage capacity of the entire chip is increased by increasing the number of memory mats of each memory macro cell. In FIG. 5, the symbols MAT indicate the respective memory mats, and those indicated by broken lines indicate the memory mats provided in each macro cross cell in FIG. 4, and are indicated by the dashed line. Some are increased memory mats. In this way, by increasing the number of memory mats in the data line direction, the length of the memory macro cell row in the word line direction does not change, so that there is no need to change the design of the power supply & DFT macro cell 400. Power supply & D FT macro-senor 400, 400 'can be used as it is.

FIG. 6 shows a third embodiment of the layout of a logic / memory embedded LSI to which the present invention is applied. The difference between the layout of this embodiment and the layout of FIG. 4 is that the test circuit 410 and the VREF generation circuit 420 A power supply & DFT macrocell 400 having a VPP generation circuit 430 and a power supply & DFT macrocell 400 ′ having a VPP generation circuit 430 and a VBB generation circuit 440 are provided.

In this embodiment, the VPP generation circuit 430 'and the VBB generation circuit 440 in the power supply & D FT macro cell 400 are also connected to the VREF generation circuit of the power supply & D FT macro cell 400 on the opposite side (the right end in the figure). It is configured to receive the voltage VREF generated at 420 and generate boosted voltages VPP and VBB, respectively. The other configuration is the same as that of FIG. 4, and the description is omitted.

The embodiment of FIG. 6 has a configuration in which a plurality of memory macro cells 300 are arranged on a chip such that the word lines are in the same direction, and power supply & DFT macro cells 400, 400 are arranged on both sides thereof. Therefore, In order to increase the storage capacity of the memory built in the memory, the number of data lines in each memory macro cell is reduced, or when the memory macro cell is composed of a plurality of memory mats, By increasing the number of memory macro cells or the number of memory macro cells in the parallel direction of the memory macro cells 300, the power supply & DFT macro cells 400 can be handled without being changed.

In other words, as mentioned above, there are two ways to increase the storage capacity of the memory: a method to increase the number of word lines (memory rows) and a method to increase the number of data lines (memory columns). In such a layout, if the number of code lines in the memory macro cell is increased, the width of the power supply & DFT macro cell 400 and the width of the memory macro cell 300 do not match, and a useless area is generated.

In order to eliminate such a wasteful area, it is necessary to redesign the power supply & DFT macro cell 400. However, the number of data lines or the number of memory mats in the direction of the code line or the memory macro cell 300 By increasing the number of memory macrocells in the array direction, the storage capacity can be increased without changing the power supply & DFT macrocells 400. However, as in the embodiment of FIG. 5, the VPP generation circuit 430 and the VBB generation circuit 440 provided in the power supply & DFT macrocell 400 are designed in advance as having a large power supply capability. Alternatively, it is necessary to adopt a design method that limits the number of simultaneously activated memory macro cells.

When the number of data lines in a memory macro cell is reduced or the number of mats is increased, it is necessary to redesign the memory macro cell.Therefore, increasing the number of memory macro cells is the method with the least design burden. .

FIG. 7 shows, by way of example, a configuration in which the storage capacity of the entire chip is increased by increasing the number of memory macro cells in the parallel direction of the memory macro cell 300. Thus, the average of memory macro cells 300 By increasing the number of memory macrocells in the vertical direction, the length of the memory macrocells in the data line direction does not change, so that there is no need to change the design of the power supply & DFT macrocell 400, and the power supply & DFT macrocell 400 in FIG. 0 can be used as it is. However, if each memory macro cell is composed of multiple memory mats, the design of the power supply & DFT macro cell 400 is changed even if the number of memory mats in each macro cross cell is increased in the direction of the code line. The storage capacity of the memory built into the chip can be increased without the need.

Whether the number of memory mats or the number of memory macrocells is increased to increase the storage capacity also depends on the shape of the original memory macrocell, that is, the ratio of the length to the width. Specifically, as shown in Fig. 6, when the length of the memory macrocell in the code line direction is shorter than the length of the data line direction, the chip width does not increase so much even if the number of memory macrocells is increased. However, if the length of the memory macro cell in the code line direction is longer than the length of the data line direction, increasing the number of memory macro cells may significantly increase the chip width. In such cases, it may be better to increase the number of memory mats.

Next, another embodiment of the layout of the logic / memory embedded LSI to which the present invention is applied will be described with reference to FIGS. 8 and 9. FIG. The same circuits and parts as those in FIG. 3 are denoted by the same reference numerals, and redundant description will be omitted.

In the embodiment of FIG. 8, the power supply & DFT macro cell 400 is arranged at one place of the chip (a part of the logic circuit section 200 in the figure) instead of being arranged along the side of the chip. In such a layout, although there is a slight disadvantage that the variation in the length of the power supply line from the VPP generation circuit 430 to each memory macrocell is larger than that in the embodiment of FIG. Since 0 is provided as a common circuit for a plurality of memory macro cells, the chip area is reduced and the chip size is reduced as compared with the conventional method in which a power supply & DFT macro cell is provided for each memory macro cell. The overall power consumption of the chip can also be reduced. In addition, regardless of whether the memory storage capacity is changed, either the line direction or the data line direction is changed, it is not necessary to change the power supply & DFT macro cell by redesigning the logic circuit. And the like.

The embodiment of FIG. 9 is different from the embodiment of FIG. 3 in that the power supply & DFT macro cell 400 is configured as a separate chip 600 instead of being provided on a logic-memory hybrid LSI chip, and the logic and memory hybrid LSI chip 1 The package is mounted in a single package 700 made of ceramic or the like together with the chip 100, and the chips are connected with bonding wires 800 to form a multi-chip module.

This embodiment has the disadvantage that the resistance of the wiring for supplying a voltage such as VPP to the memory macrocells 300 and the volume of the device are slightly larger than those of the embodiment of FIG. & Compared to the conventional method with DFT macro cells, the power consumption of the whole module can be reduced and the chip area of each module can be reduced, so that the chip yield can be improved and the cost can be reduced. can get. Next, the structure of the wiring 500 provided in the guard ring region will be described with reference to FIG. 10 and FIG. FIG. 10 is a cross-sectional plan view showing a part of the guard ring region (corner portion of the chip) in an enlarged manner. FIG. 11 is a diagram showing a cross-sectional structure of the guard ring region. FIG. — Cross section along line B, and FIG. 11 shows a cross section along line A—A in FIG. In FIG. 10 and FIG. 11, illustration of an insulating film interposed between the respective conductive layers constituting the wiring is omitted.

5 10 is a guard ring, and the guard ring 5 10 is a plurality of conductive layers 5 1 formed so as to be substantially in a line along the height direction. Conductors (vias) filled in contact holes formed continuously in the direction parallel to the edge of the chip in the insulating film between these conductive layers and the conductive layers. 5 2 7 to form a wall, and moisture and the like enter from outside the chip It has the function of preventing A ground potential VSS is applied to the guard ring 5 10 so that the guard ring 5 10 also serves as a power supply line for supplying a substrate potential to the semiconductor chip 100.

The uppermost conductive layer 537 inside the guard ring 510 and the lower conductive layer 536 are used to supply the word line selection voltage VPP generated by the power supply & D FT macrocell 400 to the memory macrocell. Wiring. A plurality of wirings 545 formed by the conductive layer immediately below the conductive layer 526 supplying the VPP are used to transmit the signal generated by the DFT circuit, and a wiring 55 inside the wiring is a power supply & DFT Wiring for supplying the memory cell substrate voltage VBB generated by the macrocell 400 to the memory macrocell.

In a conductive layer two below the DFT wiring 545, a wiring 563 to which a ground potential VSS is applied and a wiring 543 for transmitting a signal generated by the DFT circuit are provided. In addition, the reference voltage VREF generated by the power supply & D FT macro cell 400 is applied between the VSS wiring 563 and the conductive layer 513 forming the guard ring 510 or the VPP generation circuit 530 or VBB. A wiring 573 for supplying to the generation circuit 540 is provided. A conductive layer 512 constituting the guard ring 5110 extends below the wiring 573 below the VREF wiring 573. In this way, the wiring 5 7 3 for the ¥ 11 £ is formed by the card ring 5 10 to which the ground potential V S S is applied, the wiring 5 63, the extension of the conductive layer 5 1 2, and the DFT wiring 5

With the structure surrounded by 43 and 545, it is possible to prevent noise from being applied to the VREF wiring 573 due to the power coupling capacitance between the wirings.

Above the DFT wiring 543, which is made of the same conductive layer as the VREF wiring 573, the voltage VREF generated by the VREF generation circuit formed on the substrate surface is applied to the VREF wiring 573. Wiring 5 74 for communication is provided. This wiring 5 74 is formed of a conductive layer 5 75,

5 After passing through 76 and 577, the MOS that constitutes the VREF generation circuit on the substrate surface The FETs 58 1 and 58 2 are connected to diffusion layers 58 1 d and 58 2 d as drain regions.

Except for the portion where the wiring 574 is formed, an eaves-like shape is formed above the VREF wiring 573 by the conductive layer 514 that is formed of the same conductive layer as the wiring 574 and that forms the guard ring 510. If a cover is provided, more desirable results can be obtained in terms of noise suppression. In FIG. 10, reference numeral VIA denotes a via made of a conductive material filled in a contact hole connecting upper and lower wirings, and reference numeral 585 denotes a via in FIG. This is a decoupling capacitance for suppressing the fluctuation of the source voltage.

Further, a protective film 590 made of PIQ (polyimide insulating film) is formed on the top of the chip, and the voltages VPP and VBB generated by the guard ring 5100 and the power supply & D FT macro cell 400 are formed. The wirings 537, 536, 545, 555, 543, and 542 for supplying to the memory macro cells are arranged so as not to protrude from the protective film 590 made of this PIQ. In other words, the protective film 590 is formed up to the vicinity of the edge of the chip so as to completely cover the wirings 537, 536, 545, 55, 543 and 542. As a result, it is possible to more reliably prevent the wiring formed around the chip from being damaged during chip assembly.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it can be said that various modifications can be made without departing from the gist of the invention. Not even.

For example, in the above-described embodiment, the memory power generation circuit for generating the voltage supplied to the memory macro cell and the test circuit for generating the test signal are configured as one macro cell. The generation circuit and the test circuit can be configured as separate macro cells. Further, the present invention can be applied to an LSI having only a power supply circuit for memory and not having a test circuit. Industrial applicability

The case where the present invention is applied to a logic / memory hybrid LSI having a logic circuit portion and a memory has been described above.The present invention relates to an LSI or a memory having an analog circuit in addition to the logic circuit portion and the memory, and an analog circuit. It can be used for LSIs that have it.

Claims

The scope of the claims

1. A semiconductor integrated circuit with a built-in memory in which a logic circuit and a plurality of memory circuits are mounted, wherein a memory power generation circuit for generating a voltage required for the plurality of memory circuits is a common circuit. A semiconductor integrated circuit with a built-in memory, which is arranged on the same substrate.

2. A semiconductor integrated circuit with a built-in memory in which a logic circuit and a plurality of memory circuits are mounted, wherein a memory power generation circuit for generating a voltage necessary for the plurality of memory circuits is used as a common circuit. A semiconductor integrated circuit with a built-in memory, which is arranged along two opposing sides of a semiconductor substrate.

3. The voltage generated by the memory power generation circuit is configured to be supplied to each memory circuit by a wiring formed in a guard ring region provided at a peripheral portion of the semiconductor substrate. 3. The semiconductor integrated circuit with a built-in memory according to claim 2, wherein:

4. The plurality of memory circuits are arranged such that gate lines to which the selection terminals of the memory cells in the same row in each of the plurality of memory circuits are connected in common are in the same direction. 4. A semiconductor integrated circuit with a built-in memory according to item 2 or 3.

5. The semiconductor integrated circuit with built-in memory according to claim 4, wherein the power supply circuit for memory is arranged on a side parallel to the word line inside the memory circuit.

6. The power supply circuit for memory includes the word inside the memory circuit. 5. The semiconductor integrated circuit with built-in memory according to claim 4, wherein the semiconductor integrated circuit is arranged on a side orthogonal to the line.

7. The semiconductor integrated circuit with a built-in memory according to claim 5, wherein the plurality of memory circuits are arranged in two columns, and a logic circuit is arranged between these memory circuit columns. ,

8. The voltage generated by the memory power generation circuit and supplied to the memory circuit is such that the input / output terminals of the memory cells in the same column are mainly connected in common with the first voltage for providing the word line selection level. 8. The semiconductor integrated circuit with a built-in memory according to claim 2, wherein the second voltage is a second voltage for applying a precharge voltage of the data line.

9. A test circuit for generating a signal to be supplied to each memory circuit at the time of testing the memory circuit, wherein the test circuit is formed integrally with the memory power generation circuit, and is generated by the test circuit. 9. The semiconductor integrated circuit with a built-in memory according to claim 3, wherein said signal is supplied to each memory circuit by a wiring formed in said guard ring region.

10. The memory power generation circuit includes a reference voltage generation circuit for generating a third voltage serving as a reference for generating the first voltage and the second voltage on any one side of the semiconductor substrate. 10. The memory built-in semiconductor according to claim 9, wherein the reference voltage generated by the reference voltage generation circuit is supplied to the memory power generation circuit on the other side by a wiring formed in the guard ring region. Integrated circuit.

11. The wiring for supplying the reference voltage is formed in the guard ring region. 10. The semiconductor integrated circuit with a built-in memory according to claim 10, wherein the semiconductor integrated circuit with the built-in memory is arranged so as to be surrounded by a supply line for supplying a fixed potential and a line for supplying a signal generated by the test circuit.

12. The circuit that generates the first voltage is configured as two or more circuits, and these circuits are arranged so as to sandwich the reference voltage generation circuit and the circuit that generates the first voltage. The semiconductor integrated circuit with a built-in memory according to claim 10 or 11, wherein:

13. A method of designing a semiconductor integrated circuit with a built-in memory, in which the power supply circuit for the memory and the memory circuit excluding the power supply circuit are designed as separate macro cells in advance. When developing a new semiconductor integrated circuit, the number of memory macros to be mounted is determined so as to obtain the desired storage capacity, and these are connected together by the selection terminals of the memory cells in the same row inside. Of the semiconductor substrate as one or two cells common to the plurality of memory macro cells, while arranging the macro cells including the power supply generation circuit in such a manner that the read word lines are arranged in the same direction in the chip. A method for designing a semiconductor integrated circuit with a built-in memory, wherein the semiconductor integrated circuit is arranged along one or two sides.

14. When the power supply generation circuit is arranged on a side parallel to the word line and the storage capacity of the memory macro cell is increased, the number of connection lines of each memory macro cell and the number of memory cells connected thereto are increased. 14. The method for designing a semiconductor integrated circuit with a built-in memory according to claim 13, wherein:

15. When the power supply generating circuit is arranged on the side parallel to the data line to which the input / output terminals of the memory cells in the same column orthogonal to the word line are connected in common to increase the storage capacity of the memory macro cell Each memory macro cell 14. The method for designing a semiconductor integrated circuit with a built-in memory according to claim 13, wherein the number of data lines and the number of memory cells connected thereto are increased.