JPH10209371A - Ic memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid poor injection, by adhering and connecting a first chip having a memory circuit on a semiconductor substrate to a second chip having a power source circuit on the semiconductor substrate. SOLUTION: Memory cell arrays 2a-2d, row decoders 3a-3d, column decoders with amplifiers 4a-4d, predecoders 5a-5d and control circuits 7a-7d are formed by one chip to form chips 20, 30, 40, 50. Input/output circuits 6a-6d, a power source circuit 8, an input buffer 9 and a address buffer 10 are formed by one chip 60 on which the chips 20-50 are mounted and adhered to connect. Thus, the memory array is formed on the first chip and surge absorbing elements are formed on the second chip, thereby avoiding poor injection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a multi-chip IC memory in which a semiconductor memory is constituted by using a plurality of semiconductor chips.

[0002]

FIG. 7 shows a conventional 8M × 32 DR.
FIG. 2 is a schematic block diagram illustrating a circuit example of an IC memory forming an AM. 7, an IC memory 150 includes a memory cell array 151, a row decoder 152, a column decoder / amplifier circuit 153, and a predecoder 154.
, An input / output circuit 155, a power supply circuit 156, a control circuit 157, an input buffer 158, and an address buffer 1
59. The input / output circuit 155 inputs and outputs data from the outside, and the power supply circuit 156 generates a voltage for each internal circuit, a power-on reset signal, and the like based on power supplied from the outside.

The control circuit 157 includes a row decoder 1
52, a column decoder and amplifying circuit 153, a predecoder 154, an input / output circuit 155, a power supply circuit 156, and an address buffer 159. Input buffer 158
Receives an external control signal such as a write enable signal and a chip enable signal,
59 is input with address data from the outside. Note that the column decoder and amplifier circuit 153 includes a sense amplifier, a column decoder, an I / O switch transistor, a preamplifier, and the like.

FIG. 8 is a diagram showing a layout of each circuit when the DRAM shown in FIG. 7 is formed by one chip. In FIG. 8, a chip 200 has 20
A power supply circuit 156 is formed in portions 1 and 202, a control circuit 157 and an input buffer 158 are formed in portion 203, and a memory cell array 151, a row decoder 152, a column decoder and a column decoder 204 are formed in portions 204 to 207. An amplification circuit 153 and a predecoder 154 are formed, and an input / output circuit 155 and an address buffer 159 are formed at 208 and 209.

FIG. 9 is a diagram showing an example of the pin arrangement of the IC memory 150 formed by the chip 200 shown in FIG. 8, and FIG. 10 is a diagram showing an example of the structure in the IC package shown in FIG. FIG. In FIG. 10, the IC memory 150 includes the pads 30 formed on the chip 200.
1 is a bonding wire 302 and a lead frame 303
Are electrically connected to predetermined portions, respectively.

[0006]

The above-mentioned input buffer 15
8, an input protection circuit is provided at an input of the address buffer 159 and the like, and the input protection circuit is an element that performs surge absorption (hereinafter, referred to as a field transistor).
Are formed. FIG. 11 is a cross-sectional view of a chip showing an example of the structure of a field transistor. The field transistor 400 is formed by forming an isolation oxide film region 404 between two n ⁺ diffusion regions 402 and 403 formed on a p-type silicon substrate 401. The n ⁺ diffusion region 402
Connected to an aluminum wiring 406 formed in the insulating film 405 to form a source of an n-channel MOS transistor;
N ⁺ diffusion region 403 is connected to aluminum wiring 407 formed in insulating film 405 and forms the drain of an n-channel MOS transistor.

[0007] The drain of the field transistor 400 is connected to the Vss terminal shown in FIGS. 7 and 9.
Electrons are injected into the silicon substrate 401. For example, in the case of a system that operates at a high speed, an under-short of -3 to -4 V occurs, and the p-type silicon substrate 401 has Vss or
Since it is biased to about 1 to −2 V, n ⁺ diffusion region 402 serving as the source of field transistor 400
And the p-type silicon substrate 400 becomes forward biased, and electrons are injected into the p-type silicon substrate 400.

[0008] The DRAM shown in FIGS.
Since it is formed on one chip, the n ⁺ diffusion region 402 and the memory cell array 151 that form the source of the field transistor 400 are formed on the same substrate. For this reason, there has been a problem that the electrons injected from the n ⁺ diffusion region 402 reach the memory cell array 151 and destroy data stored in the memory cells, that is, a so-called injection defect occurs.

Further, as described above, an 8M × 32 DRAM
When one chip is formed, the chip size is about 300 m
become m ^2. However, when the chip size exceeds 100 mm ² , there has been a problem that the yield rapidly decreases and the chip cost increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has as its object to obtain an IC memory which can eliminate the above-mentioned injection failure and reduce the chip cost. .

[0011]

An IC according to the first aspect of the present invention.
The memory is a multi-chip type IC memory formed of a plurality of semiconductor chips, at least one first chip having a storage circuit portion having a memory cell array formed on a semiconductor substrate, and an input circuit for inputting a signal from outside Department,
An output circuit section for outputting a signal to the outside and a power supply circuit section for supplying power to each internal circuit section are formed on a semiconductor substrate;
And a chip, wherein the first chip is bonded to and connected to the second chip.

[0012] In the IC memory according to the second aspect, in the first aspect, the first chip may be configured such that the first chip uses a bump to form the second chip.
It is connected on a chip.

According to a third aspect of the present invention, there is provided an IC memory according to the first or second aspect, wherein surge absorption is achieved by forming an isolation oxide film region between two n ⁺ diffusion regions formed on a semiconductor substrate. An element to be performed is formed on the second chip.

According to a fourth aspect of the present invention, there is provided an IC memory according to any of the first to third aspects, wherein the semiconductor element formed on the first chip has a smaller thickness, and the semiconductor element formed on the second chip has a smaller thickness. Is formed with a large film thickness.

The IC memory according to a fifth aspect of the present invention is the IC memory according to the fourth aspect, wherein the thickness of the gate oxide film of the transistor formed on the first chip is reduced, and the thickness of the transistor formed on the second chip is reduced. The gate oxide film is formed with a large thickness.

According to a sixth aspect of the present invention, in the IC memory according to the first to fifth aspects, the wiring layer formed on the first chip is formed by a thin film, and the wiring layer formed on the second chip is formed by a thin film. It is formed with a thick film.

An IC memory according to a seventh aspect of the present invention is the IC memory according to the first to sixth aspects, wherein a decoupling capacitor is formed in an empty area of the second chip.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. Embodiment 1 FIG. FIG. 1 is a block diagram showing a circuit example of the multi-chip IC memory according to the first embodiment of the present invention.

In FIG. 1, an IC memory 1 includes memory cell arrays 2a, 2b, 2c, 2d, row decoders 3a,
3b, 3c, 3d, column decoder and amplifier circuit 4
a, 4b, 4c, 4d and predecoders 5a, 5b, 5
c, 5d, input / output circuits 6a, 6b, 6c, 6d for inputting / outputting data to / from the outside, row decoder 3a, column decoder / amplifier circuit 4a, predecoder 5a, and control for controlling input / output circuit 6a. A circuit 7a and a control circuit 7b for controlling the row decoder 3b, the column decoder and amplifying circuit 4b, the predecoder 5b, and the input / output circuit 6b
And a row decoder 3c, a column decoder and an amplifier circuit 4.
c, a control circuit 7c for controlling the predecoder 5c and the input / output circuit 6c, and a control circuit 7d for controlling the row decoder 3d, the column decoder and amplifying circuit 4d, the predecoder 5d and the input / output circuit 6d.

Further, the IC memory 1 stores a step-down power supply voltage intVcc,
A power supply for generating a silicon substrate bias voltage Vbb, a word line driving boosted voltage Vpp, a cell plate voltage Vcp, and a bit line potential holding voltage VBL, and further generating a power-on reset signal POR at power-on. Circuit 8,
The input buffer 9 outputs signals generated based on a row address strobe signal, a chip enable signal, and a write enable signal input from outside to the control circuits 7a to 7d, and is controlled by an enable signal from the control circuits 7a to 7d. And an address buffer 10 for generating an internal address signal based on an external address signal.

The input buffer 9 has a / RAS terminal to which a row address strobe signal / RAS is input, and / CE0, / CE1, / CE2, to which chip enable signals / CE0, / CE1, / CE2, / CE3 are input. / WE to which each terminal of / CE3 and the write enable signal / WE are inputted
Terminals, respectively, and further, each of the control circuits 7a to 7d
Connected to each other. The address buffer 1
0 is connected to each of the terminals A0 to A13 to which the address signals A0 to A13 are input.
5d. In addition, / indicates the inversion of the signal level.

The control circuits 7a to 7d are connected to the corresponding row decoders 3a to 3d, column decoders and amplifier circuits 4a to 4d, predecoders 5a to 5d, and input / output circuits 6a to 6d. It is connected to the circuit 8 and the address buffer 10, respectively. The row decoders 3a to 3d and the column decoders and amplifier circuits 4a to 4d are connected to the corresponding memory cell arrays 2a to 2d, respectively, and the column decoders and amplifier circuits 4a to 4d are connected to the corresponding input / output circuits 6a to 6d, respectively. 6
d. The predecoders 5a to 5d are connected to the corresponding row decoders 3a to 3d, respectively, and also correspond to the corresponding column decoders and amplifier circuits 4a.
To 4d. Further, the column decoder and amplifier circuits 4a to 4d are connected to corresponding input / output circuits 6a to 6d.

The input / output circuit 6a is connected to each of data input / output terminals DQ0 to DQ7.
Connected to the data input / output terminals DQ8 to DQ15,
The input / output circuit 6c is connected to data input / output terminals DQ16 to DQ23, and the input / output circuit 6d is connected to data input / output terminals DQ24 to DQ31. The power supply circuit 8 is connected to power supply terminals Vdd and Vss and further supplies power to each circuit, but the connection is omitted. Note that I
The C memory 1 is provided with power supply terminals VddQ and VssQ separately from the power supply terminals Vdd and Vss. The power supply terminals VddQ and VssQ are connected to predetermined portions of each circuit, but the connection is omitted here. doing.

The column decoder and amplifier circuits 4a to 4a
d is a sense amplifier for amplifying data of a memory cell connected by a word line selected by the corresponding row decoder 3a to 3d, and a corresponding predecoder 5
a column decoder for selecting the sense amplifier based on the outputs of a to 5d, an I / O switch transistor for connecting the sense amplifier to a local I / O line based on an output signal from the column decoder, A preamplifier for amplifying a signal read to the local I / O line is included. Furthermore, the column decoder and amplifier circuits 4a to 4a
d may include a write circuit for writing data to the corresponding memory cell arrays 2a to 2d based on the output signals of the corresponding input / output circuits 6a to 6d.

The predecoders 5a to 5d generate a predecode signal from the internal address signal input from the address buffer 10, and convert the predecode signal into the corresponding row decoders 3a to 3d, and the column decoder and amplifier circuits 4a to 4d. Output to 4d. The input / output circuit 6
a to 6d denote corresponding column decoders and amplifying circuits 4a.
4d, data is output from each data terminal based on the output signal of the preamplifier. The memory cell arrays 2a to 2d, row decoders 3a to 3d, column decoders and amplifier circuits 4a to 4d, and predecoders 5a to 5d
And the control circuits 7a to 7d form a storage circuit section, and the input / output circuits 6a to 6d, the input buffer 9, and the address buffer 1
0 forms an input circuit section, and the input / output circuits 6a to 6d also form output circuit sections. The power supply circuit 8 forms a power supply circuit section.

In the above configuration, the memory cell array 2a, the row decoder 3a, the column decoder / amplifier circuit 4a, the predecoder 5a and the control circuit 7a are formed as one chip to form a chip 20, and the memory cell array 2b, the row decoder 3b, a column decoder and amplifying circuit 4b, a predecoder 5b, and a control circuit 7b are formed on one chip to form a chip 30, and the memory cell array 2
c, row decoder 3c, column decoder and amplifying circuit 4
c, the predecoder 5c and the control circuit 7c are formed in one chip to form a chip 40, and the memory cell array 2d,
A row decoder 3d, a column decoder and an amplifier circuit 4d,
The pre-decoder 5d and the control circuit 7d are formed on one chip to form a chip 50.

Further, the input / output circuits 6a to 6d, the power supply circuit 8, the input buffer 9 and the address buffer 10 are formed as one chip to form a chip 60, and the chips 20, 30, 40 are formed on the chip 60. , 50 are arranged and connected. Here, the control circuits 7a to 7d include:
When a signal for enabling each formed chip is input, a signal is output to the power supply circuit 8 and the power supply circuit 8
Reduces the capacity of the power supplied to each chip on which the control circuit which has not received the signal is formed. Note that the chips 20, 30, 40, and 50 form a first chip,
The chip 60 forms a second chip.

Next, FIG. 2 shows the above-mentioned chips 20, 30, 4
FIG. 3 is a diagram showing a layout example in which 0 and 50 are arranged on a chip 60. 2, the chip 20 includes 21 to 2
4, a memory cell array 2a, a row decoder 3a,
A column decoder / amplifier circuit 4a and a predecoder 5a are formed, and a control circuit 7a is formed at a position 25. In the chip 30, a memory cell array 2b, a row decoder 3b, a column decoder and amplifying circuit 4b, and a predecoder 5b are formed in parts 31 to 34, and a control circuit 7b is formed in part 35.

Similarly, in the chip 40, a memory cell array 2c, a row decoder 3c, a column decoder and amplifying circuit 4c, and a predecoder 5c are formed in portions 41 to 44, and a control circuit 7c is formed in a portion 45. You. In the chip 50, the memory cell array 2
d, row decoder 3d, column decoder and amplifying circuit 4
d and a pre-decoder 5d are formed, and a control circuit 7d is formed at a portion 55. The chip 60 has 6
Input / output circuits 6a to 6d, an input buffer 9 and an address buffer 10 are formed in portions 1 to 64, and a power supply circuit 8 is formed in portion 65. Further, the chips 20, 30, 40, and 50 are arranged and connected on the chip 60, respectively.

Normally, a circuit portion having a high degree of integration has a high defect rate, and furthermore, if the chip size exceeds 100 mm ² , the yield rapidly decreases. , 50, and by keeping the chip size of the chips 20, 30, 40, 50 from exceeding 100 mm ² , the yield can be improved and the chip cost can be reduced. In the first embodiment, the portion having a high degree of integration is formed by dividing into four chips 20, 30, 40, and 50. However, the present invention is not limited to this. , 50 chip size is 100mm ²
If the chip size exceeds 100 mm ² , the portion where the degree of integration is high is divided into more chips.
What is necessary is just to make it below.

Next, FIG.
FIG. 3 is a schematic cross-sectional view showing a connection method for connecting
, The chips 20, 30, 40, 5 on the chip 60
A method of connecting 0 will be described using the chip 20 as an example. Note that, in FIG. 3, each device formed on the chips 20 and 60 is omitted for simplicity of description, and only a portion related to the connection between the chips 20 and 60 is shown. In FIG. 3, the chips 20 and 60
Are shown only partially.

In FIG. 3, connection electrodes 71 and 72 are formed on one surface of the chip 20 on which each device is formed, and an insulating film 73 is formed on the electrodes 71 and 72, respectively. It has not been. Similarly, a connection electrode 75 is provided on one surface of the chip 60 where each device is formed.
And 76 are formed, and a pad 77 for connecting to the lead frame using a bonding wire is formed. An insulating film 78 is not formed on each of the electrodes 75 and 76 and the pad 77. The electrodes 71 and 75, and the electrodes 72 and 76 are formed at corresponding positions. The electrodes 71 and 75 are connected using bumps 81, and the electrodes 72 and 76 are connected using bumps 82. Connected.

FIG. 4 is a schematic diagram showing an example of the structure inside the IC package in the IC memory according to the first embodiment.
In FIG. 4, the IC memory 1 includes chips 20, 30, 4
Chip 60 in which 0, 50 are connected by the method shown in FIG.
The pads 77 formed on the bonding wires 85
Are electrically connected to predetermined portions of the lead frame 86, respectively.

FIG. 5 is a circuit example showing a part of the address buffer 10 shown in FIG. FIG.
The pad 77 indicated by is designated as a pad 77a. In FIG. 5, a pad 77 to which an address signal is input from the outside is provided with an input protection circuit 91 having a field transistor.
Is connected. The input protection circuit 91 includes a field transistor 92, an n-channel MOS transistor 9
3 and two resistors 94 and 95.

The pad 77a is connected to the source of a field transistor 92 via a resistor 94, and the connection is connected to the drain of an n-channel MOS transistor 93 via a resistor 95. The drain of the field transistor 92 and the gate and source of the n-channel MOS transistor 93 are connected to the Vss terminal, respectively. The connection between the drain of the n-channel MOS transistor 93 and the resistor 95 is connected to one input terminal of the NOR circuit 96, and the other input terminal of the NOR circuit 96 has an undefined input potential applied to the pad 77. Sometimes N
Address buffer enable signal / CAI for preventing a current flowing through OR circuit 96 is input.

The output of the NOR circuit 97 is connected to a transmission gate 98 via an inverter circuit 97. The transmission gate 98 is connected to a latch circuit 10 formed by two inverter circuits 99 and 100.
1 and the latch circuit 101 is connected to each of the predecoders 5a to 5d via an inverter circuit 102. Further, an address latch signal / CAL for latching the signal input to the pad 77 by the latch circuit 101 at a predetermined timing is transmitted via the gate of the n-channel MOS transistor forming the transmission gate 98 and the inverter circuit 103. p-channel type MO
It is input to the gate of each S transistor.

In such a configuration, the address buffer 10 including the input protection circuit 91 is formed on the chip 60 shown in FIG. 2, and the field transistor 92 is also formed on the chip 60. Here, the memory cell arrays 2a to 2d are not formed on the chip 60, but are formed on the chips 20, 30, 40, and 50, respectively. From this, the field transistor 92
And the memory cell arrays 2a to 2d are not formed on the same chip, it is possible to prevent an injection failure caused by an undershoot in a signal input from the pad 77. The input protection circuit 9
1, the n-channel MOS transistor 93 is
This is used for operation check.

FIG. 6 shows the input / output circuit 6a shown in FIG.
It is a circuit example which shows a part of 6d. The pad 77 shown in FIG. 6 is referred to as a pad 77b. In FIG. 6, an n-channel MOS transistor 111 is provided on a pad 77b.
Is connected to the drain of the n-channel MOS transistor 112, and the drain of the n-channel MOS transistor 111 is connected to the power supply terminal VddQ of the IC memory 1.
And an n-channel MOS transistor 1
The source 12 is connected to the power supply terminal VssQ of the IC memory 1.

The gate of the n-channel MOS transistor 111 is connected to the output of the level conversion circuit 113, and the input of the level conversion circuit 113 is
4 is connected to the output. One input of the NAND circuit 114 is connected to one input of the NAND circuit 115, and an output enable signal OEM from the control circuit is input to the connection.

The other input terminal of the NAND circuit 114 receives a data signal DATA from a column decoder and an amplifier circuit corresponding to the input / output circuit.
, The inverted data signal / DATA from the column decoder and the amplifier circuit corresponding to the input / output circuit is input. The output of the NAND circuit 115 is
6 and the output of the inverter circuit 116 is
Connected to the gate of n-channel MOS transistor 112.

In the level conversion circuit 113, the power supply terminal 117 is connected to the power supply circuit 8, the boosted voltage Vpp is supplied from the power supply circuit 8, and the power supply terminal 118 is connected to the IC.
Connected to Vss terminal of memory 1. The power supply terminal 117 may be connected to the Vdd terminal of the IC memory 1. Thus, the power supply terminals 117 and 1 of the level conversion circuit 113
18 and n-channel MOS transistors 111 and 11
2 is connected to the pad 77b.
It is possible to prevent noise generated at the time of data output when data is output from the level conversion circuit 113 from passing through the chip substrate. Further, by supplying the boosted voltage Vpp to the power supply terminal 117 of the level conversion circuit 113, the “H” level of the signal output from the pad 77b can be increased.

Here, the NAND circuits 114 and 11
5 are connected to a column decoder and an amplifier circuit, so that only the NAND circuits 114 and 115 are formed on the corresponding chips 20, 30, 40 and 50 in the input / output circuits 6a to 6d. can do. By doing so, the wiring can be shortened, the wiring can be simplified, and the number of bumps can be reduced, so that the cost can be reduced.

Further, 61 to 65 in the chip 60
The decoupling capacitor can be formed by forming two metal wiring layers and an isolation oxide film in a vacant region other than the above region. Since the IC memory 1 has a multi-chip structure in which the chips 20, 30, 40, and 50 are connected to the chip 60, the free space is formed larger in the chip 60 as compared with the case where the IC memory 1 is formed by a single chip. Therefore, a decoupling capacitor having a larger capacity than the conventional one can be formed, and a conventionally used decoupling capacitor can be reduced.

The capacitor for decoupling thus formed on the chip 60 is connected to the VddQ terminal of the IC memory 1 and the VssQ terminal.
By connecting between the terminals or between the terminal for outputting the boosted voltage Vpp of the power supply circuit 8 and the Vss terminal of the IC memory 1,
Noise can be reduced. In addition, chip 20,
It can also be used as a decoupling capacitor for the power consumed by 30, 40, 50.

As described above, the multi-chip IC memory according to the first embodiment of the present invention includes the memory cell arrays 2a to 2d, the row decoder 3
a to 3d, column decoder and amplifying circuits 4a to 4d, predecoders 5a to 5d, and control circuits 7a to 7d are formed on chips 20, 30, 40, and 50, respectively. The circuits 6a to 6d, the power supply circuit 8, the input buffer 9, and the address buffer 10 were formed on the chip 60, and the chips 20, 30, 40, and 50 were arranged on the chip 60 and connected.

From the above, what has been conventionally laid out two-dimensionally on the same plane is connected by stacking chips, so that it is possible to lay out three-dimensionally. The length of the line can be reduced, which is advantageous in increasing the operation speed. Further, since the manufacturing processes of the chips 20, 30, 40, 50 and the chip 60 can be separated, the chips 20, 30, 4, 4
Reference numerals 0 and 50 indicate that the wiring layer is formed of a thin film suitable for miniaturization, and that the chip 60 does not need to be miniaturized so easily that it can be easily formed of a thick film. For this reason, the wiring of the chip 60 can reduce the resistance value. , Chip 2
By forming them at 0, 30, 40, and 50, the speed of the circuit can be increased.

Further, the thickness of the gate oxide film of the transistors formed on the chips 20, 30, 40, and 50 and the transistor formed on the chip 60 can be easily changed. In other words, transistors forming an input buffer, an address buffer, an input / output circuit, and the like formed in the chip 60 to which a surge or the like may be input use a thick gate oxide film, and the chips 20, 30, and 40,5
A transistor forming a control circuit or the like formed at 0 is
Use a gate oxide film that is suitable for miniaturization. By doing so, it is possible to avoid a decrease in the surge withstand voltage in the input / output unit that occurs when the device is miniaturized. Further, the memory cell array is divided into chips 20, 30, 40, 50
And the field transistor is formed on the chip 60, and the memory cell array and the field transistor can be formed on different chips, respectively, so that injection failure can be prevented.

In addition, a circuit portion having a high degree of integration, in which manufacturing defects are likely to occur, is formed on the chips 20, 30, 40, 50, and each chip size of the chips 20, 30, 40, 50 is reduced to 100 mm ² or less. Thereby, the yield can be improved and the chip cost can be reduced.

[0049]

According to the IC memory of the first invention, at least one first chip in which a storage circuit section having a memory cell array is formed on a semiconductor substrate is connected to an input circuit section to which a signal is inputted from outside, and to an outside. An output circuit for outputting a signal,
A power supply circuit section for supplying power to each internal circuit was bonded and connected to a second chip formed on a semiconductor substrate. For this reason, chips that are conventionally laid out two-dimensionally on the same plane are connected by stacking chips, so that three-dimensional layout can be performed, and the length of signal lines connecting each part can be increased. This can be shortened, which is advantageous in increasing the operation speed. In addition, a highly integrated memory circuit portion in which a manufacturing defect easily occurs is formed on the first chip, and the chip size of the first chip is reduced to 100 mm ^2.
By doing so, the yield can be improved and the chip cost can be reduced.

In the IC memory according to the second invention, in the first invention, specifically, the first chip is connected to the second chip using bumps. For this reason, chips that are conventionally laid out two-dimensionally on the same plane are now connected by bumps by stacking chips, so that three-dimensional layout can be achieved, and signal lines connecting each part are provided. Can be shortened, which is advantageous for speeding up the operation. In addition, by forming a highly integrated storage circuit portion in which manufacturing defects easily occur on the first chip and reducing the chip size of the first chip to 100 mm ² or less, the yield can be improved and the chip cost can be reduced. Can be achieved.

An IC memory according to a third aspect of the present invention is the IC memory according to the first or second aspect, wherein the two n-type transistors formed on the semiconductor substrate are provided.
⁺ An element for absorbing surge, which is formed by forming an isolation oxide film region between diffusion regions, was formed on the second chip. From this, the memory cell array is formed on the first chip,
Since the element for absorbing the surge is formed on the second chip, it is possible to prevent an injection failure occurring in the memory cell array.

According to a fourth aspect of the present invention, in the IC memory according to the first to third aspects, the thickness of the semiconductor element formed on the first chip is reduced and the thickness of the semiconductor element formed on the second chip is increased. did. This makes it possible to separate the manufacturing processes of the first chip and the second chip, and to increase the film thickness of the semiconductor element formed on the second chip to which a surge or the like is likely to be input. It is possible to avoid a decrease in the surge withstand voltage at the input / output unit that occurs when the switching is performed.

An IC memory according to a fifth aspect of the present invention is the IC memory according to the fourth aspect, wherein the thickness of the gate oxide film of the transistor formed on the first chip is reduced and the IC memory is formed on the second chip. The thickness of the transistor gate oxide film was increased. From this, the manufacturing process of the first chip and the second chip can be separated, and a transistor formed on the second chip to which a surge or the like may be input uses a thick gate oxide film. The transistor formed on the first chip uses a transistor suitable for miniaturization of the gate oxide film. By doing so, it is possible to avoid a decrease in the surge withstand voltage in the input / output unit that occurs when the device is miniaturized.

According to a sixth aspect of the present invention, in the IC memory according to the first to fifth aspects, the wiring layer formed on the first chip is formed of a thin film, and the wiring layer formed on the second chip is formed of a thick film. Formed. From this, the manufacturing process of the first chip and the second chip can be separated, the first chip is formed of a thin film suitable for miniaturization, and the second chip does not need to be very fine. Therefore, it can be easily formed with a thick film. Therefore, the resistance of the wiring of the first chip can be reduced, and the wiring for connecting a circuit formed in a distant place is formed in the first chip and the circuit formed in a close place is connected. By forming the wiring on the second chip, the speed of the circuit can be increased.

According to a seventh aspect of the present invention, in the IC memory according to the first to sixth aspects, a decoupling capacitor is formed in an empty area of the second chip where no element is formed.
As a result, the empty area can be formed larger in the second chip than in the conventional case, so that a decoupling capacitor having a larger capacity than the conventional one can be formed. Capacitors can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit example of a multi-chip IC memory according to a first embodiment of the present invention.

FIG. 2 shows a case where chips 20, 30, 40, and 50 are replaced with a chip 60;
FIG. 7 is a diagram illustrating an example of a layout arranged above.

FIG. 3 is a schematic cross-sectional view showing a connection method for connecting a chip 20 on a chip 60.

FIG. 4 is a schematic diagram showing a structural example in an IC package of the IC memory according to the first embodiment of the present invention;

FIG. 5 is a circuit example showing a part of the address buffer 10 shown in FIG. 1;

FIG. 6 is a circuit example showing a part of the input / output circuits 6a to 6d shown in FIG.

FIG. 7 is a schematic block diagram showing a circuit example of an IC memory forming a conventional DRAM.

8 is a diagram showing a layout of each circuit when the DRAM shown in FIG. 7 is formed by one chip.

FIG. 9 is an IC formed by the chip 200 shown in FIG.
FIG. 3 is a diagram illustrating an example of a pin arrangement of a memory 150.

FIG. 10 is a schematic diagram showing a structural example in the IC package shown in FIG. 9;

FIG. 11 is a cross-sectional view of a chip showing a structural example of a field transistor.

[Explanation of symbols]

1 IC memory, 2a to 2d memory cell array,
3a-3d row decoder, 4a-4d column decoder and amplifier circuit, 5a-5d predecoder, 6
a to 6d input / output circuit, 7a to 7d control circuit, 8
Power supply circuit, 9 input buffer, 10 address buffer, 20, 30, 40, 50, 60 chips, 8
1 Bump

Claims (7)

[Claims] In a multi-chip type IC memory formed of a plurality of semiconductor chips, at least one first chip in which a storage circuit portion having a memory cell array is formed on a semiconductor substrate, and a signal is input from outside. An input circuit section, an output circuit section for outputting a signal to the outside, and a second chip having a power supply circuit section for supplying power to each internal circuit formed on a semiconductor substrate, wherein the first chip is provided on a second chip. An IC memory, wherein the IC memory is connected by being attached to the IC memory. 2. The method according to claim 1, wherein the first chip is formed by using bumps.
The IC memory according to claim 1, wherein the IC memory is connected on a chip. 3. The second chip is characterized in that an element for performing surge absorption is formed by forming an isolation oxide film region between two n ⁺ diffusion regions formed on a semiconductor substrate. The IC memory according to claim 1 or 2, wherein 4. The semiconductor device according to claim 1, wherein the thickness of the semiconductor element formed on the first chip is reduced and the thickness of the semiconductor element formed on the second chip is increased.
The IC memory according to any one of claims 1 to 3. 5. The method according to claim 1, wherein the thickness of the gate oxide film of the transistor formed on the first chip is reduced, and the thickness of the gate oxide film of the transistor formed on the second chip is increased. The IC memory according to claim 4, wherein 6. The semiconductor device according to claim 1, wherein the wiring layer formed on the first chip is formed of a thin film, and the wiring layer formed on the second chip is formed of a thick film. An IC memory according to any one of the above. 7. The second chip, wherein a decoupling capacitor is formed in an empty area.
The IC memory according to any one of claims 1 to 6.