JPH0992797A - Cell lay-out method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lay out memory cells as small as possible. SOLUTION: The size of a power supply block 42 is so decided that the value obtained by adding the width (3) of the block 42 and the width (2) of a memory block 41 becomes the magnification of natural number of a lattice interval in automatic layout and wiring. Even if the memory cell 410 is laid out without being conscious with the interval of the aligning interconnection, the terminal position of the memory can be aligned to the lattice by the dimensional regulation of the block 42. Thus, the limit by the interval is excluded to make it possible to perform the minimum lay-out of the cell 410.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell layout method for a semiconductor integrated circuit (LSI), for example, AS
IC (Application Specific I)
The present invention relates to a technique effectively applied to the cell layout of C).

[0002]

2. Description of the Related Art Among ASICs, a gate array method requires a transistor to be spread in a chip in advance, and only metal wiring is individually performed according to a user's request, so that the manufacturing period can be shortened. The advantage is that you can However, the gate array LS
In I, since the transistor applied thereto has a size suitable for forming an ordinary gate circuit, the transistor is too large to be integrated when forming an array-shaped circuit such as a memory. In that case, the chip occupying area becomes very large, and the amount of waste becomes large. Under such circumstances, generally, a high-density memory that is uniquely designed from the diffusion layer is installed in advance at a specific position of the chip. Regarding such technology, "ISCC (Insoc; InC)" issued in February 1989.
international Solid State C
17 of the "ircuit Conference" paper
It is described on pages 8 to 179.

[0003]

In the compiled system, which is an example of automatic placement and routing, a layout pattern is automatically generated by a program corresponding to the memory capacity (word, bit configuration) selected by the user. Therefore, although the number of terminals and the terminal positions differ depending on the number of bits of data input / output (I / O), it is necessary to always match the grid in the automatic placement and routing. Therefore, the width of the memory cell and the width of the power supply cell are set to be a natural multiple of the grid in the automatic placement and routing. Alternatively, the width of the memory block and the width of the power supply cell are set to be a natural multiple of the grid. By doing so, the layout pattern is generated such that the width of the column peripheral circuit block matches the natural number times the lattice spacing and the input / output terminals become the natural number multiple of the lattice spacing.

However, in the above method, since the memory cell size is determined in consideration of the lattice spacing, the size of the memory cell is limited by the lattice spacing. For example, although the memory cell can be made smaller by devising the layout, the size of the memory cell is actually limited by the lattice spacing, so that the memory cell cannot be laid out sufficiently small. Since a large number of memory cells are arranged in the semiconductor memory, the size of each memory cell greatly affects the layout area of the entire semiconductor memory.

An object of the present invention is to provide a technique for laying out memory cells as small as possible.

Another object of the present invention is to provide a technique for reducing the layout area of a semiconductor memory.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the size of the power supply block is determined so that the size of the width of the power supply block and the width of the memory block is a natural multiple of the lattice spacing in the automatic placement and routing.

The memory cells are laid out in a small size regardless of the lattice spacing in the automatic placement and routing, and the dimension obtained by adding the width of the power supply block and the width of the memory block is a natural multiple of the lattice spacing in the automatic placement and routing. Thus, the dimensions of the power supply block are determined.

At this time, the dimensions of the column system peripheral circuit block may be determined so that the width of the column system peripheral circuit block becomes equal to the dimension of the width of the power supply block and the width of the memory block. it can.

According to the above means, it is possible to determine the size of the power supply block such that the size of the width of the power supply block and the width of the memory block is a natural multiple of the lattice spacing in the automatic placement and wiring. Even if the memory cells are laid out without considering the lattice spacing, the terminal positions of the memory can be adjusted to the lattice by adjusting the dimensions of the power supply block, and the limitation due to the lattice spacing is eliminated in the layout of the memory cells. This allows a minimum layout of memory cells. Also, even if the memory cells are laid out as small as possible without considering the grid spacing, the terminal positions of the memory can be adjusted to the grid by adjusting the dimensions of the power supply block, which reduces the layout area of the semiconductor memory. Achieve

[0013]

FIG. 2 shows a chip layout of a semiconductor integrated circuit (LSI) to which a method according to an embodiment of the present invention is applied.

The LSI 5 shown in FIG. 2 is an ASIC, and functions as a logic LSI having a predetermined function, such as a data processing device, by connecting a plurality of modules by the inter-module connection wiring channel 15.
The plurality of modules are not particularly limited, but a random access memory (RAM) 11, a read only memory (ROM) 12, and the RAM 11 and RO.
It includes logic groups 13 and 14 capable of controlling M12. An input / output unit I / O is formed so as to surround the plurality of modules, and signals can be exchanged with the outside of the LSI via the input / output unit I / O.

Various terminals are provided on the plurality of modules, and the terminals are arranged on the semiconductor chip such that the terminals are located in the grid of the automatic arrangement wiring. For example, in FIG.
As shown in the relationship between AM11 and the grid, RAM11
The plurality of terminals DX provided in the above are laid out so as to match one of the plurality of lattices 30 indicated by +. The automatic placement and routing is performed based on the plurality of grids 30.

FIG. 4 schematically shows the wiring layout and the automatic connection between modules.

As shown in FIG. 4A, by designating two points out of a large number of regularly arranged lattices 30, the wiring 31 is laid out so as to connect the designated lattices. The length L of the wiring 31 is determined by the designated inter-lattice distance. In addition, the space between wirings and the wiring width W
Is determined based on the interstitial space according to the process conditions of the wiring.

As shown in FIG. 4B, logical group 1
3 and 14 are provided with terminals for connection, and between them,
Wiring is performed based on the logical connection information. This wiring is formed as a straight line connecting between adjacent lattices based on the inter-lattice space and the wiring width rule depending on the process condition of the wiring.

FIG. 5 shows the basic layout of the RAM 11.

As shown in FIG. 5, the RAM 11 includes a memory mat 46, a row decoder 43, and an R / W control circuit 4.
4 and a column system peripheral circuit 45. Memory mat 4
6 is not particularly limited, but a memory block 41 in which a plurality of static memory cells are arranged and a power supply block 42 for back-biasing the MOS transistor forming the memory cell are alternately arranged. Become. The row decoder 43 has a function of decoding a row address, and is formed by combining a plurality of row decoder blocks. Word selection of the memory mat is performed based on the decoding result. The R / W control circuit 44, based on a read / write signal from the outside, causes the column system peripheral circuit 4 to
By controlling 5, the read operation and the write operation are controlled. The column system peripheral circuit 45 includes a sense amplifier for amplifying memory cell data, a write amplifier for amplifying write data, and a column system selection switch.

FIG. 1 shows a detailed layout structure of the main part of the RAM 11.

The memory block 41 comprises a plurality of static memory cells (referred to simply as "memory cells") 410 arranged vertically and horizontally in a matrix. The power supply block 42 is arranged for each memory block 41, and the corresponding memory cell 4
The back bias of the MOS transistor included in 10 is performed. A column system peripheral circuit block 450 is arranged for each of the memory block 41 and the power supply block 42 arranged adjacent to the memory block 41. Each column system peripheral circuit block 450 includes DO (0), DO (1), DO
The output terminal indicated by (2) and DI (0), DI
Input terminals are provided as indicated by (1) and DI (2).

In FIG. 1, is a memory cell width, is a memory block width, is a power supply block width, is a column system peripheral circuit block width, and is a memory mat width.
The distance from the origin 9 to the output terminal DO (0) of bit number 0 is indicated by XDO (0), and the distance from the origin 9 to the input terminal DI (0) of bit number 0 is XD.
Represented by I (0). Furthermore, the distance from the origin 9 to the output terminal DO (1) of bit number 1 is XDO (1)
Input terminal D of bit number 1 from origin 9
The distance to I (1) is indicated by XDI (1). Furthermore, the output terminal DO of bit number 2 from the origin 9
The distance to (2) is indicated by XDO (2), and the distance from the origin 9 to the input terminal DI (2) of bit number 2 is indicated by XDI2 (1).

Here, the width of the memory cell and the width of the power supply cell are set so as to each be a natural number multiple of the grid, or
Alternatively, when laying out the memory block width and the width of the power supply cell to be a natural number multiple of the lattice, the size of the memory cell is limited by the lattice spacing, and therefore the layout is such that the memory cell is sufficiently small. Can not.

On the other hand, in this embodiment, the memory cell 410 is laid out as small as possible regardless of the grid 30 of the automatic placement and routing, and the size of the width of the power feeding block 42 and the width of the memory block 41 is added. The dimensions of the power supply block 42 are determined so as to be a natural multiple of the grid spacing in the automatic placement and routing. That is, even if the size of the memory cell 410 is determined without being aware of the automatic placement and routing grid, the width of the power supply block 42 and the memory block 41
The terminals of the RAM 11 can be matched with the grid in the automatic placement and routing by adjusting the size of the power feeding block 42 so that the size of the width and the width becomes a natural multiple of the grid spacing in the automatic placement and routing. Memory cell 41
By laying out 0s as small as possible, it is possible to reduce the width of the memory block 41 formed by arranging them in the vertical and horizontal directions, so that the layout area of the entire RAM can be reduced. The column system peripheral circuit block 450 corresponding to the memory block 41.
Is arranged. The width of the column system peripheral circuit block 450 is the same as the width of the power supply block 42 and the memory block 41.
Is equal to the width of and.

Next, the dimensions of each part when the number of columns of the RAM 11 is 16 will be described.

When the width of the memory cell 410 is 6.8 μm as a result of laying out the memory cell 410 in a small size, the width of the memory block 41 is 108.8 μm (=
6.8 × 16). The width of the power supply block 42 is adjusted to 15.1 μm under the condition that the sum of the width of the power supply block 42 and the width of the memory block 41 is a natural multiple of the lattice spacing in the automatic placement and routing. And
Since the width of the column system peripheral circuit block 450 is made equal to the size of the width of the power feeding block 42 and the width of the memory block 41, it is 123.9 μm (= 108.8).
+15.1). When the number of input / output bits of the RAM 11 is 3 bits, the width of the memory mat 46 is 371.
It is set to 7 μm (= 123.9 × 3).

Here, if the memory cell width and the power feeding cell width are laid out to be natural multiples of the lattice spacing, the memory cell width is 8.4 μm and the power feeding cell width is 14.7 μm. As compared with the method of the embodiment described above, the width of the power supply cell is narrowed, but the width of the memory cell is widened. In this case, the width of the column system peripheral circuit block is 8.4 × 16 + 14.7 = 149.1 μm. Therefore, by adopting the method of the above-described embodiment, 149.1-123. 9 = 25.2
Reduction of μm is possible.

When the grid spacing of the automatic placement and routing is 2.1 μm and it is indicated by 1 grid, the X coordinates of the data output terminal and the input terminal are as follows, and are matched with the grid in the automatic placement and routing.

That is, the X coordinate XDO (0) of the data output terminal of bit number 0 is set to 10 grid, and the X coordinate XDI (0) of the data input terminal of bit number 0 is 12.
X-coordinate XDO (1) of the data output terminal of bit number 1 is set to 69 grid (10 + 59), and the X-coordinate XDO of the data input terminal of bit number 1 is set.
(1) is 71 grid (12 + 59), and the X coordinate XDO (2) of the data output terminal of bit number 2 is 12
8grid, X of the data output terminal of bit number 2
The coordinate XDO (2) is set to 130 grid.

Next, the details of the layout of each part will be described.

FIG. 6 shows the flow of layout development of the RAM 11.

First, the memory cell 410 in the memory block 41 is laid out so that the size (height and width) of the memory cell 410 is as small as possible regardless of the grid in the automatic placement and wiring. The size of the row decoder block 430 and the size of the column system peripheral circuit block 450 that forms the column system peripheral circuit 45 are determined. The height of the row decoder block 430 is determined based on the height of one memory cell, but the width is adjusted to be as small as possible. In addition, the width of the column system peripheral circuit block 450 is determined based on the plurality of memory cells and the width of the power supply block 42. The height is adjusted to be as small as possible. Then, based on the width of the row decoder block 430 and the height of the column peripheral circuit block 450, R
The size of the R / W control circuit block 440 of the / W control circuit 44 is determined.

FIG. 7 shows the flow of layout pattern generation.

The layout pattern of the RAM 11 has regularity. That is, the layout pattern of the RAM 11 can be formed by repeatedly arranging and connecting a plurality of reference memory cells. The layout and connection of memory cells are
This can be done by executing a dedicated program for automatic placement and routing on a workstation or the like. For example, in the example shown in FIG. 6, when the number of words and the number of bits of the memory are input as parameters, the memory block, the column peripheral circuit block, the row decoder block, and the R / W are processed by the placement program and the wiring program. In the control circuit block, a layout pattern is generated by arranging cells and connecting cells. The layout pattern generation is performed in the order of the R / W control circuit block, the column system peripheral circuit block, the row decoder block, and the memory block, although not particularly limited.

FIG. 8 shows a method of arranging memory cells and the like.

As shown in FIG. 8A, the cell CEL
For each L, a terminal is provided on the edge portion thereof. Input terminal IN, output terminal OUT, input / output terminal IN /
OUT, high-potential-side power supply terminal Vcc, ground terminal GND
Etc. are included. Regarding the arrangement of the cells, the terminals are arranged in the cells to be combined with each other. That is, the terminals having the same function are arranged so as to overlap each other. For example, as shown in FIG. 8B, the lower right corner of the cell CELL (A) is located at the origin, and the cell CELL is located on the right terminal of the cell CELL (A).
The left terminal of (C) is arranged so as to overlap, and the cell CEL
The right terminal of L (B) is arranged so that the left terminal of the cell CELL (C) overlaps, and the lower terminal of the cell CELL (D) is arranged so as to overlap the cell CELL (A) upper terminal,
The left terminal of the cell CELL (E) is arranged so as to overlap the upper terminal of the cell CELL (B) and the right terminal of the cell CELL (D).

FIG. 9 shows a configuration example of the memory cell 410.

The memory block 41 shown in FIG.
As shown in FIG. 9, a plurality of word lines WL and a plurality of bit lines BL, BL * arranged so as to cross the word lines WL.
(* Means signal inversion) is provided, and a memory cell is formed corresponding to the intersection. Memory block 4
All of the plurality of memory cells forming 1 have the same configuration,
As a configuration example of one of them is representatively shown in FIG. 9, one memory cell 410 includes p-channel type MOS transistors Q1 and Q2 and n-channel type MOS transistors Q3, Q4, Q5 and Q6. Are combined. A p-channel MOS transistor Q1 and an n-channel MOS transistor Q3 are connected in series to form a first inverter, and a p-channel MOS transistor Q2 and an n-channel MOS transistor Q4 are provided.
And are connected in series to form a second inverter. First
The inverter and the second inverter are coupled in a loop shape to exert a data holding function. An n-channel type MOS transistor Q5 is provided between the coupling point of the MOS transistors Q1 and Q3 and the bit line BL.
An n-channel MOS transistor Q6 is provided between the coupling point of the transistors Q2 and Q4 and the bit line BL *. The gate electrodes of the MOS transistors Q5 and Q6 are coupled to the word line WL, and when the word line WL is driven to the high level based on the decoding result of the row address, the MOS transistors Q5 and Q6 are turned on, Data can be written to or read from the memory cell 410.

FIG. 10 shows a layout pattern of the memory cell 410.

Reference symbol L indicates a diffusion layer, reference symbol FG indicates a polysilicon layer for forming a gate electrode of a MOS transistor, reference symbol AL1 indicates a first-layer aluminum wiring, and reference symbol AL2 indicates. The second layer aluminum wiring is shown, and the third layer aluminum wiring is shown by AL3. Diffusion layer L and first layer aluminum wiring A
L1 is connected by a through hole CONT,
Layer aluminum wiring AL1 and second layer aluminum wiring A
The second layer aluminum wiring AL2 and the third layer aluminum wiring AL3 are coupled to L2 by a through hole TC.
And are connected by a through hole UC. The characteristic of this memory cell layout is the shape of the polysilicon layer FG for making the memory cell width as narrow as possible. That is, in order to make the memory cell width as narrow as possible, the MO
In the formation portion of the S transistors Q1, Q2, Q3 and Q4, the polysilicon layer FG is bent and formed inward. As a result, the distance between the forming portion of the MOS transistor Q1 and the forming portion of the MOS transistor Q2 and the distance between the forming portion of the MOS transistor Q3 and the forming portion of the MOS transistor Q4 are narrowed. Further, as the spacing between the MOS transistor forming portions is narrowed in this way, the through hole forming portions 101 and 102 in the polysilicon layer are not formed into a quadrangle, but the corners thereof are covered, so that an adjacent polysilicon layer is formed. A certain distance is secured between them.

In the MOS transistor, the back bias must be supplied for stable operation.
That is, in the case of the n-channel MOS transistor, as shown in FIG. 11A, the P-well (P-
The back bias is supplied to the (WELL) region, and in the case of the p-channel type MOS transistor, the back bias is supplied to the N- substrate (N-sub) as shown in FIG. If the circuit for supplying the back bias is formed in each memory cell, the size of the memory cell is inevitably increased. Therefore, in this embodiment, the circuit for supplying the back bias is provided in each memory cell. The back bias is supplied to the MOS transistor by the power supply block 42 (see FIG. 1) formed separately from the memory cell without forming the circuit.

FIG. 12 shows the relationship between the memory block 41 and the power feeding block 42.

The power supply block 42 is composed of a plurality of power supply cells 421 corresponding to the memory cells 410. One power supply cell 421 commonly supplies a back bias to a plurality of memory cells 410 corresponding thereto. Since one memory cell 410 includes an n-channel type MOS transistor and a p-channel type MOS transistor, it has a P-well (P-WELL) and an N-substrate (N-s).
ub) and. The memory cells are arranged in the direction along the bit line so that the P-well (P-WELL) and the N-substrate (N-sub) are shared between adjacent memory cells. P-well (P-W
The ELLs or the N- substrates (N-subs) are laid out so as to face each other.

13 and 14 show the relationship between the memory cell and the power supply cell. Note that in FIG. 13, a part of the power supply vertical trunk line (formed by the second layer aluminum wiring AL2) shown in FIG. 14 is omitted.

High potential side power source Vcc line (Vcc-LI
NE) is formed by the third-layer aluminum wiring AL3, and the potential of the high-potential-side power supply Vcc line is supplied to the N- substrate (N-sub) via the power supply cell 421.
That is, the third layer aluminum wiring AL3 is coupled to the second layer aluminum wiring AL2 by the through hole UC, and the second layer aluminum wiring AL2 is connected to the through hole TC.
Is coupled to the first-layer aluminum wiring AL1 and the first-layer aluminum wiring AL1 is coupled to the diffusion layer N ⁺ by the through hole CONT, so that the back bias is supplied to the p-channel MOS transistor.

The ground line GND (GND-L
INE) is formed by the first-layer aluminum wiring AL1, and the ground potential of the first-layer aluminum wiring AL1 is a P-well (P-WEL) via the power supply cell 421.
L). That is, the back bias is supplied to the n-channel type MOS transistor by being coupled to the diffusion layer P ⁺ by the first layer aluminum wiring AL1 through hole CONT.

FIG. 15 shows a configuration example of a column system peripheral circuit block.

Since a plurality of column-system peripheral circuit blocks forming the column-system peripheral circuit 45 have the same structure, the structure of one of them is representatively shown in FIG. The column system peripheral circuit block 450 arranged corresponding to the memory block 41 includes a plurality of column selection circuits corresponding to the bit line pairs. This column selection circuit includes p-channel MOS transistors Q10 and Q11 for selectively coupling a bit line pair to a read common line RCOM, and a p-channel MOS transistor for selectively coupling a bit line pair to a write common line WCOM. Type MOS transistors Q12 and Q13. The operation of the MOS transistors Q10, Q11, Q12, Q13 is controlled based on the read / write signal and the decoding result of the column address. That is, when the read operation is instructed by the read / write signal, the MOS transistor Q is generated based on the decoding result of the column address.
When the operation control of 10 and Q11 is performed and the MOS transistors Q10 and Q11 are turned on, the bit line pair is selectively coupled to the read common line RCOM. In addition, when the write operation is instructed by the read / write signal, the MO based on the decoding result of the column address.
The operation control of the S transistors Q12 and Q13 is performed, and M
When the OS transistors Q12 and Q13 are turned on,
The bit line pair is selectively coupled to the write common line WCOM. A memory sense circuit 51 is coupled to the read common line, and after the memory cell data read to the read common line RCOM is amplified by the memory sense circuit 51, the output buffer 52 in the subsequent stage and the bit number 0.
The output terminals DO (0) and DO (0) can be externally output. The memory write 53 is coupled to the write common line WCOM. This memory light 53
Includes a write amplifier for amplifying the write signal,
The write data taken in via the input terminal DI (0) of bit number 0 is transmitted to the write common line WCOM via the memory write circuit 53.

According to the above embodiment, the following operational effects can be obtained.

(1) The size of the power supply block 42 plus the width of the memory block 41 is set to be a natural number multiple of the lattice spacing in the automatic placement and routing.
By deciding the size of the above, even if the memory cell 410 is laid out without considering the grid interval in the automatic placement and wiring, the terminal position of the memory can be matched with the grid by adjusting the size of the feeding block 42. As described above, in the layout of the memory cell 410, the restriction due to the lattice spacing is removed, and thus the minimum layout of the memory cell 410 is possible.

(2) Regardless of the grid spacing in the automatic placement and routing, the memory cell 410 is laid out small, and the size of the width of the power supply block 42 and the width of the memory block 41 is the grid spacing in the automatic placement and routing. By determining the size of the power supply block 42 so as to be a natural multiple of, even if the memory cell 410 is laid out as small as possible without considering the lattice spacing, the terminal DO ( 0), D
The position of I (0) can be matched to the grid. As a result, the layout area of the semiconductor memory can be reduced.

(3) Then, the width of the column system peripheral circuit block 450 is equal to the width of the power supply block 42 plus the width of the memory block 41.
By determining the dimensions of the column system peripheral circuit block, the positions of the terminals DO (0) and DI (0) can be easily adjusted to the grid in the automatic placement and routing.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes.

For example, although the layout of the RAM module has been described in the above embodiment, the ROM module can be similarly laid out.

In the above description, the invention made by the present inventor is the field of application which is the background of the invention.
Although the present invention is applied to C, the present invention is not limited thereto, and a memory L configured by one chip as a semiconductor memory is used.
It can be applied to SI and the like.

The present invention can be applied on condition that at least a MOS transistor is included.

[0058]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the size of the power supply block is determined so that the size of the width of the power supply block and the width of the memory block is a natural multiple of the grid space in the automatic placement and routing, and the grid space is not taken into consideration. Even if the memory cell is laid out in, the terminal position of the memory can be adjusted to the grid by adjusting the size of the power feeding block. In this way, in the layout of the memory cell, the limitation due to the lattice spacing is removed, so that the minimum layout of the memory cell is possible.

Further, regardless of the lattice spacing in the automatic placement and routing, the memory cells are laid out in a small size, and the sum of the width of the power feeding block and the width of the memory block is a natural number times the lattice spacing in the automatic placement and routing. By determining the dimensions of the power supply block so that even if the memory cell is laid out as small as possible without considering the grid spacing, the terminal position of the memory can be adjusted to the grid by adjusting the size of the power supply block. it can. As a result, the layout area of the semiconductor memory can be reduced.

[Brief description of drawings]

FIG. 1 is a layout explanatory diagram of a main part in a RAM to which a method according to an embodiment of the present invention is applied.

FIG. 2 is a diagram illustrating a chip layout of a semiconductor integrated circuit including the RAM.

FIG. 3 is an explanatory diagram of a relationship between the RAM and a grid for automatic placement and wiring.

FIG. 4 is an explanatory diagram of a wiring layout and inter-module automatic connection in the semiconductor integrated circuit.

FIG. 5 is an overall layout explanatory diagram of the RAM.

FIG. 6 is an explanatory diagram of the layout development of the RAM.

FIG. 7 is an explanatory diagram of the layout pattern generation of the RAM.

FIG. 8 is an explanatory diagram of a cell arrangement method in the RAM.

FIG. 9 is a circuit diagram of a configuration example of a memory cell in the RAM.

FIG. 10 is an explanatory diagram of a layout pattern of the memory cell.

FIG. 11 is a cross-sectional view of a MOS transistor that constitutes the memory cell.

FIG. 12 is an explanatory diagram of a relationship between a memory block and a power feeding block in the RAM.

FIG. 13 is an explanatory diagram of a relationship between the memory cell and a corresponding power supply cell.

FIG. 14 is an explanatory diagram of a relationship between the memory cell and a corresponding power supply cell.

FIG. 15 is a circuit diagram showing a configuration example of a column system peripheral circuit block in the RAM.

[Explanation of symbols]

 5 LSI 11 RAM 12 ROM 13 and 14 Logic Group 15 Module Wiring Channel 41 Memory Block 42 Power Supply Block 43 Row Decoder 44 R / W Control Circuit 45 Column Peripheral Circuit 46 Memory Mat 51 Memory Sense Circuit 52 Output Buffer 53 Memory Write circuit 410 Memory cell 430 Row decoder block 440 R / W control circuit block 450 Column peripheral circuit block

Claims (3)

[Claims] 1. A memory block is configured by arranging a plurality of memory cells each including a MOS transistor vertically and horizontally, and a power supply block for supplying a back bias to the MOS transistor is arranged adjacent to the memory block. In the cell layout method for a semiconductor integrated circuit, the size of the power supply block is determined so that the size of the width of the power supply block and the width of the memory block is a natural multiple of the lattice spacing in the automatic placement wiring. A cell layout method characterized by the above. 2. A memory block is formed by arranging a plurality of memory cells each including a MOS transistor vertically and horizontally, and a power supply block for supplying a back bias to the MOS transistor is arranged adjacent to the memory block. In the cell layout method for a semiconductor integrated circuit, the memory cells are laid out small regardless of the grid spacing in the automatic placement and routing, and the dimension of the width of the power supply block and the width of the memory block is the grid in the automatic placement and routing. A cell layout method, characterized in that the dimensions of the feed block are determined so as to be a natural multiple of the interval. 3. When a column peripheral circuit is arranged corresponding to the memory block, the width of the column peripheral circuit block is equal to the sum of the width of the power supply block and the width of the memory block. 3. The cell layout method according to claim 1, wherein the dimensions of the column system peripheral circuit block are determined so that