KR100222328B1 - Basic cell architecture for mask programmable gate array - Google Patents

Abstract

The present invention relates to a highly efficient CMOS cell structure for use in metal mask programmable gate arrays such as multiple gated gate arrays. In the basic cell according to the exemplary embodiment of the present invention, three or more N-channel transistors 24-35 and three or more P-channel transistors 18-23 and 36-41 are used. The large transistor is included in the driver 12 of the cell and the small transistor is included in each calculator 12 of the cell. The specific transistors of the calculator and driver and the devices of the calculator and driver can use silicon very efficiently and form various macrocells.

Description

[Name of invention]

Base Cell Design for Mask-Programmable Gate Arrays

Detailed description of the invention

[Reference to Related Application]

This application relates to pending patent application No. 5,055,716 and to pending application 07 / 524,183, entitled Abbas E1 Game1, "Basic Cell for BiCMOS Gate Array," incorporated herein by reference.

[Field of Invention]

TECHNICAL FIELD The present invention relates to integrated circuits, and more particularly, to integrated circuits for application purposes that include programmable gate arrays.

[Background of invention]

In general, a programmable gate array containing more than one million transistors is often used to design economical integrated circuits (ASICs). The programmable gate array may be metal mask programmable, electrically programmable or laser programmable. In the case of a mask programmable gate array, a silicon die with unconnected transistors is termed a master slice or master image. A user who wishes to change the master slice creates an ASIC by selectively interconnecting the transistors in the gate array using a specific logic circuit structure (macrocell) included in the macrocell library and a known software program.

In the case of one type of metal mask programmable gate array, an array of cells is formed on a chip where each cell consists of a number of unconnected elements. In a general apparatus, since each cell includes various types of elements, the macrocell designer can design various types of logic circuits in each cell or by using a combination of cells. Ideally, each cell should be an optimal number of variations so that users can design different macrocells using the shortest interconnects, the smallest die area, and other techniques to achieve the high performance of each macrocell. The device must be provided.

In a programmable gate array structure, CMOS transistors typically have cell elements in accordance with the low power consumption of CMOS devices, with N-channel MOSFETs and P-channel MOSFETs connected in series between the power supply and ground. Since the gates of these CMOS transistors are commonly connected, the other transistor is turned off while one transistor is on, thereby preventing the formation of a low impedance path between the power supply and ground. Such a CMOS transistor may be used as a component of various macrocells.

A conventional CMOS gate array cell is shown in FIG. 1, which includes multiple N-channel transistors 2 of the same size and multiple P-channel transistors 4 of the same size. Such cells are insufficient for the implementation of memory devices such as D flip-flops and SRAM cells, and their output driving functions are very limited. The size of transistors commonly used in cells of the prior art is unnecessarily large to drive nets with one or two smaller outs, for example, but insufficient to drive nets with fan outs greater than five, for example. The result of an unnecessarily large transistor size to drive less fan out is that the relatively large input capacitance of the logic macrocell causes high dynamic power dissipation and high load on the clock net.

Typical transistors are too small to adequately drive more than 5 fanouts, so two or more macro cells must be connected in parallel or a separate buffer must be included in the design. As a result, large macro cells cause inefficient chip area utilization and increase interconnect length.

In the prior art, CMOS gate array cells having two different size N-channel transistors are used to improve the efficiency of SRAM cell implementation. The smaller N-channel transistors are generally smaller than one third of the larger N-channel transistors. Such prior art cells may also include small sized P-channel transistors to perform various functions. However, in such cells, large transistors are still unnecessarily suitable for driving large fanout nets, and small transistors are not suitable for driving almost all nets. In general, in prior art devices that drive many fan out nets, two or more macrocells must be connected in parallel or have separate buffers.

In the prior art, small transistors used in SRAMs are generally not used to implement logic macrocells such as D flip-flops, so there are areas of inefficiency in such logic macrocells. In addition, the input capacitance of the macrocell is generally unnecessarily high.

[Overview of invention]

This article describes a highly efficient CMOS cell structure for use in metal mask programmable gate arrays such as multiple gated gate arrays. In a basic cell according to an embodiment of the present invention, three or more sized N-channel transistors and three or more sized P-channel transistors are used. Large transistors are included in the drive of the cell and small transistors are included in the computation of the cell. Large transistors are used to drive many fanout nets and even perform logic functions, while small transistors are used to implement SRAM cells and logic functions and drive fewer fanout nets.

The arrangement of specific transistors in the summing and driving section and transistors in the calculating and driving section makes it possible to use silicon very effectively and form various macro cells.

[Brief Description of Drawings]

1 is a diagram showing a basic cell of the prior art.

2 shows a schematic base cell for a good cell in a plurality of mask programmable gate structures.

3 (a) and 3 (b) show an SRAM constructed using a single calculation unit of the cell of FIG.

4 through 7 illustrate various logic circuits or macro cells that may be implemented in the cell structures and layouts shown in FIGS. 2 and 8.

8 (a) and 8 (b) show the sample tiles of the calculation and driver in a plurality of mask programmable gate structures.

9 is a preferred design of a single calculation unit in the basic cell structure of FIG.

10 (a) to 10 (c) show a drive unit that can be used in connection with the calculation unit of the present invention.

11 is a diagram illustrating a basic cell according to the present invention.

12 illustrates an ASIC device including a gate array.

Detailed Description of the Preferred Embodiments

A preferred embodiment of the present invention is shown in FIG. 2, wherein a single mask programmable gate array cell may include one or more calculators 6, 8, 10, and may include a driver 12 or a driver. Can be shared with other cells. The mask programmable gate array cell shown in FIG. 2 includes N channel transistors having three different sizes and P channel transistors having three different sizes. The large N-channel transistors 14 and 15 and the large P-channel transistors 16 and 17 are disposed in the driver 12 and have a wider channel pole than the transistors of the calculators 6, 8, and 10. The medium P-channel transistors 18-23 and the medium N-channel transistors 24-29 are almost half the size of the large P and N channel transistors 14-17. The small N-channel transistors 30-35 are between about 1/2 and 1/3 the size of the medium P and N channel transistors 18-29, and the small P-channel transistors 36-41 are small N Smaller than the channel transistors 30-35. The specific channel width and length (W / L) used in the preferred embodiment is shown in FIG. Each calculation part 6, 8, 10 is preferably the same.

The cell of the embodiment shown in FIG. 2 includes three arithmetic units 6, 8, 10 and one driver 12, but a certain number of calculators and drivers may be arranged in close proximity to one another to form a single cell. have. A single calculation section 6 or 8 or 10 comprises two medium N-channel transistors (e.g. 24, 25), two small N-channel transistors (e.g. 30, 31), two medium P-channel transistors (e.g. 18, 19) and Two small P-channel transistors (eg, 36, 37).

The small and medium transistors of the two calculators can be used to implement two SRAM cells with six transistors, one of which is shown in FIG. 3 (a). In FIG. 3 (a), the small P-channel transistors 36 and 37 are used as pull-up transistors of the butters 50 and 52 which are CMOS, and the medium N-channel transistors 24 and 25 are inverters 50 and 52. Used as a pull-down transistor. This is shown in FIG. 3 (b), which shows a CMOS inverter 50 or 52. The small N-channel transistors 30 and 31 are used as pass transistors in the SRAM of FIG. 3 (a).

The D flip-flop of FIG. 4 may be constructed using the entire cell of FIG. 2 having three calculation units. Each inverter is formed using a medium P channel transistor (or a medium P channel transistor connected in parallel with one small P channel transistor) and a medium N channel transistor. Other transistors used in FIG. 4 are shown in relative magnitude.

Macrocells for driving fewer fan out nets (eg, one or two nets) can be implemented using medium and small transistors, such as the NAND gate of FIG. 5 using only one computational unit. In FIG. 5, the N-channel transistors 60 and 62 connected in series are medium. The small and medium P channel transistors 64, 66 are connected in parallel for additional drive functions.

Macrocells for driving ordinary fan out nets (e.g., three to five) are included as logic elements in the drive, such as large N and P channel transistors 70 and 72, as shown by the four-input AND gate of FIG. Additional large N and P channel transistors may be used.

In order to drive many fan out nets (e.g., more than five nets), the transistors of two or more drives may be present in parallel as shown in FIG. 7, including large transistors 74-77.

As shown, the specific elements included in each computation of the cell make use of silicon very effectively. In addition to the large reduction in area by using small and medium transistors to implement logic macrocells, the use of such transistors reduces the input capacitance load of the macro cells compared to conventional gate arrays. This is particularly useful for reducing the load on the clock net and dynamic power dissipation.

The diffusion junctions and polysilicon between the elements of each computational section of the cell are chosen to ensure the routeability between the transistors in one or more cells forming the macrocell. This is considered important because the transistor size of the computational section is much smaller than in conventional gate array cells, which makes the interconnection between the transistors of the cell more difficult.

The number of calculations relative to the number of driving parts of the cell is chosen to optimize the density of available gates (ie, the number of gates per unit area). If the ratio of the computational unit to the driving unit is low, there is an advantage of high driving, while implementing a macro cell having a low driving requirement such as a large macro cell such as a D flip-flop and an SRAM cell wastes an area. On the other hand, when the ratio of the calculation unit to the driving unit is high, it is somewhat effective to implement a low driving macro cell and a D flip-flop, but is effective to implement a small macro cell (eg, a cell having a two-input gate) and a high driving macro cell. Is not The optical ratio of the cell's computational unit to the driver's depends on the statistics of the macrocell usage of the objective design and the logical mapping method.

Using an experimental approach, we determined the ratio of the three computational units for each drive to achieve the best area utilization as shown in FIG. However, if the macrocell usage statistics of the target design change, the optimal ratio changes. In fact, it is useful to use more than one ratio for the same master image. This is illustrated in Figs. 8 (a) and 8 (b), wherein Fig. 8 (a) has three calculation units (e.g. 80, 81, 82) associated with one drive unit (e.g. 83). Figure 8 (b) shows a uniform master image, with figure 8 (b) having four calculations (e.g. 84-87) or two calculations (e.g. 88, 89) associated with a single drive (e.g. 90 or 91 respectively). Show non-uniform master image.

A preferred layout of each calculation unit shown in FIG. 2 is shown in FIG. The transistor in FIG. 9 is named so as to match the transistor in the calculation section in FIG. As shown in FIG. 9, a single polysilicon gate 100 is used to control transistors 18, 36, 24, and a single polysilicon gate 102 to control transistors 19, 37, 25. Is used. Separate gates 104 and 106 control the N-channel transistors 30 and 31 to allow these transistors to operate independently, like the pass transistors 30 and 31 used in the SRAM of FIG. N and P type source / drain diffusions of the various transistors are shown as hatched regions in FIG. As shown, the central diffusions of the medium and small P-channel transistors are commonly manufactured by the diffused P-type connector portion 110.

The structure in FIG. 9 can be formed by known conventional techniques.

By replacing the large P-channel transistor of the driver 12 of FIG. 2 with an NPN bipolar transistor, a BiNMOS driver is added to the output terminal of the macrocell, which can greatly improve performance.

A driver comprising two NPN bipolar elements to implement a full BiCMOS buffer or a driver comprising one NPN bipolar transistor and a PNP bipolar transistor to implement a complementary BiCMOS buffer will be used with the described calculations. It may be. 10 (a) to 10 (c) show three examples of a drive that can be used in the cell of the present invention.

The basic cell described herein is set forth in FIG. 11 and essentially comprises one or more calculators including small and medium transistors and one or more drivers including large transistors and / or bipolar transistors. If the driver of the cell of FIG. 11 is removed and the transistor of the calculator is made somewhat larger to drive a larger load, the resulting cell would be highly desirable.

FIG. 12 shows an ASIC 120 comprising an array 124 composed of cells such as the cells of FIGS. 2, 8, and 11, which may or may not be metalized. In this ASIC, the chip region outside the array 124 may include other circuitry connected to interact with the array 124. ASIC 120 may also include multiple arrays 124.

The main differences between the computational unit described herein and the computational unit mainly described in my application No. 07 / 524,183 issued to patent 5,055,716 are: 1) addition of small P channel transistors in each computational unit: 2) medium P channel transistors Does not require that it has a smaller current processing capability than a small N-channel transistor: 3) reduction in the size of each computational section, and 4) details of polysilicon and diffusion preliminary connections.

While specific embodiments of the invention have been shown and described, it will be apparent to those skilled in the art that changes and modifications can be made without departing from the invention and the appended claims are within the scope and modifications and variations of the invention in accordance with the spirit and scope of the invention. I understand that you can.

Claims (20)

In a base cell in the mask programmable gate array before the transistors of the gate array are interconnected in a programming step, the base cell has MOS transistors connected to other transistors, the one or more calculations being substantially identical to each other and substantially rectangular. One of which is substantially larger than any MOS transistor of the unit and the at least one calculation unit and having at least one MOS transistor connected to another transistor and having a gate separated from the gate of the MOS transistor of the calculation unit and being substantially identical to each other and rectangular. One or more of the plurality of basic cells located in the gate array, each calculation unit having a size corresponding to a channel width, and at least two small N channel transistors having a common N type. At least two small N-channel transistors and at least two medium N-channel transistors sharing an acid dopant region and at least two small N-channel transistors and at least two small P-channel transistors sharing a common N-type diffusion dopant region are common P-type At least two small P-channel transistors sharing a diffusion dopant region and at least two medium P-channel transistors comprising at least two medium P-channel transistors sharing a common P-type diffusion dopant region, wherein the small N-channel and P-channel transistors Has a narrower channel width than the medium N channel and P channel transistors, respectively, wherein at least one gate of the small N channel transistor is separated from the gate of the medium N channel transistor. The base cell of claim 1, wherein the medium N-channel and P-channel transistors are at least twice as large as the small N-channel and P-channel transistors, respectively. 2. The basic device of claim 1, wherein the gate of one of the small P-channel transistors, the gate of one of the medium P-channel transistors, and the gate of one of the medium N-channel transistors are commonly formed and connected to each other. Cell. The at least one MOS transistor of claim 1, wherein the at least one MOS transistor of the at least one driver includes at least one large N-channel transistor and at least one large P-channel transistor, wherein a size corresponds to a channel width and the at least one large N. And the channel transistor and the at least one large P channel transistor have a channel width greater than each channel width of the medium N channel and P channel transistor. The method of claim 1, wherein the at least one MOS transistor of the at least one driver includes at least one large N channel transistor, wherein a size corresponds to a channel width, and the at least one large N channel transistor is the medium N channel transistor. Wherein the at least one driver also includes at least one bipolar transistor for providing a pull-up driving function. In a basic cell in the mask programmable gate array before the transistors of the gate array are interconnected in a programming step, the cells comprise one or more small P channel transistors, one or more medium P channel transistors, one or more of size corresponding to a channel width; At least one calculator comprising a small N-channel transistor and at least one medium N-channel transistor, wherein the medium P-channel transistor has a channel width that is at least nearly twice the channel width of the small P-channel transistor, and the medium N-channel transistor. Has a channel width that is nearly twice the channel width of the small N-channel transistor, wherein the small P-channel transistor has a channel width smaller than that of the small N-channel transistor, wherein the gate of one of the small P-channel transistors and the medium P channel are smaller. T The gate of one of the jitter and the gate of one of the medium N channel transistors are commonly connected by polysilicon, and the gate of the small N channel transistor is connected from the gates of the small and medium P channel transistors and the gate of the medium N channel transistor. Basic cell, characterized in that separated. 7. The base cell of claim 6, wherein the source regions of the at least one small P channel transistor and the at least one medium P channel transistor are connected by P type diffusion. 7. The apparatus of claim 6, further comprising one or more drivers having one or more transistors having a greater current drive function than the transistors of the one or more calculators and having a gate separate from the gate of the transistor of the one or more calculators. Primary cell. 10. An ASIC comprising an array of cells, each cell having a MOS transistor coupled to another transistor, said cells being substantially larger than and substantially larger than any MOS transistor of said at least one calculation unit and said at least one calculation unit. A negative one having at least one MOS transistor connected to another transistor and having a gate separate from a gate of said MOS transistor, said at least one driver being substantially identical to each other and having a rectangular shape and located inside said array, each The calculation unit has a size corresponding to a channel width, and at least two small N-channel transistors and at least two medium N-channel transistors in which at least two small N-channel transistors share a common N-type diffusion dopant area share a common N-type diffusion dopant area. doing Two or more of the small N-channel transistor and the at least two small P-channel transistors share a common P-type diffusion dopant region, and two or more of the small P-channel transistor and the at least two medium P-channel transistors share a common P-type diffusion dopant region And the small P-channel transistors, wherein the small N-channel and P-channel transistors have a narrower channel width than the medium N-channel and P-channel transistors, respectively, and the gate of the one or more small N-channel transistors is the medium N-channel transistor. ASIC, characterized in that separated from the gate. 10. The method of claim 9, wherein the at least one MOS transistor of the at least one driver includes at least one large N-channel transistor and at least one large P-channel transistor, wherein a size corresponds to a channel width, and the at least one large N. And the channel transistor and the at least one large P channel transistor have a channel width greater than each channel width of the medium N channel and P channel transistor. 10. An ASIC comprising an array of cells, each cell having one or more small P channel transistors, one or more medium P channel transistors, one or more small N channel transistors, and one or more medium N channel transistors, the size of which corresponds to a channel width. Wherein the medium P channel transistor has a channel width that is at least nearly twice the channel width of the small P channel transistor, and the medium N channel transistor is about twice the channel width of the small N channel transistor. Has a channel width, the small P channel transistor has a smaller channel width than the small N channel transistor, a gate of one of the small P channel transistors, a gate of one of the medium P channel transistors, and one of the medium N channel transistors. Gates are made of polysilicon Cylinder is connected to a gate of said small N-channel transistors are ASIC, characterized in that the separated medium from the gate of the N channel transistor and the gate of the small and medium-sized P-channel transistor. The method of claim 1, wherein each of the one or more drivers includes a plurality of transistors used as pull-up transistors of a single macrocell and a plurality of transistors used as pull-down transistors of the single macrocell, and the plurality of pull ups and pull-downs. And a transistor can be programmatically connected to provide various output drive functions to the macrocell. The plurality of pull-down transistors of claim 1, wherein each of the one or more drivers includes one or more transistors used as pull-up transistors of a single macrocell and a plurality of transistors used as pull-down transistors of the single macrocell. A basic cell can be programmatically connected to provide various output drive functions to the macro cell. The plurality of pull-up transistors of claim 1, wherein each of the one or more drivers includes a plurality of transistors used as pull-up transistors of a single macro cell and one or more transistors used as pull-down transistors of the single macro cell. A basic cell can be programmatically connected to provide various output drive functions to the macro cell. 9. The apparatus of claim 8, wherein each of the one or more drivers includes a plurality of transistors used as pull-up transistors of a single macro cell and a plurality of transistors used as pull-down transistors of the single macro cell. A pull down transistor may be programmablely connected to provide a variety of output driving functions to the macro cell. The method of claim 8, wherein each of the one or more drivers includes one or more transistors used as pull-up transistors of a single macrocell and a plurality of transistors used as pull-down transistors of the single macrocell, and the plurality of pull-down transistors. A basic cell can be programmatically connected to provide various output drive functions to the macro cell. 10. The plurality of pull-up transistors of claim 8, wherein each of the one or more drivers includes a plurality of transistors used as pull-up transistors of a single macro cell and at least one transistor used as pull-down transistors of the single macro cell. A basic cell can be programmatically connected to provide various output drive functions to the macro cell. 10. The apparatus of claim 9, wherein each of the one or more drivers includes a plurality of transistors used as pull-up transistors of a single macro cell and a plurality of transistors used as pull-down transistors of the single macro cell. A pull down transistor may be programmablely connected to provide a variety of output driving functions to the macro cell. The plurality of pull down transistors of claim 9, wherein each of the one or more drivers includes one or more transistors used as pull-up transistors of a single macrocell and a plurality of transistors used as pull-down transistors of the single macrocell. A basic cell can be programmatically connected to provide various output drive functions to the macro cell. The plurality of pull-up transistors of claim 9, wherein each of the one or more drivers includes a plurality of transistors used as pull-up transistors of a single macro cell and one or more transistors used as pull-down transistors of the single macro cell. A basic cell can be programmatically connected to provide various output drive functions to the macro cell.