JPH09162302A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize the threshold voltage of a MISFET by increasing the integration of a semiconductor integrated circuit in which the MISFET is mounted on a major surface of a device forming region. SOLUTION: In a semiconductor integrated circuit device, a source region and a drain region of a MISFET Qp (on Qn) are provided at a part of a major surface of a device forming region of an island region 3A (or 3B). A power- supply contact region 10A (or 9A), which is electrically connected to a channel forming region of the MISFET Qp (or Qn), is formed at another part of the major surface of the device forming region of the island region 3A (or 3B).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to forming an island region, which is isolated from other regions, on the main surface of an element forming region of a semiconductor substrate. the main surface to the MISFET of (M etal I nsulato
The r S emiconductor F ield E ffect T ransistor) to a semiconductor integrated circuit device to the tower.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, a so-called S in which a semiconductor layer is formed on a supporting substrate with a substrate insulating film interposed therebetween.
OI using (S ilicon O n I nsulator) semiconductor substrate structure to form an island region defined around an insulating film in the element formation region of the semiconductor substrate, separation techniques for isolation between element formation region A study is underway. For example, Japanese Patent Application No. 4-145192 discloses a substrate insulating film formed between a supporting substrate and a semiconductor layer, a field insulating film formed on the main surface of an element isolation region of a semiconductor substrate, and a field insulating film. A separation technique (1) has been disclosed in which the periphery of the island region is defined by each of the buried insulating films embedded in the separation groove reaching the substrate insulating film, and the element formation regions are insulated and separated. Also,
Solid State Technology / Japan version issued by Japan SST Co., Ltd. (January 1991 / Sol
id State Technology / Japan version), "Ultra-thin film SOI for high-speed submicron COMS technology", pages 26 to 32, a substrate insulating film formed between a supporting substrate and a semiconductor layer, a semiconductor substrate. Isolation technology for isolating and separating the element formation regions by defining the periphery of the island region with each of the field insulation films formed on the main surface of the element isolation region and contacting the lower part of the field insulation film with the substrate insulation film (2) Is disclosed. Since these isolation techniques can completely insulate the element formation regions from each other, the power consumption of the semiconductor integrated circuit device and the operating speed can be increased.

[0003]

The semiconductor integrated circuit device under development by the present inventor has a MISFET mounted thereon. MISF
ET is formed on the main surface of the element formation region of the semiconductor substrate, and its channel formation region is composed of the well region formed in the element formation region.

The channel forming region of the MISFET is
The potential is fixed for the purpose of stabilizing the threshold voltage. For example, the operating potential range of the MISFET is 0 to +5.
In the case of [V], the channel formation region of the p-channel MISFET is fixed to a positive potential of +5 [V] or higher, and the channel formation region of the n-channel MISFET is fixed to a negative potential of 0 [V] or lower.

The potential of the channel forming region of the MISFET is usually fixed by a fixed potential supplied through a power supply contact region electrically connected to the well region which is the channel forming region. The power supply contact region is composed of a semiconductor region of the same conductivity type as the well region, and is electrically connected to each channel forming region of the plurality of MISFETs.

However, when the island region is formed on the main surface of the element forming region of the semiconductor substrate by the above-mentioned separation technique (1),
Since the well region is divided into island regions, a power supply contact region must be provided for each island region. Therefore, the plane size of the island region is increased by the amount corresponding to the occupied area of the power supply contact region, and the integration degree of the semiconductor integrated circuit device is reduced.

Further, when the island region is formed on the main surface of the element forming region of the semiconductor substrate by the above-mentioned isolation technique (2), the plane size of the well region is defined by the field insulating film. A contact area cannot be provided. For this reason, a fixed potential cannot be supplied to the channel formation region of the MISFET.
It is not possible to stabilize the threshold voltage of.

An object of the present invention is to form an island region on the main surface of an element forming region of a semiconductor substrate, which is insulated from other regions.
It is an object of the present invention to provide a technique capable of reducing the planar size of the island region in a semiconductor integrated circuit device in which a MISFET is mounted on the main surface of the element forming region of the island region.

Another object of the present invention is to form an island region on the main surface of an element forming region of a semiconductor substrate, which is insulated from other regions, and mount a MISFET on the main surface of the element forming region of this island region. In a semiconductor integrated circuit device according to the present invention, there is provided a technique capable of reducing the planar size of the island region and stabilizing the threshold voltage of the MISFET.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A semiconductor integrated circuit device in which an island region is formed on a main surface of an element formation region of a semiconductor substrate and is insulated from other regions, and a MISFET is mounted on the main surface of the element formation region of the island region. A source region and a drain region of the MISFET are arranged in a part of the main surface of the element formation region of the island region, and a channel of the MISFET is formed in another region of the main surface of the element formation region of the island region. A power supply contact region electrically connected to the formation region is arranged.

According to the above-described means, the occupied area of the power supply contact region electrically connected to the channel formation region can be offset by the occupied area of the MISFET, so that the occupied area of the power supply contact region is reduced. Correspondingly, the planar size of the island region can be reduced.

Further, since the power supply contact region electrically connected to the channel formation region of the MISFET is provided in the other region of the main surface of the element formation region in the island region, the MISF is provided.
A fixed potential can be supplied to the channel formation region of the ET via the power supply contact region, and the threshold voltage of the MISFET can be stabilized.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The structure of the present invention will be described below together with the embodiments. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and a repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is an equivalent circuit diagram of an inverter circuit mounted in a logic circuit portion of a semiconductor integrated circuit device according to Embodiment 1 of the present invention, and FIG. 2 is the semiconductor integrated circuit. FIG. 3 is a plan view of a main part of a logic circuit unit of the device.
2 is a sectional view taken along the line AA shown in FIG. 2, and FIG. 4 is a sectional view taken along the line BB shown in FIG.
Note that, in FIGS. 2, 3, and 4, illustration is omitted on wirings described later in order to make the drawings easy to see.

As shown in FIG. 1, an inverter circuit which is the tower to the logic circuit portion of the semiconductor integrated circuit device, CMIS consisting of p-channel MISFETQp and n-channel MISFETQn (C omplementary M etal I nsulator S em
icoductor) configuration.

One semiconductor region (source region) of the p-channel MISFET Qp has an operating potential (for example, +5 [V]).
Is connected to an operating potential terminal Vcc to which a reference potential (for example, 0 [V]) is applied to one semiconductor region (source region) of the n-channel MISFET Qn.
It is connected to the. p-channel MISFET Qp and n
The respective gate electrodes of the channel MISFETQn are connected to the signal input terminal Din, and the other semiconductor regions (drain regions) of the p-channel MISFETQp and the n-channel MISFETQn are connected to the signal output terminal Din.

The channel forming region of the p-channel MISFET Qp is fixed at, for example, +5 [V] potential for the purpose of stabilizing the threshold voltage thereof. The channel forming region of the n-channel MISFET Qn is fixed at a potential of 0 [V], for example, for the purpose of stabilizing the threshold voltage.

The p-channel MISFET Qp is shown in FIG.
As shown in FIG. 3, the n-channel MISFET Qn is mounted on the main surface of the element forming region of the island region 3A formed on the main surface of the element forming region of the semiconductor substrate 1, and the n-channel MISFET Qn is the element forming region of the semiconductor substrate 1. Is mounted on the main surface of the element forming region of the island region 3B formed on the main surface of the. The semiconductor substrate 1 is
For example, it has a so-called SOI structure in which a semiconductor layer 1C is formed on a supporting substrate 1A with a substrate insulating film 1B interposed. The support substrate 1A is formed of, for example, a p-type semiconductor substrate made of single crystal silicon, the substrate insulating film 1B is formed of, for example, a silicon oxide film, and the semiconductor layer 1C is formed of single crystal silicon.

The channel forming region of the p-channel MISFET Qp is composed of the n-type well region 3A ₁ formed in the island region 3A. This p-channel MISFET
Qp is mainly composed of an n-type well region 3A ₁ which is a channel forming region, a gate insulating film 4, a gate electrode 5, and a pair of p-type semiconductor regions 9 which are source and drain regions.

The channel forming region of the n-channel MISFET Qn is composed of the p-type well region 3B ₁ formed in the island region 3B. This n-channel MISFET
Qn is mainly composed of a p-type well region 3B ₁ that is a channel forming region, a gate insulating film 4, a gate electrode 5, and a pair of n-type semiconductor regions 10 that are source and drain regions.

A wiring 13A is electrically connected to the p-type semiconductor region 9 which is the source region of the p-channel MISFET Qp through a connection hole 12 formed in the interlayer insulating film 11. This wiring 13A has an operating potential (for example, +5).
[V]) is applied. The wiring 13B is electrically connected to the p-type semiconductor region 9 which is the drain region of the p-channel MISFET Qp through the connection hole 12 formed in the interlayer insulating film 11.

A wiring 13C is electrically connected to the n-type semiconductor region 10 which is the source region of the n-channel MISFET Qn through a connection hole 12 formed in the interlayer insulating film 11. A reference potential (for example, 0
[V]) is applied. The wiring 13B is electrically connected to the n-type semiconductor region 10, which is the drain region of the n-channel MISFET Qn, through the connection hole 12 formed in the interlayer insulating film 11. The wiring 13B is connected to the output signal terminal (Dout) of the inverter circuit.

The gate electrodes 5 of the p-channel MISFET Qp and the n-channel MISFET Qn are shown in FIG.
Are electrically connected to each other via the wiring 13D. This wiring 13D is an output signal terminal of the inverter circuit.
Connected to (Din).

As shown in FIG. 4, a power supply contact region 10A is electrically connected to the n-type well region 3A ₁ which is the channel forming region of the p-channel MISFET Qp. A wiring 13 is formed in the power supply contact area 10A through a connection hole 12A formed in the interlayer insulating film 11.
A is electrically connected. That is, p channel MI
The channel formation region of the SFET Qp is fixed at the operating potential supplied via the power supply contact region 10A. The power supply contact region 10A is a p-channel MIS.
N-type well region 3 which is a channel forming region of FET Qp
It is composed of an n-type semiconductor region 10 of the same conductivity type as A _1, and p
It is arranged on the source region side of the channel MISFET Qp.

As shown in FIG. 4, a power supply contact region 9A is electrically connected to the p-type well region 3B ₁ which is the channel forming region of the n-channel MISFET Qn. A wiring 13C is electrically connected to the power feeding contact region 9A through a connection hole 12A formed in the interlayer insulating film 11. That is, n-channel MISF
The channel formation region of ETQn is fixed at the operating potential supplied via the power supply contact region 9A. The power supply contact region 9A is an n-channel MISFETQ.
The n-channel M is formed by the p-type semiconductor region 9 having the same conductivity type as the p-type well region 3B ₁ which is the n channel forming region.
It is arranged on the source region side of the ISFET Qn.

The island region 3A has a substrate insulating film 1B and a semiconductor layer 1 formed between the supporting substrate 1A and the semiconductor layer 1C.
Field insulating film 2 formed on the element isolation region of C
A, the periphery of each of the buried insulating films 2C embedded in the separation trench 2B that reaches the substrate insulating film 1B from the field insulating film 2A is defined and is insulated from the island region 3B and other regions. The island region 3B includes the substrate insulating film 1B and the semiconductor layer 1 formed between the supporting substrate 1A and the semiconductor layer 1C.
Field insulating film 2 formed on the element isolation region of C
A, the periphery of each of the buried insulating films 2C embedded in the isolation trenches 2B that reach the substrate insulating film 1B from the field insulating film 2A is defined, and is insulated from the island region 3A and other regions. That is, the semiconductor integrated circuit device of this embodiment uses the semiconductor substrate 1 having the SOI structure, and the substrate insulating film 1B, the field insulating film 2A, and the embedded insulating film 2C are formed on the main surface of the element forming region of the semiconductor substrate 1. Each of them forms an island region whose periphery is defined, and the element formation regions are isolated from each other.

As shown in FIG. 3, a p-channel MISF is formed in a part of the main surface of the element forming region of the island region 3A.
A pair of n that is a source region and a drain region of ETQp
The type semiconductor region 9 is arranged. Further, as shown in FIG. 4, in the other region of the main surface of the element formation region of the island region 3A, the channel formation region of the p-channel MISFET Qp is formed.
A power supply contact region 10A electrically connected to the (n-type well region 3A ₁ ) is arranged. That is, on the main surface of the element formation region of the island region 3A, which is insulated and separated by the substrate insulating film 1B, the field insulating film 2A, and the buried insulating film 2C, a pair of source and drain regions of the p-channel MISFET Qp are formed. The power supply contact region 10A in which the p-type semiconductor region 9 is arranged and is electrically connected to the channel forming region of the p-channel MISFET Qp
Is arranged.

As shown in FIG. 3, an n-channel MISF is formed in a part of the main surface of the element forming region of the island region 3B.
A pair of p that is a source region and a drain region of ETQn
The type semiconductor region 10 is arranged. Also, the island area 3B
As shown in FIG. 4, a channel forming region of the n-channel MISFET Qn is formed in the other region of the main surface of the element forming region.
A power supply contact region 9A electrically connected to the (p-type well region 3B ₁ ) is arranged. That is, the main surface of the element forming region of the island region 3B, which is insulated and separated by the substrate insulating film 1B, the field insulating film 2A, and the buried insulating film 2C, has a pair of source and drain regions of the n-channel MISFET Qn. The power supply contact region 9A in which the n-type semiconductor region 10 is arranged and which is electrically connected to the channel forming region of the n-channel MISFET Qn
Is arranged.

Next, a method of manufacturing a semiconductor integrated circuit device on which the inverter circuit is mounted will be described with reference to FIGS. 5 to 8 (a cross-sectional view of a main part for explaining the manufacturing method).

First, a semiconductor substrate 1 having a semiconductor layer 1C formed on a supporting substrate 1A with a substrate insulating film 1B interposed is prepared.

Next, PMIS on the main surface of the semiconductor layer 1C
The n-type well region 3A ₁ is selectively formed in the formation region, and p is formed in the NMIS formation region on the main surface of the semiconductor layer 1C.
The type well region 3B ₁ is selectively formed.

Next, a field insulating film 2A is formed on the element isolation region of the semiconductor layer 1C by a well-known selective oxidation method. The field insulating film 2A is formed of, for example, a silicon oxide film.

Next, a separation groove 2B reaching the substrate insulation film 1B from the field insulation film 2A is formed, and thereafter, a buried insulation film 2C made of, for example, a silicon oxide film is formed in the separation groove 2B.
To form In this step, the substrate insulating film 1B and the field insulating film 2 are formed on the main surface of the element forming region of the semiconductor substrate 1.
A, island region 3 whose perimeter is defined by each of the buried insulating film 2C
A and island regions 3B are respectively formed. This island area 3A,
Each of 3B is insulated and isolated from each other and the other regions.

Next, the gate insulating film 4 is formed on the main surfaces of the element forming regions of the island region 3A and the island region 3B.
The gate insulating film 4 is formed of, for example, a thermal silicon oxide film.

Next, the gate insulating film 4 on the island region 3A.
The gate electrode 5 is formed on the gate insulating film 4, and the gate electrode 5 is formed on the gate insulating film 4 on the island region 3B. The gate electrode 5 includes the semiconductor substrate 1 including the island regions 3A and 3B.
For example, a polycrystalline silicon film having impurities introduced therein is formed on the main surface of, and the polycrystalline silicon film is patterned.

Next, as shown in FIGS. 5 and 6, a part of the main surface of the element formation region of the island region 3A is opened on the main surface of the semiconductor substrate 1 and the island region 3B is formed. A mask 30 having an opening is formed on the other area except for a part of the main surface of the element forming area. In this step, the mask 20 covers the region other than the main surface of the element formation region of the island region 3A and the part of the main surface of the element formation region of the island region 3B. There is. The mask 30 is formed of a photoresist film formed by photolithography, for example.

Next, using the mask 30, the field insulating film 2A and the gate electrode 5 as a mask for introducing impurities, a part of the main surface of the element forming region of the island region 3A and the element forming region of the island region 3B are formed. P-type impurities are selectively introduced into the other region of the main surface of the island region by an ion implantation method, and as shown in FIG. A pair of p-type semiconductor regions 9 that are the source region and the drain region of the MISFET Qp are selectively formed, and as shown in FIG. 6, an n channel is formed in the other region of the main surface of the element forming region of the island region 3B. MISFE
A power supply contact region 9A (p-type semiconductor region 9) electrically connected to the channel formation region (p-type well region 3B ₁ ) of TQn and having the same conductivity type as that of the channel formation region is selectively formed. To do.

Next, the mask 30 is removed.

Next, as shown in FIGS. 7 and 8, a part of the main surface of the element forming region of the island region 3B is opened on the main surface of the semiconductor substrate 1 and the island region 3A is formed. A mask 31 is formed which has an opening on the other area except for a part of the main surface of the element forming area. In this step, the mask 21 covers the area other than the main surface of the element formation region of the island region 3B and the part of the main surface of the element formation region of the island region 3A. There is. The mask 31 is formed of a photoresist film formed by photolithography, for example.

Next, the mask 31, the field insulating film 2A and the gate electrode 5 are used as a mask for introducing impurities to form a part of the main surface of the element formation region of the island region 3B and the element formation of the island region 3A. An n-type impurity is selectively introduced into the other region of the main surface of the region by, for example, an ion implantation method, and as shown in FIG. 7, n is introduced into a part of the main surface of the element forming region of the island region 3B. A pair of n-type semiconductor regions 10, which are the source region and the drain region of the channel MISFET Qn, are selectively formed, and as shown in FIG. Channel MISF
A power supply contact region 10A (n-type semiconductor region 10) electrically connected to the channel formation region (n-type well region 3A ₁ ) of ETQp and having the same conductivity type as the channel formation region is selectively formed. To do.

In this process, p-channel MISFE is used.
Since the feeding contact region 10A (n-type semiconductor region 10) electrically connected to the channel forming region (n-type well region 3A ₁ ) can be arranged within the occupied area of TQp, the p-channel MISFET Qp is occupied. The area occupied by the power supply contact region 10A electrically connected to the channel forming region can be offset. Further, since the power supply contact region 9A (p-type semiconductor region 9) electrically connected to the channel formation region (p-type well region 3B ₁ ) can be arranged within the occupied area of the n-channel MISFET Qn, n Channel MISFETQ
The occupied area of n can offset the occupied area of the power supply contact region 9A electrically connected to the channel forming region.

Next, the mask 31 is removed. Then, an interlayer insulating film 11 is formed on the main surface of the semiconductor substrate 1, and then a connection hole 12 is formed in the interlayer insulating film 11.

Next, a wiring 13 is formed on the interlayer insulating film 11.
Each of A, the wiring 13B, the wiring 13C, and the wiring 13D is formed. By this step, the semiconductor integrated circuit device mounting the inverter circuit is almost completed.

As described above, according to this embodiment, the following operational effects can be obtained.

An island region 3A is formed on the main surface of the element formation region of the semiconductor substrate 1 by the substrate insulating film 1B, the field insulating film 2A, and the buried insulating film 2C, which are insulated from other regions.
A p-channel MI is formed on the main surface of the element formation region of the island region 3A.
A semiconductor integrated circuit device mounting an SFET Qp,
The source region and the drain region of the p-channel MISFET Qp are arranged in a part of the main surface of the element formation region of the island region 3A, and the source region and the drain region of the p-channel MISFET Qp are arranged in other regions of the main surface of the element formation region of the island region 3A. A power supply contact region 10A electrically connected to the channel formation region of the p-channel MISFET Qp is arranged. With this configuration, the p channel M
Since the occupied area of the power supply contact region 10A electrically connected to the channel formation region can be offset by the occupied area of the ISFET Qp, the plane area of the island region 3A corresponds to the occupied area of the power supply contact region 10A. The size can be reduced. Similarly, the planar size of the island region 3B can be reduced.

Further, since the plane size of each of the island region 3A and the island region 3B can be reduced, the island region 3
A p-channel MISFET Qp mounted on the main surface of A and an n-channel MISFET Q mounted on the main surface of the island region 3B.
It is possible to realize high integration of a semiconductor integrated circuit device on which an inverter circuit having a CMIS structure composed of n and n is mounted.

(Second Embodiment) FIG. 9 shows a second embodiment of the present invention.
11 is a chip layout diagram showing a schematic configuration of a semiconductor integrated circuit device, FIG. 10 is an equivalent circuit diagram of a 2-input NAND gate circuit mounted in a logic circuit portion of the semiconductor integrated circuit device, and FIG. FIG. 12 is a plan view of an essential part of a logic circuit part of a semiconductor integrated circuit device, and FIG.
13 is a sectional view taken along the line C, FIG. 13 is a sectional view taken along the line D-D shown in FIG. 12, and FIG.
15 is a cross-sectional view taken along line EE shown in FIG.
FIG. 13 is a sectional view taken along the line FF shown in FIG. 12.
It should be noted that, in FIGS. 12 to 16, illustrations are omitted on wirings described later in order to make the drawings easy to see.

As shown in FIG. 9, the semiconductor integrated circuit device of this embodiment is mainly composed of a semiconductor chip 20 having a rectangular plane, for example. Semiconductor chip 20
A plurality of external terminals (bonding pads) 21 and a plurality of input / output buffer circuits 22 arranged along each side are arranged in the outermost peripheral portion of the. A plurality of basic cells 23 are arranged in a matrix in the logic circuit portion surrounded by the input / output buffer circuit 22.

As shown in FIG. 10, the basic cell 23 is composed of, for example, a 2-input NAND gate circuit. The 2-input NAND gate circuit is a p-channel MISF
ETQp1, p-channel MISFETQp2, n-channel MISFETQn1, p-channel MISFETQn2
Of the CMIS configuration.

The p-channel MISFETs Qp1 and Q
One of the semiconductor regions (source region) of p2 has an operating potential terminal Vcc to which an operating potential (for example, +5 [V]) is applied.
It is connected to the. The other semiconductor region (drain region) of each of the p-channel MISFETs Qp1 and Qp2 is connected to the signal output terminal Dout, and the n-channel MI
It is connected to one semiconductor region (source region) of the SFET Qn1. The other semiconductor region (drain region) of the n-channel MISFETQn2 is the n-channel MISFETQn.
It is connected to the other semiconductor region (drain region) 1. One semiconductor region of the n-channel MISFET Qn1
The (source region) is connected to a reference potential terminal Vss to which a reference potential (for example, 0 [V]) is applied.

The p-channel MISFETs Qp1 and n
Each gate electrode of the channel MISFETQn2 is connected to the signal input terminal Din2. p channel MISF
The gate electrodes of the ETQp2 and the n-channel MISFETQn1 are connected to the signal input terminal Din1.

The p-channel MISFETs Qp1 and Q
Each channel forming region of p2 is fixed at, for example, +5 [V] potential for the purpose of stabilizing the threshold voltage. In addition, the n-channel MISFET Qn1
The channel forming regions of Qn and Qn2 are fixed at, for example, 0 [V] potential for the purpose of stabilizing the threshold voltage.

The p-channel MISFETs Qp1 and Q
p2 is the semiconductor substrate 1 as shown in FIGS.
The island region 3A formed on the main surface of the element forming region is mounted on the main surface of the element forming region of the island region 3A. The semiconductor substrate 1 has the substrate insulating film 1 formed on the supporting substrate 1A as in the first embodiment.
It has a so-called SOI structure in which the semiconductor layer 1C is formed with B interposed.

The p-channel MISFETs Qp1 and Q
Each channel forming region of p2 is composed of the n-type well region 3A ₁ formed in the island region 3A. The p-channel MISFETs Qp1 and Qp2 mainly include an n-type well region 3A ₁ that is a channel forming region, a gate insulating film 4, a gate electrode 5, a pair of p-type semiconductor regions 6 that are source and drain regions, and a pair of p-types. It is composed of the type semiconductor region 9.

The impurity concentration of the p-type semiconductor region 6 is p
The concentration is set lower than the impurity concentration of the type semiconductor region 9. That is, the p-channel MISFET of this embodiment
Qp1 and Qp2 is a so-called partial region of the channel formation region side of the drain region is set to a low impurity concentration than the impurity concentration of the other regions LDD (L ightly D oped
D rain) structure. This LDD structure reduces the amount of diffusion of the drain region toward the channel formation region,
Since the channel length dimension can be secured, the occurrence of the short channel effect can be suppressed. In addition, the LDD structure can relax the gradient of the impurity concentration distribution of the pn junction formed between the drain region and the channel formation region and weaken the electric field strength generated in this region, so that the generation of hot carriers is generated. The amount can be reduced. Note that p
The type semiconductor region 6 is formed in self-alignment with the gate electrode 5, and the p-type semiconductor region 9 is formed in self-alignment with the sidewall spacers 8 formed on the side wall surfaces of the gate electrode 5 in the gate length direction. It is formed.

An interlayer insulating film 11 is formed in the p-type semiconductor region 9 which is the drain region of the p-channel MISFET Qp1.
The wiring 13B is electrically connected through the connection hole 12 formed in the. A wiring 13B is electrically connected to the p-type semiconductor region 9 which is the drain region of the p-channel MISFET Qp2 through a connection hole 12 formed in the interlayer insulating film 11. The p-channel MISFET Qp
A wiring 13A is electrically connected to the p-type semiconductor region 9 which is the source region of each of 1 and Qp2 through a connection hole 12 formed in the interlayer insulating film 11. This wiring 13A
An operating potential (for example, +5 [V]) is applied to.

The p-channel MISFETs Qp1 and Q
p-type well region 3 which is each channel forming region of p2
As shown in FIG. 12, a power supply contact region 10A is electrically connected to A ₁ . A wiring 13A is electrically connected to the power supply contact region 10A through a connection hole 12A formed in the interlayer insulating film 11.
That is, the channel forming regions of the p-channel MISFETs Qp1 and Qp2 are fixed to the operating potential supplied via the power supply contact region 10A. The power supply contact region 10A is a p-channel MISFET Qp1.
And Qp2 are formed of n-type semiconductor regions 10 having the same conductivity type as the n-type well region 3A ₁ which is a channel forming region of each of p-channel MISFETs Qp1 and Qp2.

The n-channel MISFETs Qn1 and Qn
n2 is the semiconductor substrate 1 as shown in FIGS.
The island region 3B formed on the main surface of the element forming region is mounted on the main surface of the element forming region of the island region 3B.

The n-channel MISFETs Qn1 and Qn
Each channel forming region of n2 is composed of the p-type well region 3B ₁ formed in the island region 3B. The n-channel MISFETs Qn1 and Qn2 mainly consist of a p-type well region 3B ₁ which is a channel forming region, a gate insulating film 4, a gate electrode 5, a pair of n-type semiconductor regions 7 which are source and drain regions, and a pair of n. Type semiconductor region 10
It is composed of

The impurity concentration of the n-type semiconductor region 7 is n
The concentration is set lower than the impurity concentration of the type semiconductor region 10. That is, the n-channel MISFE of the present embodiment
Each of TQn1 and Qn2 has an LDD structure in which a part of the drain region on the channel formation region side has an impurity concentration lower than that of the other regions. The n-type semiconductor region 7 is formed in self alignment with the gate electrode 5, and the n-type semiconductor region 10 is formed with the gate electrode 5.
Are formed in self alignment with the side wall spacers 8 formed on the respective side wall surfaces in the gate length direction.

An interlayer insulating film 11 is formed in the n-type semiconductor region 10 which is the source region of the n-channel MISFET Qn1.
The wiring 13C is electrically connected through the connection hole 12 formed in. A reference potential (for example, 0 [V]) is applied to the wiring 13C. The n-channel MISFET
In the n-type semiconductor region 10 which is the source region of Qn2, the wiring 13 is formed through the connection hole 12 formed in the interlayer insulating film 11.
B is electrically connected.

The n-channel MISFETs Qn1 and Qn
n-type well region 3 which is each channel forming region of n2
As shown in FIG. 15, a power feeding contact region 9A is electrically connected to B ₁ . In the power supply contact region 9A, the connection hole 12 formed in the interlayer insulating film 11 is formed.
The wiring 13C is electrically connected through A. That is, the channel forming regions of the n-channel MISFETs Qn1 and Qn2 are fixed at the reference potential supplied via the power feeding contact region 9A. The power supply contact region 9A includes n-channel MISFETs Qn1 and Qn.
P-type well regions 3B which are the respective channel forming regions
It is composed of a p-type semiconductor region 9 of the same conductivity type as that of _1, and is arranged on the source region side of the n-channel MISFET Qn1.

As shown in FIGS. 11 and 13, the island region 3A is formed in the element isolation region of the substrate insulating film 1B and the semiconductor layer 1C formed between the supporting substrate 1A and the semiconductor layer 1C. Further, the lower part thereof is defined around each of the field insulating films 2A in contact with the substrate insulating film 1B, and is insulated from the island region 3B and other regions. As shown in FIGS. 11 and 14, the island region 3B is a support substrate 1A.
And the semiconductor layer 1C are formed between the substrate insulating film 1B and the semiconductor layer 1C, and the field insulating film 2A formed in the element isolation region of the semiconductor layer 1C and the lower part of which is in contact with the substrate insulating film 1B defines the perimeter. It is insulated from the island region 3A and other regions. That is, the semiconductor integrated circuit device of the present embodiment uses the semiconductor substrate 1 having the SOI structure, and the periphery thereof is defined by the substrate insulating film 1B and the field insulating film 2A on the main surface of the element forming region of the semiconductor substrate 1. Island regions are formed, and the element formation regions are isolated from each other. Note that n
The type well region 3A ₁ and the p-type well region 3B ₁ are divided into island regions.

As shown in FIG. 13, a p-channel MIS is formed in a part of the main surface of the element forming region of the island region 3A.
Source regions (9) and drain regions (9) of the FETs Qp1 and Qp2 are arranged. In addition, as shown in FIG. 12, in the other region of the main surface of the element formation region of the island region 3A, electrically connected to the respective channel formation regions (n-type well region 3A ₁ ) of the p-channel MISFETs Qp1 and Qp2. The connected power supply contact region 10A is arranged. That is, the substrate insulating film 1B and the field insulating film 2A
In the main surface of the element formation region of the island region 3A, which is insulated and separated by the above, the source region (9) and the drain region (9) of the p-channel MISFETs Qp1 and Qp2 are arranged, and the p-channel MISFET Qp1 and Qp2
Power supply contact regions 10A electrically connected to the respective channel formation regions are arranged.

As shown in FIG. 14, an n-channel MIS is formed in a part of the main surface of the element forming region of the island region 3B.
Source regions (10) and drain regions (10) of the FETs Qn1 and Qn2 are arranged. Also, island area 3
As shown in FIG. 15, in the other region of the main surface of the B element formation region, as shown in FIG. 15, a power supply electrically connected to each channel formation region (p-type well region 3B ₁ ) of the n-channel MISFETs Qn1 and Qn2. For contact area 9A is arranged. That is, the substrate insulating film 1B and the field insulating film 2
The source region (10) and the drain region (10) of the n-channel MISFETs Qn1 and Qn2 are arranged on the main surface of the element formation region of the island region 3B which is insulated and separated by each of A, and the n-channel MISFET Qn1 is formed. And a power supply contact region 9A electrically connected to the channel formation regions of Qn2 and Qn2, respectively.

As described above, according to this embodiment, the following operational effects can be obtained.

An island region 3A is formed on the main surface of the element forming region of the semiconductor substrate 1 so as to be insulated from the other regions by the substrate insulating film 1B and the field insulating film 2A. A semiconductor integrated circuit device in which p-channel MISFETs Qp1 and Qp2 are mounted on the main surface, and the p-channel is formed in a part of the main surface of the element formation region of the island region 3A.
A source region (p-type semiconductor region 9) and a drain region (p-type semiconductor region 9) of each of the channel MISFETs Qp1 and Qp2 are arranged, and the p-channel is formed in the other region of the main surface of the element forming region of the island region 3A. MISFET Qp1
And power supply contact region 1 electrically connected to the respective channel forming regions (n-type well region 3A ₁ ) of Qp2.
0A (n-type semiconductor region 10) is arranged. With this configuration, the occupied areas of the p-channel MISFETs Qp1 and Qp2 can offset the occupied areas of the power supply contact area 10A electrically connected to the channel formation areas, so that the power supply contact area 10A is occupied. The planar size of the island region 3A can be reduced by an amount corresponding to the area, and the channel formation regions of the p-channel MISFETs Qp1 and Qp2 are formed in the other regions of the main surface of the element formation region of the island region 3A. Since the power supply contact region 10A electrically connected is provided, a fixed potential can be supplied to the respective channel formation regions of the p-channel MISFETs Qp1 and Qp2 via the power supply contact region 10A, and the p-channel MISFETs Qp1 and Qp2 are provided. It is possible to stabilize the threshold voltage of each Similarly, the plane size of the island region 3B can be reduced, and the threshold voltages of the n-channel MISFETs Qn1 and Qn2 can be stabilized.

Further, since the plane size of each of the island region 3A and the island region 3B can be reduced, the island region 3
P channel MISFETs Qp1 and Qp mounted on A
2 and an n-channel MISFET mounted on the island region 3B
Two-input NA of CMIS configuration consisting of Qn1 and Qn2
High integration of a semiconductor integrated circuit device having an ND gate circuit can be realized.

Further, the threshold voltages of the p-channel MISFETs Qp1 and Qp2 mounted on the island region 3A can be stabilized, and the n-channel MISFETs Qn1 and Qn2 mounted on the island region 3B can be stabilized. Since the threshold voltage can be stabilized, the circuit performance of the semiconductor integrated circuit device mounting the 2-input NAND gate circuit composed of these semiconductor elements can be maintained at a high level.

Each of the power feeding contact region 9A and the power feeding contact region 10A is formed by the same manufacturing process as that of the power feeding contact region 9A and the power feeding contact region 10A described in the first embodiment. .

(Third Embodiment) FIG. 16 is a plan view of a main portion of a logic circuit portion of a semiconductor integrated circuit device according to a third embodiment of the present invention. FIG. 17 shows a position of line GG shown in FIG. FIG. 18 is a cross-sectional view taken along the line, FIG. 18 is a cross-sectional view taken along the line H-H shown in FIG. 16, and FIG.
FIG. 19 is a cross-sectional view taken along the line, FIG. 19 is a cross-sectional view taken along the line JJ shown in FIG. 16, and FIG.
It is sectional drawing cut | disconnected in the position of the KK line shown in FIG. It should be noted that in FIGS. 16 to 20, wirings to be described later are omitted in order to make the drawings easy to see.

As shown in FIG. 16, a basic cell 23 is arranged in the logic circuit portion of the semiconductor integrated circuit device of this embodiment. Although not shown, the basic cell 23 is similar to the second embodiment described above in that the p-channel MISFET Qp
1, p-channel MISFET Qp2, n-channel MIS
It is composed of a two-input NAND gate circuit having a CMIS structure composed of an FET Qn1 and a p-channel MISFET Qn2.

The p-channel MISFETs Qp1 and Q
p2 is the semiconductor substrate 1 as shown in FIGS.
It is mounted on the main surface of the island region 3A formed on the main surface of the element forming region. The semiconductor substrate 1 has a so-called SOI structure in which the semiconductor layer 1C is formed on the supporting substrate 1A with the substrate insulating film 1B interposed therebetween, as in the second embodiment.

The p-channel MISFETs Qp1 and Q
Each channel forming region of p2 is composed of the n-type well region 3A ₁ formed in the island region 3A. The p-channel MISFETs Qp1 and Qp2 are mainly composed of an n-type well region 3A ₁ which is a channel forming region, a gate insulating film 4, a gate electrode 5, and a pair of p-type semiconductor regions 9 which are source and drain regions. There is.

The n-channel MISFETs Qn1 and Qn
n2 is the semiconductor substrate 1 as shown in FIGS.
Is mounted on the main surface of the island region 3B formed in the element formation region.

The n-channel MISFETs Qn1 and Q
Each channel forming region of n2 is composed of the p-type well region 3B ₁ formed in the island region 3B. The n-channel MISFETs Qn1 and Qn2 are mainly composed of a p-type well region 3B ₁ which is a channel forming region, a gate insulating film 4, a gate electrode 5, and a pair of n-type semiconductor regions 10 which are source and drain regions. There is.

As shown in FIGS. 16 and 18, the island region 3A is formed in the element isolation region of the substrate insulating film 1B and the semiconductor layer 1C formed between the supporting substrate 1A and the semiconductor layer 1C, Further, the lower part thereof is defined around each of the field insulating films 2A in contact with the substrate insulating film 1B, and is insulated from the island region 3B and other regions. As shown in FIGS. 11 and 14, the island region 3B is a support substrate 1A.
And the semiconductor layer 1C are formed between the substrate insulating film 1B and the semiconductor layer 1C, and the field insulating film 2A formed in the element isolation region of the semiconductor layer 1C and the lower part of which is in contact with the substrate insulating film 1B defines the perimeter. It is insulated from the island region 3A and other regions. That is, the semiconductor integrated circuit device of the present embodiment uses the semiconductor substrate 1 having the SOI structure, and the periphery thereof is defined by the substrate insulating film 1B and the field insulating film 2A on the main surface of the element forming region of the semiconductor substrate 1. Island regions are formed, and the element formation regions are isolated from each other.

A pair of p-type semiconductor regions 9 which are a source region and a drain region of the p-channel MISFET Qp1.
Is in contact with the substrate insulating film 1B formed below the island region 3A, as shown in FIG. The p channel M
The pair of p-type semiconductor regions 9 that are the source region and the drain region of the ISFET Qp2 are in contact with the substrate insulating film 1B formed below the island region 3A. That is, each of the channel formation region of the p-channel MISFET Qp1 n-type well region 3A _1, a channel formation region of the p-channel MISFET Qp2 n-type well region 3A ₁ s is
The periphery of the p-type semiconductor region 9 is defined and insulated from each other.

A pair of n-type semiconductor regions 1 which are a source region and a drain region of the n-channel MISFET Qn1.
As shown in FIG. 19, 0 is in contact with the substrate insulating film 1B formed below the island region 3B. The pair of n-type semiconductor regions 10 which are the source region and the drain region of the n-channel MISFET Qn2 are in contact with the substrate insulating film 1B formed below the island region 3B. That is, n
The p-type well region 3B ₁ which is the channel forming region of the channel MISFET Qn1 and the n-channel MISFET Qn2
Each of the p-type well regions 3B ₁ which is the channel forming region is defined by the n-type semiconductor region 10 and is insulated from each other.

In the p-type semiconductor region 9 which is the drain region of the p-channel MISFET Qp1, the structure shown in FIGS.
As shown in FIG. 8, the connection hole 1 formed in the interlayer insulating film 11
The wiring 13B is electrically connected through 2. P which is the drain region of the p-channel MISFET Qp2
A wiring 13B is electrically connected to the type semiconductor region 9 through a connection hole 12 formed in the interlayer insulating film 11.
The interlayer insulating film 1 is formed in the p-type semiconductor region 9 which is the source region of each of the p-channel MISFETs Qp1 and Qp2.
The wiring 13A is electrically connected through the connection hole 12 formed in 1. An operating potential (for example, +5 [V]) is applied to the wiring 13A.

The p-channel MISFETs Qp1 and Q
p-type well region 3 which is each channel forming region of p2
As shown in FIG. 17, the power supply contact region 10A is electrically connected to A ₁ . A wiring 13A is electrically connected to the power supply contact region 10A through a connection hole 12A formed in the interlayer insulating film 11.
That is, the channel forming regions of the p-channel MISFETs Qp1 and Qp2 are fixed to the operating potential supplied via the power supply contact region 10A. The power supply contact region 10A is a p-channel MISFET Qp1.
And Qp2 are formed of n-type semiconductor regions 10 having the same conductivity type as the n-type well region 3A ₁ which is a channel forming region of each of p-channel MISFETs Qp1 and Qp2.

The n-type semiconductor region 10 which is the source region of the n-channel MISFET Qn1 has a structure shown in FIGS.
As shown in FIG. 9, the connection hole 1 formed in the interlayer insulating film 11
The wiring 13C is electrically connected through 2. A reference potential (for example, 0 [V]) is applied to the wiring 13C. A wiring 13B is electrically connected to the n-type semiconductor region 10, which is the source region of the n-channel MISFET Qn2, through a connection hole 12 formed in the interlayer insulating film 11.

The n-type well region 3B ₁ which is the channel forming region of the n-channel MISFET Qn1 has a structure shown in FIG.
As shown in, the power supply contact region 9A is electrically connected. In the power supply contact region 9A, the wiring 1 is formed through the connection hole 12A formed in the interlayer insulating film 11.
3C is electrically connected. That is, n channel M
The channel formation region of the ISFET Qn1 is fixed at the reference potential supplied via the power supply contact region 9A. The power supply contact region 9A is an n-channel MISF.
P-type well region 3 which is a channel forming region of ETQn1
It is composed of a p-type semiconductor region 9 of the same conductivity type as B _1, and is arranged on the source region side of the n-channel MISFET Qn1.

As shown in FIG. 18, a p-channel MIS is formed in a part of the main surface of the element formation region of the island region 3A.
Source regions (9) and drain regions (9) of the FETs Qp1 and Qp2 are arranged. In addition, as shown in FIG. 17, in the other region of the main surface of the element formation region of the island region 3A, electrically connected to the respective channel formation regions (n-type well region 3A ₁ ) of the p-channel MISFETs Qp1 and Qp2. The connected power supply contact region 10A is arranged. That is, the substrate insulating film 1B and the field insulating film 2A
In the main surface of the element formation region of the island region 3A, which is insulated and separated by the above, the source region (9) and the drain region (9) of the p-channel MISFETs Qp1 and Qp2 are arranged, and the p-channel MISFET Qp1 and Qp2
Power supply contact regions 10A electrically connected to the respective channel formation regions are arranged.

In a part of the main surface of the element forming region of the island region 3B, an n-channel MIS is formed as shown in FIG.
Source regions (10) and drain regions (10) of the FETs Qn1 and Qn2 are arranged. Also, island area 3
As shown in FIG. 20, a power supply contact region 9A electrically connected to the channel formation region (p-type well region 3B ₁ ) of the n-channel MISFET Qn1 is provided in the other region of the main surface of the B element formation region. Are arranged. That is,
The source regions of the n-channel MISFETs Qn1 and Qn2 are formed on the main surface of the element forming region of the island region 3B that is insulated and separated by the substrate insulating film 1B and the field insulating film 2A.
(10) and the drain region (10) are arranged, and the power supply contact region 9A electrically connected to the channel forming region of the n-channel MISFET Qn1 is arranged.

As shown in FIGS. 16 and 21, the island region 3B is connected to the island region 3C. A p-type well region 3B ₁ which is a channel forming region of the n-channel MISFET Qn2 is drawn out to the island region 3C. In addition, an n-channel MISF is formed on the main surface of the island region 3C.
A power feeding contact region 9B electrically connected to the channel forming region of ETQn2 is arranged. A wiring 13C is electrically connected to the power supply contact region 9B through a connection hole 12A formed in the interlayer insulating film 11. That is, the channel formation region of the n-channel MISFET Qn2 is fixed in potential to the reference potential supplied via the power supply contact region 9B arranged on the main surface of the island region 3C. The power supply contact region 9B has an n-channel M
The p-type well region 3B ₁ which is the channel formation region of the ISFET Qn2 is composed of the p-type semiconductor region 9 of the same conductivity type, and is arranged on the source region side of the n-channel MISFET Qn2.

As described above, according to this embodiment, the following operational effects can be obtained.

(1) On the main surface of the element formation region of the semiconductor substrate 1, an island region 3A is formed, which is insulated from the other regions by the substrate insulating film 1B and the field insulating film 2A, and the element of this island region 3A is formed. A p-channel MISFETQ is formed on the main surface of the formation region.
A semiconductor integrated circuit device having p1 and Qp2 mounted thereon, wherein each source region (p-type semiconductor region 9) of each of the p-channel MISFETs Qp1 and Qp2 is provided in a part of the main surface of the element formation region of the island region 3A. And a drain region (p-type semiconductor region 9) are arranged, and the p-channel MISF is formed in the other region of the main surface of the element formation region of the island region 3A.
A power supply contact region 10A (n-type semiconductor region 10) electrically connected to each channel formation region (n-type well region 3A ₁ ) of ETQp1 and Qp2 is arranged. With this configuration, the p-channel MISFETs Qp1 and Qp2 are
Since the occupied areas of the power supply contact regions 10A electrically connected to the channel formation regions can be offset by the respective occupied areas, the power supply contact regions 1
The plane size of the island region 3A can be reduced by the amount corresponding to the occupied area of 0 A, and the p-channel MISFET is formed in the other region of the main surface of the element formation region of the island region 3A.
Since the power supply contact region 10A electrically connected to the respective channel formation regions of Qp1 and Qp2 is provided,
A fixed potential can be supplied to the channel forming regions of the p-channel MISFETs Qp1 and Qp2 through the power supply contact region 10A, and the p-channel MISFETs can be supplied.
It is possible to stabilize the threshold voltage of each of Qp1 and Qp2.

In particular, as in this embodiment, the p channel M
N-type well region 3A ₁ is a channel formation region of ISFETQp1, if each of the n-type well region 3A ₁ is a channel formation region of the p-channel MISFETQp2 are separated, the two-input NAND gate circuit, the p-channel MISFETQp1 and Qp2 By arranging the power supply contact region 10A on the side of each source region (9), a fixed potential can be supplied to each channel formation region of the p-channel MISFETs Qp1 and Qp2.

(2) The substrate insulating film 1 is formed on the main surface of the semiconductor substrate 1.
B, the field insulating film 2A forms an island region 3B that is insulated from other regions, and the n-channel MISFETs Qn1 and Qn2 are formed on the main surface of the element forming region of the island region 3B.
A semiconductor integrated circuit device mounted on the island region of the island region 3
The source regions of the n-channel MISFETs Qn1 and Qn2 are provided in a part of the main surface of the B element formation region.
(10) and the drain region (10) are arranged and electrically connected to the channel formation region (p-type well region 3B ₁ ) of the n-channel MISFET Qn1 in the other region of the main surface of the element formation region of the island region 3B. A power supply contact region (p-type semiconductor region 9) 9A connected to is disposed. With this configuration, the occupied area of the n-channel MISFET Qn1 can offset the occupied area of the power-feeding contact region 9A electrically connected to the channel forming region, and thus corresponds to the occupied area of the power-feeding contact region 9A. Therefore, the plane size of the island region 3B can be reduced, and the n-channel MSI is formed in the other region of the main surface of the island region 3B.
Since the power supply contact region 9A electrically connected to the channel forming region of the FET Qn is provided, the n-channel MI is formed.
A fixed potential can be supplied to the channel formation region of the SFET Qn1 via the power feeding contact region 9A, and the threshold voltage of the n-channel MISFET Qn1 can be stabilized.

In particular, as in this embodiment, the n-channel M
P-type well region 3B ₁ is a channel formation region of ISFETQn1, if each of the p-type well region 3B ₁ is a channel formation region of the n-channel MISFETQn2 are separated, the two-input NAND gate circuit, a source of n-channel MISFETQn1 If the power supply contact region 9A is arranged on the region (10) side, the n-channel MIS
A fixed potential can be supplied to the channel formation region of the FET Qn1.

(3) An island region 3B is formed on the main surface of the device forming region of the semiconductor substrate 1 so as to be insulated from the other regions by the substrate insulating film 1B and the field insulating film 2A. N channel MISFETQ is formed on the main surface of the formation region.
A semiconductor integrated circuit device having n1 and Qn2 mounted thereon, wherein the n-channel MISFET Q is provided in the island region 3B.
Another island region 3C from which the n2 channel forming region is extracted
And a power supply contact region 9B electrically connected to the channel forming region of the n-channel MISFET Qn2 is disposed on the other main surface of the island region 3C. With this configuration, a fixed potential can be supplied to the channel forming region of the n-channel MISFET Qn1 via the power feeding contact region 9A, and thus the n-channel MISFETQn.
It is possible to stabilize the threshold voltage of n2.

Particularly, as in this embodiment, the n-channel M
P-type well region 3B ₁ is a channel formation region of ISFETQn1, if each of the p-type well region 3B ₁ is a channel formation region of the n-channel MISFETQn2 are separated, the two-input NAND gate circuit, in the island region 3B, The channel formation region of the n-channel MISFET Qn2 is connected to the extracted other island region 3C, and the n-channel MISFET Qn2 is connected to the main surface of the other island region 3C.
If the power supply contact region 9B electrically connected to the channel forming region of the n-channel MISFETQ is arranged.
A fixed potential can be supplied to the n2 channel formation region.

The power supply contact area 9A, the power supply contact area 9B, and the power supply contact area 10A are the same as the power supply contact area 9A and the power supply contact area 10A shown in the first embodiment. It is formed by the manufacturing process.

The inventions made by the present inventors are as follows.
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above embodiment, and various changes can be made without departing from the scope of the invention.

For example, according to the present invention, an island region is formed on the main surface of the element formation region of the semiconductor substrate so as to be insulated from other regions, and three or more island regions are formed on the main surface of the element formation region of this island region. It can be applied to a semiconductor integrated circuit device on which a MISFET is mounted.

Further, the present invention comprises a CMIS configuration 3
The present invention can be applied to a semiconductor integrated circuit device in which NAND gate circuits having inputs or more are mounted.

In addition, the present invention provides an O having a CMIS configuration.
It can be applied to a semiconductor integrated circuit device on which an R gate circuit is mounted.

[0101]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

A semiconductor integrated circuit device in which an island region, which is insulated from other regions, is formed on the main surface of an element formation region of a semiconductor substrate, and a MISFET is mounted on the main surface of the element formation region of this island region. It is possible to reduce the plane size of the island region.

In the semiconductor integrated circuit device,
In addition to reducing the planar size of the island region,
It is possible to stabilize the threshold voltage of the ISFET.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of an inverter circuit mounted in a logic circuit section of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a plan view of a main part of a logic circuit section of the semiconductor integrated circuit device.

FIG. 3 is a sectional view taken along a line AA shown in FIG. 2;

FIG. 4 is a cross-sectional view taken along the line BB shown in FIG.

FIG. 5 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 7 is a cross-sectional view illustrating the method for manufacturing the semiconductor integrated circuit device.

FIG. 8 is a cross-sectional view illustrating the method for manufacturing the semiconductor integrated circuit device.

FIG. 9 is a chip layout diagram of a semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 10 is an equivalent circuit diagram of a 2-input NAND gate circuit mounted in a logic circuit section of the semiconductor integrated circuit device.

FIG. 11 is a main-portion plan view of a logic circuit portion of the semiconductor integrated circuit device;

12 is a cross-sectional view taken along the line CC of FIG.

13 is a cross-sectional view taken along the line DD shown in FIG.

14 is a sectional view taken along the line EE shown in FIG.

15 is a cross-sectional view taken along the line FF shown in FIG.

FIG. 16 is a main-portion plan view of a logic circuit portion of a semiconductor integrated circuit device which is Embodiment 3 of the present invention;

17 is a cross-sectional view taken along the line GG shown in FIG.

18 is a cross-sectional view taken along the line HH shown in FIG.

19 is a cross-sectional view taken along the line I-I shown in FIG.

20 is a cross-sectional view taken along the line JJ shown in FIG.

21 is a cross-sectional view taken along the line KK shown in FIG.

[Explanation of symbols]

1 ... Semiconductor substrate, 1A ... Support substrate, 1B ... Substrate insulating film,
1C ... Semiconductor layer, 2A ... Field insulating film, 2B ... Separation trench, 2C ... Buried insulating film, 3A, 3B, 3C ... Island region, 3
A ₁ ... N-type well region, 3B ₁ ... P-type well region, 4 ...
Gate insulating film, 5 ... Gate electrode, 6 ... P-type semiconductor region,
7 ... N-type semiconductor region, 8 ... Sidewall spacer, 9
... p-type semiconductor region, 10 ... n-type semiconductor region, 9A, 9
B, 10A ... Contact region for power feeding, 11 ... Interlayer insulating film, 12 ... Connection hole, 13A, 13B, 13C, 13D ...
Wiring, 20 ... Semiconductor chip, 21 ... External terminal (bonding pad), 22 ... Input buffer circuit, 23 ... Basic cell, 30, 31 ... Mask.

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/786

Claims (10)

[Claims] 1. A semiconductor integrated circuit device in which a main surface of an element formation region of a semiconductor substrate is formed with an island region which is insulated from other regions, and a MISFET is mounted on the main surface of the element formation region of the island region. The source region and the drain region of the MISFET are arranged in a part of the main surface of the element formation region of the island region, and the MISFET is formed in another region of the main surface of the element formation region of the island region. A semiconductor integrated circuit device, in which a power supply contact region electrically connected to the channel forming region is disposed. 2. A semiconductor integrated structure in which an island region is formed on a main surface of an element forming region of a semiconductor substrate and is insulated from other regions, and at least two MISFETs are mounted on the main surface of the element forming region of the island region. A circuit device, wherein the two MISFE are formed in a part of the main surface of the element formation region of the island region.
Each of the source region and the drain region of T is arranged, and a power supply contact electrically connected to each of the channel forming regions of the two MISFETs in the other region of the main surface of the element forming region of the island region. A semiconductor integrated circuit device having regions arranged therein. 3. The power supply contact region is provided with the MI.
3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is arranged on the source region side of the SFET. 4. A semiconductor integrated device in which an island region, which is insulated from other regions, is formed on a main surface of an element forming region of a semiconductor substrate, and at least two MISFETs are mounted on the main surface of the element forming region of the island region. A circuit device, wherein the two MISFE are formed in a part of the main surface of the element formation region of the island region.
Each source region and drain region of T is arranged, and a power supply contact electrically connected to one of the two MISFETs in the other region of the main surface of the element formation region of the island region. A semiconductor integrated circuit device having regions arranged therein. 5. The semiconductor integrated circuit device according to claim 4, wherein the power supply contact region is arranged on the source region side of the one MISFET. 6. A semiconductor integrated device in which an island region, which is insulated from other regions, is formed on the main surface of an element formation region of a semiconductor substrate, and at least two MISFETs are mounted on the main surface of the element formation region of this island region. In the circuit device, another island region from which the channel forming region of one of the two MISFETs is extracted is connected to the island region, and the main surface of the other island region is connected to the other island region. A semiconductor integrated circuit device having a power supply contact region electrically connected to a channel formation region of a MISFET. 7. The island region is defined by an insulating film formed on a lower portion thereof and an insulating film formed on a side portion of the island region, and is insulated from other regions. The semiconductor integrated circuit device according to any one of claims 1 to 6. 8. The method according to claim 1, wherein the source region and the drain region of the MISFET are in contact with an insulating film formed under the island region. The semiconductor integrated circuit device described. 9. The semiconductor substrate according to claim 1, wherein the semiconductor substrate has an SOI structure in which a semiconductor layer is formed on a supporting substrate with an insulating film interposed therebetween. A semiconductor integrated circuit device according to item. 10. A first island region and a second island region, which are insulated from each other, are formed on a main surface of an element formation region of a semiconductor substrate, and a first surface is formed on a main surface of the element formation region of the first island region. A method of manufacturing a semiconductor integrated circuit device, comprising: a conductive type first MISFET; and a second conductive type second MISFET mounted on a main surface of an element forming region of the second island region. The first MI is formed on a part of the main surface of the formation area.
The source region and the drain region of the SFET are selectively formed, and the channel formation region of the second MISFET and the channel formation region of the second MISFET are electrically formed in a region other than a part of the main surface of the element formation region of the second island region. Selectively forming a power supply contact region which is connected to the channel formation region and has the same conductivity type as that of the channel formation region, and the second island region is formed in a part of the main surface of the element formation region, A source region and a drain region of the 2MISFET are selectively formed, and are electrically connected to the channel formation region of the first MISFET in a region of the other main surface of the element formation region of the first island region, and A method of manufacturing a semiconductor integrated circuit device, comprising the step of selectively forming a power supply contact region formed of the same conductivity type as that of a channel formation region.