WO1997008752A1

WO1997008752A1 - Mis semiconductor device

Info

Publication number: WO1997008752A1
Application number: PCT/JP1995/001691
Authority: WO
Inventors: Masafumi Miyamoto; Kazuo Yano; Yasuhiko Sasaki
Original assignee: Hitachi, Ltd.
Priority date: 1995-08-25
Filing date: 1995-08-25
Publication date: 1997-03-06

Abstract

The area of a logical gate using a path transistor is greatly reduced, the operating speed is increased, and the power consumption is lowered. A control signal is commonly inputted into the gates of two MIS transistors of a two-input selector circuit. One of the MIS transistors is a PMOS transistor and the other is an NMOS, which are both formed on an SOI substrate. Therefore, the area of the logic gates can be reduced remarkably, because the inverter for generating an inverting signal for the two-input selector circuit is not needed. In addition, the power consumption of the gates can be reduced by the amount of electric power consumed by the inverter and the operating speed of the gates can be increased by taking advantage of the large driving current and low junction capacitance of the MIS transistors having SOI structures.

Description

Specification

MIS type semiconductor device

The present invention relates to a MIS type semiconductor device, and more particularly to a pass transistor logic circuit or a selector circuit using a transistor formed in a thin film semiconductor layer on an insulating film. Background art

Due to demands for higher speed and lower power consumption of logic circuits, research on logic circuits or selector circuits using so-called pass transistors has been conducted.

Conventionally, the circuit power shown in Fig. 5 is known as a commonly used pass transistor logic circuit (K. Yano, et.al., IEEE Journal of Solid-State Cir Cuits, Vol. 25, No. _{2, p P 388-395 (1990)} ). The logic circuit shown in Fig. 5 is formed on a so-called bulk semiconductor substrate, and the Ql and Q7 source Z drain regions of an n-type MOS transistor (NMOS) are connected to each other to form an output amplifier circuit. Connected to the input of the CMOS inverter (complementary MOS circuit). The gate of Q1 is connected to the control signal input terminal C, and the gate of Q7 is connected to the inverted signal from the terminal C through the inverter. After one of the signals input to the input terminals X and Y of the source Z drain region of Q1 and Q7 is selected by the control signal input to the terminal C and inverted and output amplified by the inverter, Output to OUT terminal. When the same input as the X terminal is input to the C terminal in this circuit, it functions as a two-input NAND. It is known that a logic circuit combined with the basic gate of the pass transistor operates in a smaller area and operates at a higher speed than a logic circuit combined with an ordinary CMOS CMOS circuit. Disclosure of the invention

The conventional pass transistor logic circuit described above operates at high speed with a small circuit area However, the use of two NMOSs (Ql and Q7) in the selector circuit limits the reduction in circuit area. In other words, since the selector circuit is composed of NMOSs (Ql, Q7), one of the input signals C of the gates of the two NM〇S (Ql, Q7) inputs the inverted control signal. Therefore, an inverter is required for this, and the area for this inverter increases. Further, in such a configuration, not only the circuit area but also the power consumption for driving the inverter increases.

FIG. 4 is a layout diagram of the conventional pass transistor logic circuit shown in FIG. 5, which was studied by the inventor prior to the present invention. In the figure, reference numeral 1 denotes a two-input selector circuit shown in FIG. The N-type semiconductor region 2 and the gate electrode 4 constitute the selector circuits Q 1 and Q 7, and the N-type semiconductor region 2-6 and the gate electrode 4 constitute the control signal inverting inverter 13. The PMOS constituting the inverter 13 is constituted by the P-type semiconductor region 3-6 and the gate electrode 4, and the N-type semiconductor region 2-1 and the P-type semiconductor region 3-1 and the gate electrode 4- The output inverter 12 is constituted by 1, and each transistor is connected by the metal wiring 6. As is clear from the figure, the area of the element corresponding to the semiconductor region constituting the inverter 13 has increased. In addition, the PMOS transistor must be formed on the upper side in the figure and the NMOS transistor must be formed on the lower side in the figure because of the formation of the p-well region, but since the number of NMOS transistors is larger than the number of PMOS transistors, the PMOS side As a result, an extra empty area is formed and an efficient layout cannot be achieved.

On the other hand, as a technique for removing the above-mentioned inverter for inverting the control signal, Japanese Unexamined Patent Publication No. Hei 6-13886 discloses that a transistor constituting a selector (corresponding to Ql and Q7 in FIG. 5) is formed by a PMOS and an NMOS. What constitutes is disclosed.

However, the present inventor has found that it is practically impossible to simply configure a selector circuit composed of PM〇S and NMOS on a so-called Balta substrate because of the following problems.

That is, in the case of a transistor using a bulk substrate as in the past, the PMOS gate potential is connected to the power supply, and a single-level input signal is applied to the output point of the selector circuit corresponding to the node d in FIG. When output, the potential at the output point goes low. O 7/0 752

Substrate bias is applied as the bell approaches. As a result, the threshold value rises due to the substrate bias effect, and the potential at the output point does not reach the complete ground level but remains at a potential substantially equal to the threshold voltage increased due to the substrate bias effect. . In addition, the NMOS transistor of the selector circuit using the pass transistor is connected to the ground, and when a high-level input signal is output to the output point, the potential of the output point approaches a high level. As a result, a substrate bias is applied, and the potential at the output point increases only to a potential obtained by subtracting the threshold voltage increased by the substrate bias effect from the power supply voltage. Therefore, in this case, the amplitude of the output signal at the output point corresponding to the node d is a value obtained by subtracting the threshold values of both NMOS and PMOS, which have risen due to the body bias effect, from the power supply voltage. The operating speed is extremely deteriorated under the power supply voltage (see Fig. 6 described later). For this reason, in a transistor simply formed on a bulk semiconductor substrate as in the conventional example, it is practically impossible to use both NMOS and PMOS as a selector circuit.

In consideration of the reduction of junction capacitance, etc., an example in which a pass transistor circuit is formed on a so-called SOI (semiconductor-on-insulator) substrate has been proposed in the fifth year of the Spring Meeting of the Institute of Electronics, Information and Communication Engineers, 1992. -181, as described in Section 1, uses NMOS for the selector circuit, and does not consider any increase in circuit area and power consumption due to the control signal inverting inverter. .

As described above, a path transistor logic circuit that takes advantage of the characteristics of a reduced circuit area and high-speed operation, but a logic circuit that satisfies both the reduced circuit area and high-speed operation regardless of the conventional technology. It is clear from the consideration of the present inventor that it is not possible to realize the above.

Accordingly, an object of the present invention is to provide a MIS type semiconductor device which satisfies demands for high speed operation and low power consumption while significantly reducing the area of a logic circuit using pass transistors.

Still another object of the present invention is to provide a layout of elements suitable for realizing the above-mentioned MIS semiconductor device.

Further objects of the present invention will become clear from the description and drawings of the present application. In order to achieve the above object, an MIS type semiconductor device according to a representative embodiment of the present invention is provided. The first MISFET (Q1) of the first conductivity type, the second MISFET (Q2) of the second conductivity type, which is a different conductivity type from the first conductivity type, and an input terminal An output buffer circuit (1 2) having a common drain buffer region, wherein one of the source and drain regions of the first MISFET and one of the source and drain regions of the second MISFET are shared by the output buffer. A gate electrode of the first MISFET and a gate electrode of the second MISFET are connected in common;

The first MISFET and the second MISFET are formed in a semiconductor base region (16, 17) formed on an insulating film (9).

As described above, by forming the pass transistor logic circuit with the P-type MISFET and the N-type MISFET, an inverter for inverting the control signal is not required, thereby reducing the circuit area and the power consumption. it can. Furthermore, by forming the substrate on a so-called SOI substrate on an insulating film, it is possible to prevent a reduction in operating speed due to the substrate effect and to enable a high-speed operation even at a low power supply voltage.

Further, in the MIS type semiconductor device according to another representative embodiment of the present invention, the first input signal (X) is applied to the other source / drain region of the first MISFET, and The second input signal (Y) is applied to the other source ♦ drain region of the MIS FET, and the first control signal (C 1) is commonly applied to the gate electrodes of the first and second MIS FETs. Is applied, and the first or second input signal is selectively transmitted to the first or second source / drain region according to the value of the first control signal. Can be configured.

Further, in the MIS type semiconductor device according to another representative embodiment of the present invention, the semiconductor base region includes a first region (16) and a second region (17) separated by an insulating film. The first MISFET (Q 1) is formed in the first region, the second MISFET (Q 2) is formed in the second region, and the first region is formed in the first region. When the inversion layer is formed in the channel region of the MIS FET, the depletion layer is completely depleted when the inversion layer is formed, and the inversion layer is formed in the channel region of the second MIS FET in the second region. By being configured to be completely depleted in some cases, the semiconductor substrate region can be operated in a floating state, and a high-speed circuit operation can be realized without receiving a substrate bias effect. Also, the MIS type semiconductor device according to another representative embodiment of the present invention has an output amplifying inverter (12) and another latch (14) an inverter so that the amplitude of the output signal of the circuit can be sufficiently increased. That can be kept.

Further, in the MIS type semiconductor device according to another representative embodiment of the present invention, the gate electrodes of the MIS transistors (Ql, Q2) forming the selector are formed of a tungsten material, so that the two transistors can be connected to each other. The threshold values can be made uniform, and the configuration is suitable for control by the common control signal (C1).

Also, an MIS type semiconductor device according to another representative embodiment of the present invention electrically connects the plurality of semiconductor regions (16, 17) formed on the insulating film (9) with the plurality of semiconductor regions. A first _n- type MI SFET (2) formed in a first semiconductor region, which is one of the plurality of semiconductor regions, having an isolation insulating film (1) to be separated;

A first p-type MISFET (3) formed in a second semiconductor region that is one of the plurality of semiconductor regions; and a third semiconductor region that is one of the plurality of semiconductor regions. A second n-type MI SFET (2-1), a second p-type MI SFET formed in a fourth semiconductor region that is one of the plurality of semiconductor regions, and (3-1) a power supply wiring (Vc c), ground wiring (GND), and first and second gate electrode wirings (4, 4-1), wherein the power supply wiring extends in a first direction, and the ground wiring Extends substantially parallel to the power supply wiring, and the first semiconductor region and the third semiconductor region are formed adjacent to the ground wiring in the first direction so as to overlap the ground wiring in a planar manner. The second semiconductor region and the fourth semiconductor region are formed adjacent to each other in the first direction so as to planarly overlap with the power supply wiring, and the first gate electrode is The second gate electrode extends commonly on the first and second semiconductor regions, and the second gate electrode extends commonly on the third and fourth semiconductor regions. One source 'drain region is connected to one source of the second MISFET. ♦ The drain region is connected to the second gate electrode by a first metal wiring (6). One source / drain region and one source / drain region of the fourth MISFET are connected by a second metal wiring (6-1), and the other source / drain region of the third MISFET is connected. Is connected to the ground wiring, and the other source / drain region of the fourth MISFET is connected to the power supply wiring. You.

With such a configuration, the above-described logic circuit can be efficiently laid out on the SOI substrate.

A MIS semiconductor device according to another representative embodiment of the present invention includes a third n-type MIS FET formed in a fifth semiconductor region, which is one of the plurality of semiconductor regions.

(2-2), the third p-type MISFET formed in the sixth semiconductor region, which is one of the plurality of semiconductor regions, and (3-2), the third gate electrode wiring (4-2). 2)) and wherein the fifth semiconductor region is disposed adjacent to the first semiconductor region in the first direction, and the sixth semiconductor region is disposed in the first direction. The third good electrode is arranged adjacent to the second semiconductor region, the third good electrode is commonly extended on the fifth and sixth semiconductor regions, and one of the source electrodes of the third n-type MISF ET is provided. The drain region is connected to one of the sources of the third p-type MISFET ♦ The drain region is connected to the other source of the first n-type MISFET ♦ The drain region is connected by the third metal wiring (6-2) It has been done. By arranging the transistors constituting the selector circuit adjacent to each other, a selector circuit having three or more inputs can be formed by a simple arrangement.

A MIS semiconductor device according to another representative embodiment of the present invention includes a fourth n-type MISFET formed in a seventh semiconductor region, which is one of the plurality of semiconductor regions.

(2-5), a fourth p-type MIS FET (3-5) formed in an eighth semiconductor region which is one of the plurality of semiconductor regions, and a fourth gate electrode wiring (4-5). (5) and a fourth metal wiring (6-5), wherein the seventh semiconductor region is arranged adjacent to the third semiconductor region in the first direction, and The semiconductor region is disposed adjacent to the fourth semiconductor region in the first direction, the fourth gate electrode extends commonly on the seventh and eighth semiconductor regions, and Second metal wiring above

(6), the fourth metal wiring is electrically connected to the first metal wiring and one of the source / drain regions of the fourth n-type MISFET and the fourth p-type MISFET. They are connected. According to the present invention, by adopting such a configuration, a selector circuit including the above-described latch inverter circuit (14) can be efficiently arranged. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a layout diagram showing a first embodiment which is a typical embodiment of the present invention. FIG. 2 is a circuit diagram showing a first embodiment which is a typical embodiment of the present invention.

FIG. 3 is a view showing a process flow of a first embodiment which is a typical embodiment of the present invention.

FIG. 4 is a layout diagram examined by the inventor of the present invention based on a circuit diagram of a conventional example. FIG. 5 is a circuit diagram showing a conventional example.

FIG. 6 is a diagram showing the drain voltage dependence of the gate delay time.

FIG. 7 is a layout diagram showing a second embodiment which is a typical embodiment of the present invention. FIG. 8 is a circuit diagram showing a second embodiment which is a typical embodiment of the present invention.

FIG. 9 is a layout diagram showing a third embodiment which is a typical embodiment of the present invention. FIG. 10 is a circuit diagram showing a second embodiment which is a typical embodiment of the present invention. FIG. 11 is a layout diagram showing a fourth embodiment which is a typical embodiment of the present invention.

FIG. 12 is a circuit diagram showing a fourth embodiment which is a typical embodiment of the present invention. FIG. 13 is a layout diagram showing a fifth embodiment which is a typical embodiment of the present invention.

FIG. 14 is a circuit diagram showing a fifth embodiment which is a typical embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, typical embodiments for carrying out the present invention will be described as examples.

In the following, a description will be given using a silicon MOS transistor (MOS FET). However, the operation principle is the same for a MOS transistor (MISFET) using another semiconductor material, and the present invention can be applied similarly. In the circuit diagram, n-type M

The OS transistor and the p-type MOS transistor are distinguished by the direction of the arrow shown in the channel portion.

A first embodiment of the present invention is shown in FIG. 1, FIG. 2 and FIG.

FIG. 2 is a circuit diagram showing a two-input selector according to the first embodiment of the present invention. No. The circuit shown in FIG. 2 is a basic configuration of a so-called two-input selector using pass transistors, and a desired logic circuit can be formed by this basic configuration or by appropriately combining this basic configuration.

As shown in FIG. 3 (e), the n-type MOS transistor Q1 and the p-type MOS transistor Q2 are formed on a thin-film SOI substrate. As shown in FIG. 2, one of the source'drain terminal of Q1 and one of the source'drain terminal of Q2 are commonly connected, and the common connection point is an inverter which is an output amplification buffer. It is connected to 12 input terminals, and is configured so that an output signal can be obtained from the output terminal OUT from INVERK 12. The other input X of the source and drain terminals of Q1 is supplied with the first input signal, the other input signal Y of the source and drain terminals of Q2 is supplied with the second input signal, and the gate terminals C of Q1 and Q2 are supplied. 1 is supplied with a common control signal. For convenience of description, the names of the terminals and the signals supplied to the terminals will be described using common reference numerals. The circuit in Fig. 2 shows one of the signals X and Y input to the source and drain terminals X and Y of the N-type MOS transistor (NM〇S) Q1 and the P-type MOS transistor (PMOS) Q2. Is selected by the control signal C1 directly connected to the gates of Q1 and Q2, and the inverted signal is output to the OUT terminal through the output amplification inverter. When C1 is at the high level, the signal at the X terminal is selected, and when it is at the single level, the signal at the Y terminal is selected. The inverted signal is output to the OUT terminal through the inverter 12 of the output amplifier. In the present embodiment, since Q 1 and Q 2 are configured as n-type and p-type, respectively, even if the control signal C 1 is commonly supplied to each gate electrode, only one input signal is supplied to the inverter 12. This eliminates the need to invert the control signal as in the prior art. Here, if the same input signal as that of the X terminal is input to the C1 terminal, this circuit becomes a logic circuit that operates as a two-input NAND circuit.

FIG. 1 is a layout diagram of the first embodiment formed on a thin-film SO 1 substrate, and FIG. 3 shows a manufacturing method thereof.

First, a method for forming a semiconductor device according to the present embodiment will be described with reference to FIGS. 3 (a) to 3 (e). The cross-sectional view shown in FIG. 3 is AA ′ in FIG.

FIG. 3 (a) shows an SOI structure substrate on which the semiconductor device of the present invention is formed. The SOI substrate has a thickness of about 400 on the semiconductor substrate 11 made of silicon single crystal. An oxide film 9 which is an insulating film of nm is formed, and a thin film semiconductor layer 10 of about 100 nm serving as a base on which a MOS transistor is formed is formed thereon. Although not particularly limited, such a Si substrate can be thermally treated by bonding an Si (silicon) substrate having an oxide film formed thereon to another Si substrate, or by implanting oxygen ions into the Si substrate. Can be formed.

Next, as shown in FIG. 3 (b), a protective oxide film 15 on the surface and an element isolation region 20 are formed by thermal oxidation. The element isolation region 20 is a LO COS oxide film (local oxide film) formed by a so-called selective oxidation method. The semiconductor regions .16 and 17 serving as bases are formed to a thickness of about 100 nm or less, and each have an impurity concentration of about 1 × 10 ¹⁶ cm ³ . This is for controlling the semiconductor regions 16 and 17 to be completely depleted during the operation of the circuit, and by thus depleting the semiconductor regions to a floating state without applying a substrate potential to the semiconductor regions. This is to enable operation without being affected by the effect. In addition, the element isolation region 1 is formed so as to be in contact with the insulating film 9 constituting the SOI substrate, so that the region for forming the transistor can be completely separated for each transistor to ensure electrical insulation. Can be done. After the element isolation region 1 and the surface protection oxide film 15 are formed, impurities for controlling the threshold are introduced into the region 16 where the n-channel MOS transistor is formed and the region 17 where the p-channel MOS transistor is formed. The surface protective oxide film 15 protects the surface of the base when powerful impurities are introduced by ion implantation. In this embodiment, 2 × 10 12 cm 2 ion implantation of phosphorus at 30 keV is performed on the PMOS channel region 16 so as to obtain a desired threshold value. In the channel region 17 of the NMOS, boron is ion-implanted at 50 keV into 2 × 10 12 squared Z square cm.

Thereafter, as shown in FIG. 3 (c), after removing the surface protection oxide film 15, a gate oxide film 7 of about 6 nm is formed by thermal oxidation. Next, tungsten is vapor-deposited on the entire surface and processed into a desired shape to form gate electrodes 4 and 4-1. In this embodiment, the work function between the high-concentration n-type silicon and the high-concentration p-type silicon is set so that the threshold values of NM OS and PMOS become the desired value (0.2 to 0.5 V in absolute value) with one gate material. With tungsten. As a gate material, a polycrystalline silicon film into which impurities are introduced, or a laminated film of a polycrystalline silicon film and a metal material can be used.

The threshold voltage is lower when using n-type impurity-doped polycrystalline silicon as the NMOS gate electrode, and when using p-type impurity-doped polycrystalline silicon. (It fluctuates similarly in the case of PMOS, but the fluctuation is upside down as in the case of NMOS). Therefore, in order to match the threshold values of both MOSs, the work function between polycrystalline silicon with a high concentration of n-type impurity introduced and polycrystalline silicon with a high concentration of p-type impurity introduced must be determined. It is desirable to use W (tungsten) or the like for the gate electrode. In the case of this embodiment, since a control signal is applied to both transistors in common, it is necessary to control the value voltage to the same value. It is to be noted that TiN (titanium nitride) and Mo (molybdenum), which are materials having a work function equivalent to that of tungsten, can also be used. However, considering the low resistance, etc., the tungsten used in the present embodiment is used. Is more preferable.

Next, as shown in FIG. 3D, the source and drain regions of the MOS transistor are formed by ion implantation. Arsenic is ion-implanted on the NMOS side at 3 O ke V at 2 × 10 15 square cm, and self-aligned using the gate electrode and isolation oxide film as a mask, the n + source / drain region 2 -Form one. In the PMOS, boron fluoride is ion-implanted at 30 keV at 2 × 10 15 square cm, and the p + source / drain region 3 is formed in a self-aligned manner. Next, as shown in FIG. 3 (e), an oxide film 8 is deposited in the same manner as in a normal wiring forming step, a contact hole 5 is processed, and then an anoremi is deposited and processed into a desired pattern. Metal wiring 6, 6-1. Further, the second-layer interlayer insulating film 16 and the second-layer metal wiring 17 are processed in the same manner and completed. If necessary, the third and fourth layers and wiring can be stacked.

Through such a process, the semiconductor integrated circuit of this embodiment can be formed. FIG. 3 (e) shows a completed cross-sectional view of this embodiment, omitting the final passivation protective film and the like. As is clear from the figure, in this example, an NMOS and a PMOS are formed on a so-called SOI substrate, and these transistors form the circuit shown in FIG. FIG. 1 shows a layout diagram of the present embodiment. 1 in FIG. 1 shows the layout when the two-input selector circuit shown in FIG. 2 is formed on a semiconductor substrate as a semiconductor integrated circuit. Although FIG. 1 shows one layout diagram of a two-input selector circuit, a desired logic circuit can be obtained by appropriately arranging and wiring a plurality of selector circuits in accordance with this layout. In the present embodiment, a cell 1 which is one unit circuit block is constituted by a two-input selector circuit, another cell is constituted in another 1-1 part on the right side of the drawing, and a cell row is arranged in a horizontal direction in the drawing. Is configured. In addition, channel regions 101 and 102 extending in the horizontal direction are formed at the upper and lower portions of the cell column, and wiring 103, 104, 105, etc. are provided between cells and between cell columns. (Note that the wirings 102 to 105 in the figure are only schematic and detailed description is omitted. The wiring of the channel region 102 is also the same. Omitted).

In Fig. 1, 2 and 2-1 are n-type semiconductor regions serving as source and drain regions of n-type MOS, and 3 and 3-1 are p-type semiconductor regions serving as source and drain regions of p-type MOS. Reference numerals 4 and 4-1 denote gate electrodes of the MOS transistors, which are formed on the semiconductor substrate through a relatively thin gate insulating film 7 by tungsten, polycrystalline silicon, or a laminated film of polycrystalline silicon and silicide. You. Reference numerals 6 and 6-1 denote metal wirings, which are formed of a metal material containing aluminum as a main component or the like on a wiring layer on which a gate electrode is formed via an interlayer insulating film. Further, as described above, the unit circuits and the like shown in FIG. 1 are repeatedly arranged in a row in the left-right direction of the drawing to form a so-called cell row. Further, a plurality of cell rows are formed as wiring areas between the cell rows. It is arranged and wired in the vertical direction of the drawing via the channel regions 101 and 102 to form a desired logic circuit.

The semiconductor region 2 is a semiconductor region constituting the n-type MOS transistor Q1 shown in FIG. Q 1 is configured as one of the switches of the selector circuit, and is configured so that the input signal X is supplied to the drain region of the semiconductor region 2 via the output of the adjacent cell or the wiring of the channel region. You. Further, a gate electrode 4 is formed on the semiconductor region 2, and a control signal C1 is supplied from outside the two-input selector circuit 1 via a contact through a contact.

The semiconductor region 3 is a semiconductor that constitutes the p-type MOS transistor Q2 shown in FIG. Similarly, the input signal Y is supplied to the drain region, and the control signal C 1 is supplied via the gate electrode 4. In this embodiment, since the channel conductivity types of Q1 and Q2 are different, the control signal C1 can be commonly supplied to both transistors without inversion, so that the gate electrode 4 is common to both transistors even in the layout. It can be that of. In this embodiment, the gate electrode 4 extends in the vertical direction with respect to the semiconductor regions 2 and 3 arranged vertically in the figure, and extends on both semiconductor regions. The semiconductor regions 2-1 and 3-1 and the gate electrode 4-1 form an n-type MOS and a p-type MOS which form the inverter circuit 12 in FIG. The gate electrode serving as the input of the inverter circuit 12 is connected in common with the source areas of Q1 and Q2 forming the selector, and extends in common on both semiconductor areas. Further, a portion corresponding to the drain region in both semiconductor regions is connected in common by the metal wiring 6-1 so that the output OUT can be taken out. This output is wired so that V, which is the input signal of another selector circuit, becomes a control signal as necessary.

Further, in this embodiment, wiring (V cc, GND) for supplying the power supply voltage V cc and the ground potential GND as the reference potential to the circuit extends above and below the basic circuit forming the cell in the horizontal direction of the drawing. Are located. The power supply wiring and the ground wiring 6 are configured to extend along the cell row so that they can be shared by the above-described cell row. Here, the power supply voltage wiring V cc is arranged so as to overlap the p-type semiconductor region 3-1 in a plane so as to supply the power supply voltage and the ground potential to the inverter circuit 12, and the p-type semiconductor region 3 is connected via the contact hole. -Connected to one. Similarly, the ground potential wiring G-ND is arranged so as to overlap the n-type semiconductor region 2-1 in a plane, and is connected to the n-type semiconductor region 2-1 via a contact hole. When the input signal is fixed to the power supply voltage Vcc or the ground potential GND by the logic realized by the selector circuit, these wirings are connected to the semiconductor region 2 or 3. In the present embodiment, the metal wirings 6 and 61, the power supply voltage wiring Vcc, and the ground potential wiring GND are formed in the same wiring layer.

According to the present embodiment, the semiconductor regions 3-1 and 2-1 are spaced apart in the vertical direction in the figure. This is to ensure a contact space between the metal wiring 6 and the gate electrode wiring 4-1 between both regions. Also, the semiconductor regions 3-1 and 3 are H! The semiconductor regions 2-1 and 2 are arranged adjacent to each other in the left-right direction, and the semiconductor regions 3 and 2 have the same spacing as the semiconductor regions 3-1 and 2-1. It is arranged with.

As described above, according to the present embodiment, the two-input selector portion using Ql and Q2 can be formed with a simple layout similar to a normal CMOS inverter, and an inverter for forming an inverted signal is not required, so that an extremely small area is required. Can be formed.

FIG. 4 is a layout diagram of the conventional two-input selector circuit shown in FIG. 5 studied by the inventor using a standard layout method. In FIG. 4, the same reference numerals as those in FIG. 1 denote the same parts, and a detailed description thereof will be omitted. Comparing FIG. 4 with FIG. 1, it is clear that a two-input selector circuit that realizes the same circuit function can be realized with an area of approximately 1 × 2.

Fig. 6 shows the voltage dependence of the gate delay time (the delay time from the signal input to the output of the two-input selector circuit), with the horizontal axis representing the power supply voltage of the circuit and the vertical axis representing the gate delay. Shows time. Fig. 6 (1) shows the characteristics of the circuit composed of nMOS on the Balta substrate described at the beginning of the conventional example, and Fig. 6 (2) shows the characteristics of the circuit described on the second example of the conventional example. This shows the characteristics of a circuit formed using NMOS and PMOS, and FIG. 6-3 shows the characteristics of the circuit according to the present embodiment. As is clear from FIG. 6, in the present invention using the SOI substrate, the threshold value can be reduced and the junction capacitance can be reduced, so that the gate delay time is about 30% as compared with the conventional example 1. It is possible to increase the speed. Also, in the conventional example 2, the delay time is rapidly increased at a low power supply voltage, and the present invention can also achieve a higher speed.

Next, a second embodiment of the present invention will be described. FIG. 7 shows a layout diagram of this embodiment, and FIG. 8 shows a circuit diagram thereof.

The circuit diagram shown in FIG. 8 shows a three-input selector circuit in which the two-input selector circuit shown in FIG. 2 is connected in two stages. In the description of the present embodiment, a description of parts that are the same as in the first embodiment will be omitted, and different parts will be mainly described. In FIG. 7, other cells and channel regions are not shown, but can be configured in the same manner as in the first embodiment. PC J 5 /

14

The NMOS transistors Q 3 and Q 1 and the PMOS transistors Q 4 and Q 2 are each formed on the S 0 I substrate as shown in FIG. 3 and formed by the method shown in FIG. 3. Is what you can do. Q 3 and Q 4 have one of their source and drain terminals connected in common, and the other of their source and drain terminals receive input signals L and M, and a control signal C 2 is commonly shared by the gate electrodes. It is configured to receive. Similarly, Q 1 and Q 2 are also configured such that one source / drain terminal is commonly connected and a control signal C 1 is commonly supplied to a gate electrode. Here, the other source / drain terminal of Q1, which is one of the transistors constituting the 2-input selector, is connected to the commonly connected source / drain terminals of Q3 and Q4, and the other of Q2 The source ♦ drain terminal is configured to receive another input signal N.

Thus, in the present embodiment, one of the signals input to the input terminals L and M of the source Z drain regions of Q 3 and Q 4 is first selected by the control signal input to the C 2 terminal, and Is output. Next, one of the input to the node e and the input to the N terminal is selected by the control signal input to the C1 terminal, and the inverted signal is output to the OUT terminal through the inverter 12 of the output amplifier. Also in this embodiment, a desired logic circuit can be realized by supplying appropriate signals to the input signal and the control signal. FIG. 7 shows a layout diagram of the circuit shown in FIG. As shown in FIG. 7, semiconductor region 3 is a P-type semiconductor region forming transistor Q2, semiconductor region 2 is an N-type semiconductor region forming transistor Q1, and semiconductor region 3-1 forms inverter 12 The P-type semiconductor region and the semiconductor region 2-1 are N-type semiconductor regions that also constitute the inverter 12. This is the same as the layout diagram of the two-input selector circuit shown in FIG. 2. In the present embodiment, the semiconductor regions 2-2 and Q4 forming the semiconductor regions Q3 and Q4 are formed in the two-input selector circuit. A region 3-2 and 4-2 forming a common gate electrode are added. The semiconductor regions 3-2 and 2-2 are formed continuously to the left of the semiconductor regions 3 and 2, and the gate electrode 4-2 extends in the vertical direction in the drawing, and Q 3 and The source / drain regions of Q4 are commonly connected by metal wiring 6-2, and are also connected to the source / drain regions of Q1. In the present embodiment, unlike the first embodiment, the semiconductor regions 3-1 and 2-1 are arranged without an interval corresponding to the contact space. For this reason, the circuit area constituting the cell 1 is reduced, and the useless space between the semiconductor regions 3 and 2 as in the first embodiment can be eliminated. The semiconductor regions 2 and 3 are connected to the gate electrode wiring 4-1 by connecting the semiconductor regions 2 and 3 with the metal wiring 6, and the metal wiring 6 and the gate electrode 4-1 are different from the metal wiring 6. Are connected by a metal wiring 17 and a metal wiring 6-6 using a second wiring layer as a wiring layer. Such a layout and wiring method according to the present embodiment can be similarly applied to other embodiments. Further, the three-input selector circuit of the present embodiment can also be configured by an arrangement in which a contact space is provided between the semiconductor regions 3-1 and 2-1 as shown in FIG. In this case, it is not necessary to use the second wiring layer 17 in the cell, so that the degree of freedom when wiring between cell columns is performed in the second layer can be increased.

In the present embodiment, the semiconductor regions 3-2 and 2-2 are arranged adjacent to the semiconductor regions 3 and 2 and on the side opposite to the semiconductor regions 3-1 and 2-1. Thus, the semiconductor regions 3-2, 2-2, and 2 can be arranged close to each other, and the metal wiring 6-2 can be connected efficiently over a short distance.

As described above, according to the present embodiment, since an inverter circuit for inverting the control signal is not required, a simple configuration in which Q3 and Q4 are simply added to the layout diagram shown in FIG. the 3 _¾ can constitute an input selector circuit also inverters - capacitor circuit is reduced occupied area of the circuit only unnecessary min, it is possible to form a three-input selector circuit in a very small area.

Next, a third embodiment of the present invention is shown in FIG. 9 and FIG. In this embodiment, the case where the present invention is applied to the four-input selector circuit shown in FIG. 10 will be described. In the description of the present embodiment, portions that are the same as those in the first and second embodiments will not be described, and different portions will be mainly described. In FIG. 9, other cells and channel regions are omitted, but can be configured in the same manner as in the first embodiment.

The selector circuit shown in FIG. 10 includes an NMOS transistor Q3 and a PMOS transistor. It comprises a two-input selector circuit composed of a star Q4, a two-input selector circuit composed of a NMOS transistor Q5 and a PMOS transistor Q6, and a selector circuit for selecting their outputs. As in the first and second embodiments, the NMOS transistor and the PMOS transistor constituting the selector circuit are each formed on an SOI substrate and can be formed by the process shown in FIG.

Transistors Q3 and Q4 have one source / drain terminal connected in common, and the other source / drain terminals are supplied with input signals L and M, respectively. The control signal C2 is commonly connected to each gate electrode. As in the other embodiments, since Q3 and Q4 are transistors of different conductivity types, an inverter for inverting the control signal is not required, and the control signal is applied to the gate electrodes of both transistors in common. I have. Transistors Q5 and Q6 have one source / drain terminal connected in common, and the other source / drain terminals are supplied with input signals 0 and P, respectively. A control signal C3 is commonly applied to each gate electrode. Transistors Q 1 and Q 2 also have one source and drain connected in common, but the other source 'drain of Q 1 is connected to the common connection point of Q 3 and Q 4 and the other of Q 2 The source ♦ drain terminal is connected to the common connection point of Q5 and Q6.

In this embodiment, the outputs of a two-input selector composed of NMOS, Q5, PMOS, and Q6 are further connected to the inputs of the source / drain regions of Q2 in the second embodiment. One of the signals input to the input terminals 0 and P of the source / drain regions of Q5 and Q6 is first selected by the control signal input to the C3 terminal, and is output to the node f. Similarly, the input terminals of the source and drain regions of Q3 and Q4, one of the signals input to M is selected by the control signal input to the C2 terminal, and output to the node _e . Next, one of the input of the node e and the input of the node ί is selected by the control signal input to the C1 terminal, and an inverted signal is output to the OUT terminal through the inverter 12 of the output amplifier. Also in this embodiment, a desired logic circuit can be realized by supplying appropriate signals to the input signal and the control signal.

FIG. 9 shows a layout when the four-input selector circuit of this embodiment is formed on an SOI substrate. FIG. The layout diagram of this embodiment has a form in which a two-input selector is further added to the left side of the layout of the three-input selector circuit in FIG.

The semiconductor region 2-3 is an n-type semiconductor region forming an n-type MOSQ5, the semiconductor region 3-3 is a p-type semiconductor region forming a p-type MOSQ6, and 4-3 is a control signal common to Q5 and Q6. This is the gate electrode to be supplied. The semiconductor regions 23 and 3-3 are commonly connected by the metal wiring 6-3, and at the same time, are connected to the semiconductor region 3 forming Q2.

As described above, a two-input selector is added to the left of the second embodiment, and an inverter for inverting the control signal of C3 is not required. An input selector can be formed.

In the layout of the present embodiment, the semiconductor regions 3, 3-2, 3-3 are arranged on a substantially straight line S, and the semiconductor region 3-1 protrudes upward in FIG. . This is because, in order to secure a contact space between the metal wiring 6 and the gate electrode 4-1, the semiconductor regions 3-1 and 2-1 are vertically separated from each other in the figure, and the metal wiring 6-3 and the power supply are separated. This is to allow a sufficient margin between the wiring Vcc and the margin margin. The circuit area in the vertical direction increases by the amount of the contact space between the metal wiring 6 and the gate electrode 4-1.However, wiring outside the cell must be performed using the metal wiring of the second layer as shown in Fig. 7. This has the advantage that it does not hinder the case where wiring between cell columns is performed by the second-layer metal wiring. Such a layout can be similarly adopted in the layouts of FIGS. 1, 7, and 11. In this case, the semiconductor regions other than those that do not require a contact space by separating the semiconductor regions (regions 2 and 3 in FIG. 1, regions 2 and 3 in FIG. 7, 2-2 and 3-2, and 11 2 and 3, 2-2 and 3-2, 2-3 and 3-3, 2-4 and 3-4) may be arranged close to each other as in this embodiment.

As described above, according to the present invention, a circuit for selecting an arbitrary number of inputs is formed by further adding a two-input selector to the input terminal in the same manner as in the second or third embodiment. It can be formed simply by adding another two-input selector on the left side of this embodiment, and it can be formed extremely simply and with a small area. Can be.

Next, FIG. 11 shows a planar structure of a fourth embodiment in which the basic circuit of the present invention is combined, and FIG. 12 is a circuit diagram thereof.

The circuit shown in Fig. 12 realizes the desired logic by adding a two-input selector circuit composed of transistors Q7 and Q8 and an inverter 12 to the input terminal M of the three-input selector circuit shown in Fig. 8. Circuit. In the description of this embodiment, a description of parts that are the same as those of the first to third embodiments will be omitted, and different parts will be mainly described. In FIG. 11, the illustration of other cells and channel regions is omitted, but the configuration can be the same as in the first embodiment.

In order to realize such a combination of the selector circuit and the inverter, as shown in FIG. 11, the inverter circuit (semiconductor area 2) extends in the horizontal direction with respect to the layout of the selector circuit shown in FIG. -4 and 3-4, the gate electrode 4-4) and the selector circuit (semiconductor regions 2-3 and 3-3, the gate electrode 4-3) are added, and the metal wiring (6-3, It can be realized by connecting according to 6-4). As described above, according to the present embodiment, as described above, a logical combination can be achieved by simply arranging and connecting the basic selector circuit and the inverter circuit in the horizontal direction. Can be realized.

Next, a fifth embodiment of the present invention will be described with reference to the layout diagram of FIG. 13 and the circuit diagram of FIG. The present embodiment has a configuration in which a latch circuit is provided in the output amplification inverter 12 of the first embodiment shown in FIGS. 1 to 3. In the description of the present embodiment, description of portions that are the same as in the first to fourth embodiments will be omitted, and different portions will be mainly described. In FIG. 13, other cells and channel regions are not shown, but can be configured in the same manner as in the first embodiment.

The two-input selector circuit in Fig. 14 connects the input of a latch inverter 14 (consisting of a CMOS transistor) to the output of an inverter 12 for output amplification, and outputs the output to an inverter 1. It is configured to connect to node c which is the input of 2. Also, NMO S? ^! 03 The gate width of the FET is sufficiently smaller than that of the inverter 12 It is configured not to hinder the movement of the inverter 12. It should be noted that a similar effect is obtained even if the gate length of the inverter 14 is increased. However, at the same time, an increase in gate capacitance and the like are caused.

As in the first embodiment, when the latch inverter 14 is not provided, there is a possibility that the voltage of the node c becomes lower than the power supply voltage by the threshold value of NMOS, even when the value of the node c is at the high level. For example, when a high-level signal substantially equal to the power supply voltage is input to the input signal X and a similar high-level signal is applied as the control signal C1, the output voltage is changed from the input signal X to the NM OSFETQ1. The voltage drops by the threshold voltage. Therefore, when the power supply voltage is low, or when such a selector circuit is configured in multiple stages, the driving force of the inverter 12 is weak and the operation tends to be slow.

On the other hand, in this embodiment, since the latching inverter 14 is formed, the value of the output terminal OUT becomes low level and the output of the inverter 14 becomes high level, and the PMO constituting the inverter 14 becomes The node c is fully charged to the power supply voltage by the SFET and rises to the power supply voltage. Therefore, the voltage loss due to the threshold voltage of the transistor can be compensated by the inverter 14 as in the present embodiment, and the operation of the inverter 12 can be accelerated. Similarly, when a low-level signal is input to the input terminal Y of the PMOSQ 2 and a low-level control signal is also input to the gate electrode, the potential of the node c is similarly grounded by the NMOS transistor of the inverter 14. It can be lowered to the potential. -Next, Fig. 13 shows the layout that realizes this circuit.

In FIG. 13, a latch inverter 14 is formed on the right side of the layout shown in FIG. The inverter 14 includes a semiconductor region 2-5 forming an n-type MOS, a semiconductor region 3-5 forming a p-type MOS, and a gate electrode 4-5 commonly formed by both transistors. The semiconductor regions 2-5 and 3-5 are configured to have a smaller width in the vertical direction in the figure than the other semiconductor regions (for example, 2 and 3) in order to reduce the gate width of both transistors. The metal wiring for supplying the power supply voltage Vcc and the ground power GND is accordingly protruded.

The gate electrode 4-5 which is the input of the inverter 14 is the output of the inverter circuit 12 Connected to the metal wiring 6-1. A semiconductor region serving as a drain region of both transistors serving as an output of the inverter 14 is commonly connected by an umbrella wiring 6-4. The connection between the output of the inverter 14 and the common connection point of the transistors Q1 and Q2 is made by the metal wiring 19 via the contacts 18 and 18-5. Since the metal wiring 17 extends in the horizontal direction in the drawing, the second-layer metal wiring which is a wiring layer different from the metal wiring 6-1 etc. so as not to overlap with the metal wiring 6-1 etc. It consists of.

According to this embodiment, a pass transistor logic circuit with a small increase in delay time even at a low voltage can be realized, and can be formed in a small area with an extremely simple layout. In this embodiment, an example of a two-input selector circuit is shown. However, as is clear from the second to fourth embodiments, adding a selector circuit to the left in FIG. A selector circuit can be configured.

Note that the output amplification inverter circuits 12 are arranged for each of the number of selector circuits (for example, two or three) to compensate for the reduction in drive capability due to the serial connection of the selector circuits. Is provided corresponding to the inverter circuit 12 to compensate for the output of the selector circuit. Therefore, in the other embodiments, the same effect as that of the present embodiment can be obtained by providing the inverter circuit for latching of the present embodiment in addition to the inverter circuit for output amplification.

As described above with reference to the first to fifth embodiments, the MIS type semiconductor device according to the representative embodiment of the present invention uses a transistor formed on a thin-film SOI substrate and uses two transistors of a two-input selector circuit. One of the transistors is set to PMOS, and the control signal input to the gate is made common to the other transistor (NMOS).

In a typical embodiment of the present invention, the underside of the channel regions 16 and 17 of the transistor formed on the so-called thin film SOI is covered with the insulating film 9 and thus connected to any potential. Not in a so-called floating state. Therefore, the body bias effect is extremely small, and the threshold value is almost constant regardless of the source potential. Even if PMOS is used for one transistor of the two-input selector as in the circuit in Fig. 2, the single-level signal input to PMOS is applied to node C. When the output is made, only the threshold when the substrate bias is not applied and the potential corresponding to the value remain. Furthermore, the SOI transistor can lower the threshold voltage without increasing the leakage current by taking advantage of the rapid subthreshold characteristics, so that the voltage remaining at the node c is lower than when a bulk substrate is used. Become smaller. For the above reason, by using PMOS for one transistor of the two-input selector circuit formed on the SOI, the area can be reduced by eliminating the need for an inverter for generating an inverted signal. In addition, power consumption can be reduced as an inverter is not required.

Furthermore, high speed can be achieved by taking advantage of the high drive current and low junction capacitance of the SOI structure transistor.Since no module region is required, the width of the element isolation region can be reduced and the area can be further reduced. . Industrial applicability

As described above, according to the present invention, an inverter for generating an inverted signal input to the gate of the two-input selector circuit is not required, and the area can be reduced. In addition, power consumption can be reduced by eliminating the need for an inverter, and higher speeds can be achieved by taking advantage of the high drive current and low junction capacitance of SOI transistors.

Therefore, the present invention can be widely used for logic circuits formed by semiconductor integrated circuits.

Claims

The scope of the claims

1. a first MIS FET of a first conductivity type;

A second MIS FET of a second conductivity type, which is a conductivity type different from the first conductivity type, and an output buffer circuit having an input terminal;

One source of the first MISFET ♦ The drain region and one of the source / drain regions of the second MISFET are commonly connected to the input terminal of the output buffer circuit,

The gate electrode of the first MISFET and the gate electrode of the second MISFET are connected in common,

The MISFET type semiconductor device, wherein the first MISFET and the second MISFET are formed in a semiconductor base region formed on an insulating film. ·

2. The MIS type semiconductor device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

3. A first input signal is applied to the other source / drain region of the first MIS FET, and a second input signal is applied to the other source / drain region of the second MIS FET. A first control signal is commonly applied to the gate electrodes of the first and second MISFETs, and the first or second input signal is selectively applied according to the value of the first control signal. 2. The MIS type semiconductor device according to claim 1, wherein the MIS type semiconductor device is transmitted to a first or second source / drain region.

4. The semiconductor substrate region has a first region and a second region separated by an insulating film,

The first MISFET is formed in the first region, the second MISFET is formed in the second region,

The first region is configured to be completely depleted when an inversion layer is formed in the channel region of the first MISFET,

The second region is configured to be completely depleted when an inversion layer is formed in a channel region of the second MISFET. 2. The MIS semiconductor device according to claim 1.

. A semiconductor substrate region formed on the insulating film;

An _n- type MIS transistor and a p-type MIS transistor formed in the semiconductor substrate region,

First and second inverter circuits,

One of the source and drain electrodes of the n-type MIS transistor and the p-type MIS transistor is commonly connected to the input of the first inverter circuit, and the gate of the n-type MIS transistor and the p-type MIS transistor is connected. Electrodes are connected in common,

An input of the second inverter circuit is connected to an output of the first inverter circuit, and an output of the second inverter circuit is connected to an output of the first inverter circuit; Type semiconductor device.

The first inverter circuit and the second inverter circuit each have an n-type MIS transistor and a p-type MIS transistor connected in series, and form an n-type MIS transistor and a second inverter circuit. 6. The MIS type semiconductor device according to claim 5, wherein an MIS transistor and a p-type MIS transistor are formed on the semiconductor substrate.

The n-type MIS transistor and the p-type MIS transistor constituting the second inverter circuit have their gate electrodes commonly connected to the output of the first inverter circuit, and their drain electrodes are commonly connected to the first inverter circuit. The source electrode of the n-type MIS transistor is connected to the ground potential of the circuit, and the source electrode of the p-type MIS transistor is connected to the power supply voltage of the circuit. 7. The MIS type semiconductor device according to claim 6, wherein:

The semiconductor substrate region has first and second regions separated by a local oxide film, the n-type MIS transistor is formed in the first region, and the p-type MIS transistor is formed in the second region. 6. The MIS type semiconductor device according to claim 5, wherein the MIS type device is formed in a region defined by:

The first region is configured to be completely depleted when forming the inversion layer of the n-type MIS transistor, 9. The MIS semiconductor device according to claim 8, wherein the second region is configured to be completely depleted when the inversion layer of the p-type MIS transistor is formed.

10. a semiconductor substrate;

An insulating film formed on the semiconductor substrate,

A plurality of semiconductor substrates formed on the insulating film,

An isolation oxide film for electrically separating the plurality of semiconductor substrates; an n-type MIS transistor is formed on one of the plurality of semiconductor substrates; A p-type MIS transistor is formed, and one of the n-type MIS transistor and the p-type MIS transistor has one source ♦ drain region connected in common,

A first input signal is applied to the other source / drain region of the n-type MIS transistor,

A second input signal is applied to the other source / drain region of the P-type MIS transistor,

A gate electrode of the n-type MIS transistor and a gate electrode of the p-type MIS transistor are connected in common, wherein the MIS-type semiconductor device is characterized in that:

1 1. A control signal is commonly applied to the gate electrodes of the n-type MIS transistor and the p-type MIS transistor,

10. The MIS semiconductor device according to claim 10, wherein said control signal selectively controls the conduction state of said n-type MIS transistor and said p_-type MIS transistor.

12. The MIS semiconductor device according to claim 11, wherein a gate electrode of said n-type MIS transistor and a gate electrode of said p-type MIS transistor are formed of tungsten.

13. The MIS semiconductor according to claim 12, wherein a threshold voltage of the n-type MIS transistor and a threshold voltage of the p-type MIS transistor are substantially equal to each other. apparatus.

14. a plurality of semiconductor regions formed on the insulating film; An MIS type semiconductor device comprising: an isolation insulating film for electrically isolating the plurality of semiconductor regions;

A first n-type MISFET formed in a first semiconductor region that is one of the plurality of semiconductor regions;

A first p-type MISFET formed in a second semiconductor region that is one of the plurality of semiconductor regions;

A second n-type MIS FET formed in a third semiconductor region which is one of the plurality of semiconductor regions;

A second p-type MISFET formed in a fourth semiconductor region that is one of the plurality of semiconductor regions;

A power wiring, a ground wiring, and first and second gate electrode wirings, wherein the power wiring extends in a first direction, and the ground wiring extends substantially parallel to the power wiring. ,

The first semiconductor region and the third semiconductor region are formed adjacent to each other in the first direction so as to overlap the ground wiring in plan view,

The second semiconductor region and the fourth semiconductor region are formed adjacent to each other in the first direction so as to overlap the power supply wiring in a plane, and

The first gate electrode extends in common on the first and second semiconductor regions, and the second gate electrode extends in common on the third and fourth semiconductor regions. The first source / drain region of the first MIS FET and the one source / drain region of the second MIS FET are connected to the second gate electrode by a first metal wiring. ,

One source and drain region of the third MISFET and one source and drain region of the fourth MISFET are connected by a second metal wiring, and the other source and drain of the third MISFET are connected. The area is connected to the above ground wiring,

The MIS type semiconductor device, wherein the other source / drain region of the fourth MIS FET is connected to the power supply wiring.

5. The other source and drain regions of the first MIS FET are connected to the first input signal. Signal is applied, a second input signal is applied to the other source / drain region of the second MISFET, a control signal is applied to the first gate electrode wiring, and the first input 15. The MIS semiconductor device according to claim 14, wherein a signal or said second input signal is selectively transmitted to said second gate electrode wiring in response to said control signal.

16. The first and second gate electrode wirings are formed by the same wiring layer,

The first metal wiring, the second metal wiring, the power supply wiring and the ground wiring are the same.

15. The MIS type semiconductor device according to claim 14, wherein the MIS type semiconductor device is formed by the following wiring layer.

1 7. The above MIS type semiconductor device

A third n-type MISFET formed in a fifth semiconductor region that is one of the plurality of semiconductor regions;

A third p-type MISFET formed in a sixth semiconductor region, which is one of the plurality of semiconductor regions,

A third gate electrode wiring,

The fifth semiconductor region is disposed adjacent to the first semiconductor region in the first direction,

The sixth semiconductor region is arranged adjacent to the second semiconductor region in the first direction,

The third gate electrode extends in common on the fifth and sixth semiconductor regions, and has one source / drain region of the third n-type MISFET and the third p-type MISFET. 15. The MIS type according to claim 14, wherein one source / drain region and the other source / drain region of said first n-type MISFET are connected by a third metal wiring. Semiconductor device.

18. The above MIS type semiconductor device

A fourth n-type MIS FET formed in a seventh semiconductor region, which is one of the plurality of semiconductor regions,

A fourth p-type MISF ET formed in an eighth semiconductor region, which is one of the plurality of semiconductor regions, A fourth gate electrode wiring,

And a fourth metal wiring,

The seventh semiconductor region is arranged adjacent to the third semiconductor region in the first direction,

The eighth semiconductor region is arranged adjacent to the fourth semiconductor region in the first direction,

The fourth goodt electrode extends commonly on the seventh and eighth semiconductor regions, and is connected to the second metal wiring,

The fourth metal wiring is electrically connected to the first metal wiring and one of the source / drain regions of the fourth n-type MISFET and the fourth p-type MISFET. 15. The MIS type semiconductor device according to claim 14, wherein: 19. The MIS type semiconductor according to claim 18, wherein the fourth metal wiring is formed by a wiring layer different from the first and second metal wirings. apparatus.

20. The gate width of the fourth n-type MISFET is smaller than the gate width of the second n-type MISFET, and the gate width of the fourth p-type MISFET is 19. The MIS type semiconductor device according to claim 18, wherein the MIS type semiconductor device is configured to be smaller than a gate width of the p-type MIS FET.

21. An n-type first MI transistor and a P-type second MIS transistor which are formed on a thin film semiconductor layer on an insulating film and which are completely depleted when an inversion layer of the MIS transistor is formed. Type transistor

One of the source and drain regions of each of the first and second MIS transistors is connected to each other to form an output node, and the gate electrodes are connected to each other to form a control signal input node; and the first and second MIS transistors are connected to each other. An MIS type semiconductor device comprising: a circuit for selecting one of input signals respectively connected to the other one of a source Z drain region of a transistor by the control signal and outputting the selected signal to a first output node, and a combination thereof. .

22. The n-type first and third MIS transistors are formed on the thin film semiconductor layer on the insulating film and are completely depleted when the inversion layer of the MIS transistor is formed. In the transistor and the p-type second and fourth MIS transistors, one of the source and drain regions of the first and second MIS transistors is connected to each other to form a first output node, and the gate electrode is connected to each other. And the other of the source and drain regions of the third and fourth MIS transistors is connected to each other to form the first control signal input node. The gate electrodes of the third and fourth MIS transistors are connected to each other to form a second control signal input node, and the other of the source and drain regions of the third and fourth MIS transistors are connected to each other. One of the input signals respectively connected to one is selected by the second control signal and output to the other of the source Z drain region of the first MIS transistor, and the output signal and the second MIS transistor are output. An MIS type semiconductor device comprising: a circuit for selecting an input signal connected to the other one of a source drain region of a type transistor by a first control signal and outputting the selected signal to a first output node, and a combination thereof.

3. The thin film semiconductor layer is formed on the insulating film, and the thin film semiconductor layer is completely depleted when the inversion layer of the MIS transistor is formed. The n-type first, third, and fifth MIS type transistors and the p-type In the second, fourth and sixth MIS transistors,

The source and drain regions of the first and second MIS transistors are connected to each other to form a first output node, and the gate electrodes are connected to each other to form a first control signal input node. One of the source drain regions of the MIS transistor is connected to each other and connected to the other source drain region of the first MIS transistor, and the gate electrodes of the third and fourth MIS transistors are connected to each other. Connected to each other to form a second control signal input node, and connected to one of the source / drain regions of the fifth and sixth MIS transistors to the other of the source Z drain region of the second MIS transistor. The gate electrodes of the fifth and sixth MIS transistors are connected to each other to form a third control signal input node, and the source and drain of the third and fourth MIS transistors are connected to each other. First other one of the source / drain regions of the MIS-type transistor and more selective to the one input signal connected to the other one of the in-area second control signal The third control signal selects one of the input signals connected to the other one of the source / drain regions of the fifth and sixth MIS transistors, and selects the source of the second MIS transistor. An MIS type semiconductor comprising: a circuit for outputting to the other one of the drain regions, selecting one of the two output signals by a first control signal and outputting the selected signal to a first output node, and a combination thereof. Dress

24. The MIS-type semiconductor device according to claims 21 to 23, wherein an _n- type seventh MIS-type transistor and a p-type eighth MIS-type transistor are added. The gate electrode of the MIS transistor is connected to the first output node, the source region of the seventh MIS transistor is connected to ground, and the source region of the eighth MIS transistor is connected to the power supply. A drain region of the seventh and eighth MIS transistors is connected to each other to form a second output node.

25. The MIS-type semiconductor device according to claim 24, wherein the _n- type ninth MIS-type transistor whose gate width is smaller than the seventh MIS-type transistor and the gate width is smaller than that of the eighth MIS-type transistor. A small p-type tenth MIS transistor is added, the gate electrodes of the ninth and tenth MIS transistors are connected to the second output node, and the source region of the ninth MIS transistor is Connected to the ground, the source region of the tenth MIS transistor was connected to the power supply, and the drain regions of the ninth and tenth MIS transistors were connected to the first output node, respectively. Characteristic MIS type semiconductor device.