JP4527070B2 - Semiconductor device, manufacturing method thereof, and electronic apparatus - Google Patents

Description

  The present invention relates to a semiconductor device in which an active circuit using a thin film transistor (hereinafter referred to as TFT) is provided over a substrate having an insulating surface, and a manufacturing method thereof. In particular, the present invention can be suitably used for an electro-optical device typified by a liquid crystal display device in which an image display region and a drive circuit thereof are provided on the same substrate, and an electronic apparatus equipped with the electro-optical device. Note that the semiconductor device in this specification refers to all devices that function by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electronic apparatus in which the electro-optical device is mounted.

  A TFT in which a semiconductor layer is formed of a crystalline silicon film (hereinafter referred to as a crystalline silicon TFT) has high field effect mobility, and various functional circuits can be formed. In an active matrix liquid crystal display device using crystalline silicon TFTs, an image display region and a drive circuit for performing image display are formed on the same substrate. The image display area is provided with a pixel TFT formed of an n-channel TFT and a storage capacitor, and the drive circuit is composed of a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, etc. that are formed based on a CMOS circuit. ing.

  However, the operating conditions of the pixel TFT and the TFT of the driving circuit are not the same, and therefore, the characteristics required for the TFT are not a little different. For example, the pixel TFT functions as a switch element, and is driven by applying a voltage to the liquid crystal. Since the liquid crystal is driven by alternating current, a method called frame inversion driving is often employed. In this method, in order to keep power consumption low, a characteristic required for the pixel TFT is to sufficiently reduce an off-current value (a drain current that flows when the TFT is turned off). On the other hand, since a high drive voltage is applied to the buffer circuit of the control circuit, it is necessary to increase the withstand voltage so as not to break even when a high voltage is applied. In order to increase the current driving capability, it is necessary to secure a sufficient on-current value (drain current that flows when the TFT is on).

  As a TFT structure for reducing the off-current value, a lightly doped drain (LDD) structure is known. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration, and this region is referred to as an LDD region. I'm calling. A so-called GOLD (Gate-drain Overlapped LDD) structure in which an LDD region is disposed so as to overlap a gate electrode through a gate insulating film is known as a means for preventing deterioration of an on-current value due to hot carriers. . With such a structure, it is known that a high electric field in the vicinity of the drain is relaxed, hot carrier injection is prevented, and the deterioration phenomenon is effective.

  On the other hand, in order to increase the value as a product of an active matrix type liquid crystal display device, there has been a demand for a larger screen and higher definition. However, since the number of scanning lines (gate wirings) is increased and the length thereof is increased due to the increase in size and definition of the screen, it is necessary to lower the resistance of the gate wiring. That is, as the number of scanning lines increases, the charging time for the liquid crystal becomes shorter, and it is necessary to reduce the time constant (resistance × capacitance) of the gate wiring and to respond at high speed. For example, when the specific resistance of the material forming the gate wiring is 100 μΩcm, the screen size is almost limited to the 6-inch class, but when it is 3 μΩcm, it is possible to display up to the 27-inch class.

  However, the required characteristics are not necessarily the same between the pixel TFT of the pixel matrix circuit and the TFT of the control circuit such as a shift register circuit or a buffer circuit. For example, in the pixel TFT, a large reverse bias (a negative voltage in an n-channel TFT) is applied to the gate, but the TFT of the control circuit basically does not operate in a reverse bias state. Further, regarding the operation speed, the pixel TFT may be 1/100 or less of the TFT of the control circuit.

  In addition, the GOLD structure has a high effect of preventing deterioration of the on-current value, but on the other hand, there is a problem that the off-current value becomes larger than that of a normal LDD structure. Therefore, it is not a preferable structure for application to the pixel TFT. Conversely, the normal LDD structure has a high effect of suppressing the off-current value, but has a low effect of relaxing the electric field in the vicinity of the drain and preventing deterioration due to hot carrier injection. Thus, in a semiconductor device having a plurality of integrated circuits with different operating conditions, such as an active matrix liquid crystal display device, it is not always preferable to form all TFTs with the same structure. Such problems have become apparent as the characteristics of crystalline silicon TFTs increase and the performance required for active matrix liquid crystal display devices increases.

  In order to realize an active matrix type liquid crystal display device with a large screen, it is conceivable to use aluminum (Al) or copper (Cu) as a wiring material, but it has a drawback of poor corrosion resistance and heat resistance. Therefore, it is not always preferable to form the gate electrode of the TFT with such a material, and it is not easy to introduce such a material into the TFT manufacturing process. Of course, it is possible to form the wiring with another conductive material, but there is no material as low as aluminum (Al) or copper (Cu), and a display device with a large screen could not be manufactured.

  In order to solve the above problems, the structure of the present invention is a semiconductor device having a pixel TFT provided in a display region and a TFT of a drive circuit provided in the periphery of the display region on the same substrate. The TFT and the TFT of the driving circuit have a gate electrode formed of a first conductive layer, and the gate electrode is in electrical contact with a gate wiring formed of the second conductive layer at a connection portion. The connection portion is provided outside a channel formation region of the pixel TFT and the TFT of the driving circuit.

  According to another aspect of the invention, in a semiconductor device having a pixel TFT provided in a display region and a TFT of a drive circuit provided around the display region on the same substrate, the pixel TFT and the drive circuit The TFT has a gate electrode formed of a first conductive layer, and the gate electrode includes a gate wiring formed of a second conductive layer, a channel included in the pixel TFT and the TFT of the driver circuit. A contact portion provided outside the formation region is in electrical contact, and the LDD region of the pixel TFT is disposed so as not to overlap the gate electrode of the pixel TFT, and the first n-channel TFT of the drive circuit The LDD region of the first n-channel TFT is disposed so as to overlap the gate electrode of the first n-channel TFT, and the LDD region of the second n-channel TFT of the driving circuit is the gate of the first n-channel TFT. It is characterized in that at least part of which is arranged so as to overlap with the electrode.

  In the structure of the present invention, the first conductive layer is formed on the conductive layer (A) including a conductive layer (A) containing at least one selected from tantalum, tungsten, titanium, and molybdenum and nitrogen. A conductive layer (B) containing at least one selected from tantalum, tungsten, titanium, and molybdenum as a main component, and a region where the conductive layer (B) is not in contact with the conductive layer (A). A conductive layer (C) containing nitrogen and at least one selected from tungsten, titanium, and molybdenum, and the second conductive layer is a conductive layer (D) containing at least aluminum or copper as a main component. ) And a conductive layer (E) whose main component is at least one selected from tantalum, tungsten, titanium, and molybdenum, and the conductive layer (C) and the conductive layer (D) are in contact with each other at the connection portion. Have It is characterized in that. The conductive layer (B) preferably contains argon as an additive element, and the oxygen concentration in the conductive layer (B) is preferably 30 ppm or less.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes a semiconductor device having a pixel TFT provided in a display region and a TFT of a drive circuit provided in the periphery of the display region on the same substrate. In the manufacturing method, a step of forming a gate electrode of the pixel TFT and a TFT of the driver circuit with a first conductive layer, and a step of forming a gate wiring connected to the gate electrode with a second conductive layer The gate electrode and the gate wiring are connected by a connection portion provided outside a channel formation region of the pixel TFT and the TFT of the driving circuit.

In addition, according to the method for manufacturing a semiconductor device of the present invention, in the semiconductor device having the pixel TFT provided in the display region and the TFT of the drive circuit provided in the periphery of the display region on the same substrate, the drive circuit is formed. First step of selectively adding an impurity element imparting n-type to a semiconductor layer of the first and second n-channel TFTs to be applied in a concentration range of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ And a second step of forming a gate electrode of the pixel TFT and the TFT of the driving circuit with a first conductive layer, and a semiconductor layer of a p-channel TFT forming the driving circuit with 3 × 10 ²⁰ to A third step of selectively adding an impurity element imparting p-type in a concentration range of 3 × 10 ²¹ atoms / cm ³ ; and semiconductor layers of first and second n-channel TFTs forming the drive circuit And 1 × 1 to the semiconductor layer of the pixel TFT A fourth step of selectively adding an impurity element imparting n-type conductivity in a concentration range of ^{20 ~1 × 10 21 atoms / cm} 3, the semiconductor layer of the pixel TFT, the gate electrode as a mask, 1 × 10 ^A fifth step of selectively adding an impurity element imparting n-type in a concentration range of ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ ; and a gate wiring between the pixel TFT and the TFT of the driver circuit is formed in the second step. A sixth step of forming with a conductive layer, wherein the gate electrode and the gate wiring are connected by a connection portion provided outside a channel formation region of the pixel TFT and the TFT of the driving circuit. It is characterized by.

  In the method for manufacturing a semiconductor device of the present invention, the first conductive layer includes a step of forming a conductive layer (A) containing at least one selected from tantalum, tungsten, titanium, and molybdenum and nitrogen, Forming a conductive layer (B) formed on the conductive layer (A) and containing as a main component at least one selected from tantalum, tungsten, titanium, and molybdenum; and the conductive layer (B) is formed of the conductive layer (B). A) formed in a region not in contact with A) and forming a conductive layer (C) containing at least one selected from tantalum, tungsten, titanium, and molybdenum and nitrogen, and the second conductive layer includes: A step of forming a conductive layer (D) containing at least aluminum or copper as a main component and at least one selected from tantalum, tungsten, titanium, and molybdenum as a main component; It is formed and a step of forming a conductive layer (E), a conductive layer (C) and the conductive layer by the connecting portion (D) is characterized in that it connects. The conductive layer (A) can be formed by sputtering using a target mainly composed of at least one selected from tantalum, tungsten, titanium, and molybdenum in a mixed atmosphere of argon and nitrogen or ammonia. The conductive layer (C) is preferably formed by heat-treating the conductive layer (B) in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less. The conductive layer (C) may be formed by heat-treating the conductive layer (B) in a nitrogen plasma atmosphere having an oxygen concentration of 1 ppm or less.

By using the present invention, in a semiconductor device (specifically, an electro-optical device here) in which a plurality of functional circuits are formed on the same substrate, a TFT having appropriate performance according to the specifications required by the functional circuits Can be arranged, and its operating characteristics and reliability can be greatly improved. In particular, by forming the LDD region of the n-channel TFT of the pixel matrix circuit with n ⁻ concentration and only Loff, the off-current value can be greatly reduced, contributing to lower power consumption of the pixel matrix circuit. Can do. In addition, by forming the LDD region of the n-channel TFT of the control circuit with an n ⁻ concentration and only Lov, the current driving capability is increased, deterioration due to hot carriers is prevented, and deterioration of the on-current value is reduced. be able to. In addition, the operation performance and reliability of a semiconductor device (specifically, an electronic device here) having such an electro-optical device as a display medium can be improved.

  Further, the gate electrode of the pixel TFT and the TFT of the driving circuit is formed of a conductive material having high heat resistance, and the gate wiring connected to the gate electrode is formed of a low resistance material such as aluminum (Al). Good TFT characteristics can be realized, and a large-screen display device of 4 inches class or more can be realized using such TFT.

Embodiment 1 An embodiment of the present invention will be described with reference to FIGS. Here, a method for manufacturing a pixel TFT in the display area and a TFT in a driver circuit provided around the display area on the same substrate will be described in detail according to the process. However, in order to simplify the description, a CMOS circuit that is a basic circuit such as a shift register circuit and a buffer circuit is shown in the control circuit, and an n-channel TFT that forms a sampling circuit.

In FIG. 1A, a low alkali glass substrate or a quartz substrate can be used for the substrate 101. In this example, a low alkali glass substrate was used. In this case, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. A base film 102 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 101 on which the TFT is formed in order to prevent impurity diffusion from the substrate 101. For example, a silicon oxynitride film made of SiH ₄ , NH ₃ , and N ₂ O by plasma CVD is formed to a thickness of 100 nm, and a silicon oxynitride film made of SiH ₄ and N ₂ O is laminated to a thickness of 200 nm. To do.

  Next, a semiconductor film 103a having an amorphous structure with a thickness of 20 to 150 nm (preferably 30 to 80 nm) is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film having a thickness of 55 nm is formed by plasma CVD. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. Further, since the base film 102 and the amorphous silicon film 103a can be formed by the same film formation method, they may be formed continuously. After the formation of the base film, it is possible to prevent contamination of the surface by not exposing it to the air atmosphere, and it is possible to reduce variations in characteristics of TFTs to be manufactured and variations in threshold voltage. (Fig. 1 (A))

  Then, a crystalline silicon film 103b is formed from the amorphous silicon film 103a using a known crystallization technique. For example, a laser crystallization method or a thermal crystallization method (solid phase growth method) may be applied. Here, in accordance with the technique disclosed in Japanese Patent Laid-Open No. 7-130552, the crystallization method using a catalytic element is used for crystallization. A quality silicon film 103b was formed. Prior to the crystallization step, depending on the amount of hydrogen contained in the amorphous silicon film, heat treatment is performed at 400 to 500 ° C. for about 1 hour, and the amount of hydrogen contained is reduced to 5 atom% or less for crystallization. desirable. When the amorphous silicon film is crystallized, the rearrangement of atoms occurs and the film is densified. Therefore, the thickness of the produced crystalline silicon film is larger than the thickness of the initial amorphous silicon film (55 nm in this embodiment). Also decreased by about 1 to 15%. (Fig. 1 (B))

  Then, the crystalline silicon film 103b is divided into island shapes, so that island-like semiconductor layers 104 to 107 are formed. Thereafter, a mask layer 108 made of a silicon oxide film having a thickness of 50 to 100 nm is formed by plasma CVD or sputtering. (Figure 1 (C))

Then, a resist mask 109 is provided, and p has a concentration of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ for the purpose of controlling the threshold voltage over the entire surface of the island-like semiconductor layers 105 to 107 forming the n-channel TFT. Boron (B) was added as an impurity element imparting a mold. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of an amorphous silicon film. Although boron (B) is not necessarily added here, the semiconductor layers 110 to 112 to which boron (B) is added are preferably formed in order to keep the threshold voltage of the n-channel TFT within a predetermined range. It was good. (Figure 1 (D))

In order to form the LDD region of the n-channel TFT of the driver circuit, an impurity element imparting n-type conductivity is selectively added to the island-like semiconductor layers 110 and 111. Therefore, resist masks 113 to 116 are formed in advance. As an impurity element imparting n-type conductivity, phosphorus (P) or arsenic (As) may be used. Here, an ion doping method using phosphine (PH ₃ ) is applied to add phosphorus (P). The phosphorus (P) concentration of the formed impurity regions 117 and 118 may be in the range of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ . In this specification, the concentration of an impurity element imparting n-type contained in the impurity regions 117 to 119 formed here is represented as (n ⁻ ). The impurity region 119 is a semiconductor layer for forming a storage capacitor of the pixel matrix circuit, and phosphorus (P) is added to this region at the same concentration. (Fig. 2 (A))

Next, the mask layer 108 is removed with hydrofluoric acid or the like, and a step of activating the impurity element added in FIGS. 1D and 2A is performed. The activation can be performed by a heat treatment at 500 to 600 ° C. for 1 to 4 hours or a laser activation method in a nitrogen atmosphere. Moreover, you may carry out using both together. In this embodiment, a laser activation method is used, a KrF excimer laser beam (wavelength 248 nm) is used to form a linear beam, and an oscillation frequency of 5 to 50 Hz and an energy density of 100 to 500 mJ / cm ² are used. The entire surface of the substrate on which the island-shaped semiconductor layer was formed was processed by scanning with an overlap ratio of 80 to 98%. Note that there are no particular limitations on the irradiation conditions of the laser beam, and the practitioner may make an appropriate decision.

  Then, the gate insulating film 120 is formed of an insulating film containing silicon with a thickness of 10 to 150 nm by using a plasma CVD method or a sputtering method. For example, a silicon oxynitride film is formed with a thickness of 120 nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure. (Fig. 2 (B))

  Next, a first conductive layer is formed to form a gate electrode. The first conductive layer may be formed as a single layer, but may have a laminated structure such as two layers or three layers as necessary. In this example, a conductive layer (A) 121 made of a conductive nitride metal film and a conductive layer (B) 122 made of a metal film were laminated. The conductive layer (B) 122 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, or an alloy film combining the elements. (Typically, a Mo—W alloy film or a Mo—Ta alloy film) may be used, and the conductive layer (A) 121 may be a tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, or nitride. It is made of molybdenum (MoN). Alternatively, tungsten silicide, titanium silicide, or molybdenum silicide may be applied to the conductive layer (A) 121 as an alternative material. In the conductive layer (B), the concentration of impurities contained in the conductive layer (B) should be reduced in order to reduce the resistance. In particular, the oxygen concentration should be 30 ppm or less. For example, tungsten (W) was able to realize a specific resistance value of 20 μΩcm or less by setting the oxygen concentration to 30 ppm or less.

  The conductive layer (A) 121 may be 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 122 may be 200 to 400 nm (preferably 250 to 350 nm). In this embodiment, a 30 nm thick tantalum nitride film is used for the conductive layer (A) 121 and a 350 nm Ta film is used for the conductive layer (B) 122, both of which are formed by sputtering. In film formation by this sputtering method, if an appropriate amount of Xe or Kr is added to the sputtering gas Ar, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 121. This improves adhesion and prevents oxidation of the conductive film formed thereon, and at the same time, an alkali metal element contained in a trace amount in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 120. Can be prevented. (Fig. 2 (C))

  Next, resist masks 123 to 127 are formed, and the conductive layer (A) 121 and the conductive layer (B) 122 are etched together to form the gate electrodes 128 to 131 and the capacitor wiring 132. The gate electrodes 128 to 131 and the capacitor wiring 132 are integrally formed of 128a to 132a made of a conductive layer (A) and 128b to 132b made of a conductive layer (B). At this time, the gate electrodes 129 and 130 formed in the driver circuit are formed so as to overlap part of the impurity regions 117 and 118 with the gate insulating film 120 interposed therebetween. (Fig. 2 (D))

Next, in order to form a source region and a drain region of the p-channel TFT of the driver circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity region is formed in a self-aligning manner using the gate electrode 128 as a mask. At this time, a region where the n-channel TFT is formed is covered with a resist mask 133. Then, an impurity region 134 was formed by an ion doping method using diborane (B ₂ H ₆ ). The boron (B) concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 134 formed here is expressed as (p ⁺ ). (Fig. 3 (A))

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 135 to 137 were formed, and an impurity element imparting n-type conductivity was added to form impurity regions 138 to 142. This was performed by ion doping using phosphine (PH ₃ ), and the phosphorus (P) concentration in this region was set to 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 138 to 142 formed here is expressed as (n ⁺ ). (Fig. 3 (B))

  The impurity regions 138 to 142 already contain phosphorus (P) or boron (B) added in the previous step, but phosphorus (P) is added at a sufficiently high concentration, so that The influence of phosphorus (P) or boron (B) added in the previous step may not be considered. Further, since the phosphorus (P) concentration added to the impurity region 138 is 1/2 to 1/3 of the boron (B) concentration added in FIG. 3A, p-type conductivity is ensured, and TFT characteristics are obtained. It had no effect on.

Then, an impurity adding step for imparting n-type for forming the LDD region of the n-channel TFT of the pixel matrix circuit was performed. Here, an impurity element imparting n-type in a self-aligning manner is added by ion doping using the gate electrode 131 as a mask. The concentration of phosphorus (P) to be added is 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^3, which is based on the concentration of the impurity element added in FIGS. 2 (A), 3 (A), and 3 (B). In addition, by adding at a low concentration, substantially only the impurity regions 143 and 144 are formed. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 143 and 144 is represented by (n ⁻ ). (Figure 3 (C))

  Thereafter, a heat treatment process is performed to activate the impurity element imparting n-type or p-type added at each concentration. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation process was performed by furnace annealing. The heat treatment is performed at 400 to 800 ° C., typically 500 to 600 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, heat treatment is performed at 550 ° C. for 4 hours. went. Further, in the case where a substrate 101 having heat resistance such as a quartz substrate is used, heat treatment may be performed at 800 ° C. for 1 hour, and activation of the impurity element, impurity region to which the impurity element is added, and A good junction with the channel formation region could be formed.

  In this heat treatment, the conductive layers (C) 128c to 132c are formed with a thickness of 5 to 80 nm from the surface of the metal films 128b to 132b forming the gate electrodes 128 to 131 and the capacitor wiring 132. For example, when the conductive layers (B) 128b to 132b are tungsten (W), tungsten nitride (WN) can be formed, and when tantalum (Ta) is used, tantalum nitride (TaN) can be formed. The conductive layers (C) 128c to 132c can be formed in the same manner even when the gate electrodes 128 to 131 are exposed to a plasma atmosphere containing nitrogen using nitrogen or ammonia. Further, a heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

In the case where the island-shaped semiconductor layer was formed from an amorphous silicon film by a crystallization method using a catalytic element, a trace amount of the catalytic element remained in the island-shaped semiconductor layer. Of course, it is possible to complete the TFT even in such a state, but it is more preferable to remove at least the remaining catalyst element from the channel formation region. As one of means for removing the catalyst element, there is a means for utilizing the gettering action by phosphorus (P). The concentration of phosphorus (P) necessary for gettering is approximately the same as that of the impurity region (n ⁺ ) formed in FIG. 3B, and the n-channel TFT and the p-type are formed by heat treatment in the activation process performed here. The catalytic element could be gettered from the channel formation region of the channel TFT. (Fig. 3 (D))

  6A and 7A are top views of the TFT in the steps up to here, and the AA ′ cross section and the CC ′ cross section are AA ′ and CC in FIG. It corresponds to '. Further, the BB ′ cross section and the DD ′ cross section correspond to the cross sectional views of FIGS. 8A and 9A. Although the gate insulating film is omitted in the top views of FIGS. 6 and 7, the gate electrodes 128 to 131 and the capacitor wiring 132 are formed on the island-like semiconductor layers 104 to 107 as shown in the drawings by the steps up to here. Has been.

  After the activation and hydrogenation steps are completed, a second conductive film is formed as a gate wiring. The second conductive film includes a conductive layer (D) mainly composed of aluminum (Al) or copper (Cu), which is a low resistance material, titanium (Ti), tantalum (Ta), tungsten (W), molybdenum ( It is good to form with the conductive layer (E) which consists of Mo). In this embodiment, an aluminum (Al) film containing 0.1 to 2% by weight of titanium (Ti) is formed as the conductive layer (D) 145, and a titanium (Ti) film is formed as the conductive layer (E) 146. The conductive layer (D) 145 may be 200 to 400 nm (preferably 250 to 350 nm), and the conductive layer (E) 146 may be 50 to 200 (preferably 100 to 150 nm). (Fig. 4 (A))

Then, the conductive layers (E) 146 and (D) 145 were etched to form gate wirings connected to the gate electrodes, so that gate wirings 147 and 148 and capacitor wirings 149 were formed. The etching process is performed first by removing from the surface of the conductive layer (E) to the middle of the conductive layer (D) by a dry etching method using a mixed gas of SiCl ₄ , Cl ₂ and BCl _3, and then a phosphoric acid-based etching solution By removing the conductive layer (D) by wet etching, the gate wiring can be formed while maintaining selective processability with the base.

6B and 7B are top views of this state, and the AA ′ and CC ′ sections correspond to AA ′ and CC ′ in FIG. 4B. ing. Further, the BB ′ section and the DD ′ section correspond to BB ′ and DD ′ in FIGS. 8B and 9B. 6B and 7B, part of the gate wirings 147 and 148 overlaps with part of the gate electrodes 128, 129, and 131 and is in electrical contact. This state is also apparent from the cross-sectional structure diagrams of FIGS. 8B and 9B corresponding to the BB ′ cross section and the DD ′ cross section, and the conductive layer (C) forming the first conductive layer. And the conductive layer (D) forming the second conductive layer are in electrical contact.

  The first interlayer insulating film 150 is formed of a silicon oxide film or a silicon oxynitride film with a thickness of 500 to 1500 nm, and then a contact hole reaching the source region or the drain region formed in each island-like semiconductor layer is formed. Then, source wirings 151 to 154 and drain wirings 155 to 158 are formed. Although not shown, in this embodiment, this electrode is a laminated film having a three-layer structure in which a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film is 150 nm continuously formed by sputtering.

  Next, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed as the passivation film 159 with a thickness of 50 to 500 nm (typically 100 to 300 nm). When the hydrogenation treatment was performed in this state, favorable results were obtained with respect to the improvement of TFT characteristics. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect can be obtained by using a plasma hydrogenation method. Note that an opening may be formed in the passivation film 159 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later. (Fig. 4 (C))

6C and 7C are top views of this state, and the AA ′ and CC ′ sections correspond to AA ′ and CC ′ in FIG. 4C. is doing. The BB ′ cross section and the DD ′ cross section correspond to BB ′ and DD ′ in FIGS. 8C and 9C. In FIG. 6C and FIG. 7C, the first interlayer insulating film is omitted, but source wirings 151, 152, and the like are not illustrated in the source and drain regions of the island-shaped semiconductor layers 104, 105, and 107. 154 and drain wirings 155, 156, 158 are connected through a contact hole formed in the first interlayer insulating film.

  Thereafter, a second interlayer insulating film 160 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Here, it was formed by baking at 300 ° C. using a type of polyimide that is thermally polymerized after being applied to the substrate. Then, a contact hole reaching the drain wiring 158 is formed in the second interlayer insulating film 160, and pixel electrodes 161 and 162 are formed. The pixel electrode may be a transparent conductive film in the case of a transmissive liquid crystal display device, and may be a metal film in the case of a reflective liquid crystal display device. In this embodiment, an indium tin oxide (ITO) film having a thickness of 100 nm is formed by sputtering to form a transmissive liquid crystal display device. (Fig. 5)

  In this way, a substrate having the TFTs of the driving circuit and the pixel TFTs of the display area on the same substrate could be completed. A p-channel TFT 201, a first n-channel TFT 202, and a second n-channel TFT 203 are formed in the driver circuit, and a pixel TFT 204 and a storage capacitor 205 are formed in the display region. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

  The p-channel TFT 201 of the driver circuit includes a channel formation region 206, source regions 207a and 207b, and drain regions 208a and 208b in the island-like semiconductor layer 104. The first n-channel TFT 202 includes an LDD region 210 that overlaps the island-shaped semiconductor layer 105 with a channel formation region 209 and a gate electrode 129 (hereinafter, such an LDD region is referred to as Lov), a source region 211, and a drain region 212. have. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. The second n-channel TFT 203 includes a channel formation region 213, LDD regions 214 and 215, a source region 216, and a drain region 217 in the island-shaped semiconductor layer 106. This LDD region is formed with an LDD region that does not overlap the Lov region and the gate electrode 130 (hereinafter, such an LDD region is referred to as Loff), and the length of the Loff region in the channel length direction is 0.3-2. It is 0 μm, preferably 0.5 to 1.5 μm. The pixel TFT 204 includes channel formation regions 218 and 219, Loff regions 220 to 223, and source or drain regions 224 to 226 in the island-shaped semiconductor layer 107. The length of the Loff region in the channel length direction is 0.5 to 3.0 μm, preferably 1.5 to 2.5 μm. Further, the storage capacitor 205 includes capacitor wirings 132 and 149, an insulating film made of the same material as the gate insulating film, and a semiconductor layer 227 connected to the drain region 226 of the pixel TFT 204 and doped with an impurity element imparting n-type conductivity. Is formed. Although the pixel TFT 204 has a double gate structure in FIG. 5, it may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

  As described above, the present invention can optimize the structure of TFTs constituting each circuit in accordance with specifications required by the pixel TFT and the drive circuit, and can improve the operation performance and reliability of the semiconductor device. it can. Furthermore, the LDD region, the source region, and the drain region can be easily activated by forming the gate electrode from a heat-resistant conductive material, and the wiring resistance can be sufficiently reduced by forming the gate electrode from a low-resistance material. Therefore, the present invention can be applied to a display device having a display area (screen size) of 4 inches class or more.

Embodiment 2 FIG. 16 is a diagram showing another embodiment of a gate electrode and a gate wiring. The gate electrode and the gate wiring in FIG. 16 are formed in the same manner as in the process described in Embodiment 1, and are formed above the island-shaped semiconductor layer 901 and the gate insulating film 902.

  In FIG. 16A, a conductive layer (A) 903 includes a tantalum nitride (TaN), a tungsten nitride (WN), a titanium nitride (TiN) film, and a molybdenum nitride (MoN). Form with. The conductive layer (B) 904 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, or an alloy film in which the elements are combined. The conductive layer (C) 905 is formed on the surface in the same manner as in the first embodiment. The conductive layer (A) 903 may be 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 904 may be 200 to 400 nm (preferably 250 to 350 nm). The second conductive layer used as the gate wiring is composed of a conductive layer (D) whose main component is aluminum (Al) or copper (Cu), which is a low resistance material, and titanium (Ti), tantalum (Ta) or the like on the conductive layer (D). A conductive layer (E) to be formed is stacked. Since aluminum (Al) and copper (Cu) are easily diffused by stress migration or electromigration, it is necessary to form the silicon nitride film 908 with a thickness of 50 to 150 nm so as to cover the second conductive layer. is there.

  FIG. 16B shows a gate electrode and a gate wiring manufactured in the same manner as in Embodiment Mode 1. A silicon film 909 doped with phosphorus (P) is formed under the gate electrode. The silicon film 909 doped with phosphorus (P) has an effect of preventing a trace amount of alkali metal element contained in the gate electrode from diffusing into the gate insulating film, and is useful for the purpose of ensuring the reliability of the TFT.

  FIG. 16C illustrates an example in which the first conductive layer for forming the gate electrode is formed using a silicon film 910 doped with phosphorus (P). The silicon film doped with phosphorus (P) is a high-resistance material as compared with other conductive metal materials, but the second conductive layer for forming the gate wiring is formed of aluminum (Al) or copper (Cu). Thus, the present invention can be applied to a large-area liquid crystal display device. Here, the gate wiring has a three-layer structure in which a Ti film 911 is formed with a thickness of 100 nm, an aluminum (Al) film 912 containing Ti is formed with a thickness of 300 nm, and a Ti film 913 is formed with a thickness of 150 nm. Heat resistance can be provided by preventing direct contact with the silicon film.

Embodiment 3 FIG. 15 is a diagram for explaining the structure of a TFT according to the present invention, in which a channel formation region of a semiconductor layer, an LDD region, a gate insulating film on the semiconductor layer, and a gate on the gate insulating film. In the TFT having electrodes, the positional relationship between the gate electrode and the LDD region is described.

  FIG. 15A shows a structure in which a semiconductor layer including a channel formation region 209, an LDD region 210, and a drain region 212, and a gate insulating film 120 and a gate electrode 129 thereover are provided. The LDD region 210 is Lov provided so as to overlap the gate electrode 129 with the gate insulating film 120 interposed therebetween. Lov has a function of relaxing a high electric field generated near the drain, can prevent deterioration due to hot carriers, and is suitable for use in an n-channel TFT such as a shift register circuit, a level shifter circuit, and a buffer circuit of a control circuit. Yes.

  FIG. 15B shows a structure in which a semiconductor layer including a channel formation region 213, LDD regions 215a and 215b, and a drain region 217, and a gate insulating film 120 and a gate electrode 130 are provided over the semiconductor layer. The LDD region 215a is provided so as to overlap the gate electrode 130 with the gate insulating film 120 interposed therebetween. The LDD region 215b is Loff provided so as not to overlap the gate electrode 130. Loff has an effect of reducing the off-current value. By adopting a configuration in which Lov and Loff are provided, the off-current value can be reduced while preventing deterioration due to hot carriers, and the n of the sampling circuit of the control circuit can be reduced. Suitable for channel type TFT.

  In FIG. 15C, a channel formation region 219, an LDD region 223, and a drain region 226 are provided in the semiconductor layer. The LDD region 223 is Loff provided so as not to overlap with the gate electrode 131, can effectively reduce the off-current value, and is suitable for use in the pixel TFT. The concentration of the impurity element imparting n-type in the LDD region 223 of the pixel TFT is desirably 1/2 to 1/10 than the concentration of the LDD regions 210 and 215 of the driver circuit.

[Embodiment 4] In this embodiment, a process for manufacturing an active matrix liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 11, an alignment film 601 is formed on the active matrix substrate in the state shown in FIG. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. A light shielding film 603, a transparent conductive film 604, and an alignment film 605 were formed on the counter substrate 602 on the counter side. After the alignment film was formed, rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. Then, the pixel matrix circuit, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are bonded to each other through a sealing material, a spacer (both not shown), or the like by a known cell assembling process. Thereafter, a liquid crystal material 606 was injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix liquid crystal display device shown in FIG. 11 was completed.

  Next, the structure of the active matrix liquid crystal display device will be described with reference to the perspective view of FIG. 12 and the top view of FIG. 12 and 13 use the same reference numerals in order to correspond to the cross-sectional structure diagrams of FIGS. 1 to 5 and FIG. Further, the cross-sectional structure along E-E ′ shown in FIG. 13 corresponds to the cross-sectional view of the pixel matrix circuit shown in FIG. 5.

  In FIG. 12, the active matrix substrate includes a display region 306, a scanning signal driving circuit 304, and an image signal driving circuit 305 formed on the glass substrate 101. A pixel TFT 204 is provided in the display area, and a driving circuit provided in the periphery is configured based on a CMOS circuit. The scanning signal driving circuit 304 and the image signal driving circuit 305 are connected to the pixel TFT 204 by a gate wiring 148 and a source wiring 154, respectively. Further, the FPC 731 is connected to the external input / output terminal 734 and is connected to the respective drive circuits by the input wirings 302 and 303.

FIG. 13 is a top view showing almost one pixel in the display area 306. The gate wiring 148 intersects the semiconductor layer 107 thereunder via a gate insulating film (not shown). Although not shown, in the semiconductor layer, a source region, a drain region, and an Loff region composed of an n ⁻ region are formed. Reference numeral 163 denotes a contact portion between the source wiring 154 and the source region 224, 164 denotes a contact portion between the drain wiring 158 and the drain region 226, and 165 denotes a contact portion between the drain wiring 158 and the pixel electrode 161. The storage capacitor 205 is formed in a region where the capacitor wirings 132 and 149 overlap with the semiconductor layer 227 extending from the drain region 226 of the pixel TFT 204 and the gate insulating film.

  Note that the active matrix liquid crystal display device of this example has been described with reference to the structure described in Embodiment 1, but an active matrix liquid crystal display device can be manufactured by freely combining with the structure of Embodiment 2. it can.

Embodiment 5 FIG. 10 is a diagram showing an example of the arrangement of input / output terminals, a display area, and a drive circuit of a liquid crystal display device. In the display region 306, m gate lines and n source lines intersect in a matrix. For example, when the pixel density is VGA, 480 gate wirings and 640 source wirings are formed, and in the case of XGA, 768 gate wirings and 1024 source wirings are formed. The screen size of the display area is 340 mm for the 13-inch class and 460 mm for the 18-inch class. In order to realize such a liquid crystal display device, the gate wiring needs to be formed of a low resistance material as shown in the first and second embodiments.

  Around the display area 306, a scanning signal driving circuit 304 and an image signal driving circuit 305 are provided. Since the lengths of the gate wirings of these drive circuits are inevitably longer as the screen size of the display area is increased, a low resistance material as shown in the first and second embodiments is used to realize a large screen. It is preferable to form.

  Further, according to the present invention, the input wirings 302 and 303 that connect the input terminal 301 to each driving circuit can be formed of the same material as the gate wiring, which can contribute to a reduction in wiring resistance.

Embodiment 6 FIG. 14 is an example of a circuit configuration of an active matrix substrate shown in Embodiment 1 or 2, and is a diagram illustrating a circuit configuration of a direct-view display device. The active matrix substrate of this embodiment includes an image signal driving circuit 1001, a scanning signal driving circuit (A) 1007, a scanning signal driving circuit (B) 1011, a precharge circuit 1012, and a display area 1006. Note that the driving circuit described in this specification is a generic name including the image signal driving circuit 1001 and the scanning signal driving circuit (A) 1007.

  The image signal driving circuit 1001 includes a shift register circuit 1002, a level shifter circuit 1003, a buffer circuit 1004, and a sampling circuit 1005. The scanning signal driver circuit (A) 1007 includes a shift register circuit 1008, a level shifter circuit 1009, and a buffer circuit 1010. The scanning signal driving circuit (B) 1011 has the same configuration.

  The shift register circuits 1002 and 1008 have a driving voltage of 5 to 16 V (typically 10 V), and the structure indicated by 202 in FIG. 5 is suitable for the n-channel TFT of the CMOS circuit forming this circuit. Further, the level shifter circuits 1003 and 1009 and the buffer circuits 1004 and 1010 have a drive voltage as high as 14 to 16 V, but a CMOS circuit including the n-channel TFT 202 in FIG. 5 is suitable as in the shift register circuit. In these circuits, when the gate is formed with a multi-gate structure, the breakdown voltage is increased, which is effective in improving the reliability of the circuit.

  Although the sampling circuit 1005 has a driving voltage of 14 to 16 V, it is driven by alternately inverting the polarity, and it is necessary to reduce the off-current value. Therefore, a CMOS circuit including the n-channel TFT 203 in FIG. 5 is suitable. ing. In FIG. 5, only an n-channel TFT is displayed, but in an actual sampling circuit, a p-channel TFT is also formed in combination. At this time, the structure indicated by 201 in FIG.

  The pixel TFT 204 has a driving voltage of 14 to 16 V, and it is required to further reduce the off-current value from the viewpoint of reducing power consumption, so that it does not overlap with the gate electrode like the pixel TFT 204. It is desirable to have a structure having an LDD (Loff) region provided in the substrate.

  Note that the configuration of this embodiment can be easily realized by manufacturing a TFT according to the steps shown in Embodiment 1. In the present embodiment, only the configuration of the display area and the drive circuit is shown. However, according to the steps of the first embodiment, in addition to the above, a signal dividing circuit, a frequency divider circuit, a D / A converter, a γ correction circuit, an operational amplifier circuit Further, a signal processing circuit such as a memory circuit or an arithmetic processing circuit, or a logic circuit can be formed on the same substrate. As described above, the present invention can realize a semiconductor device including a display region and a driver circuit thereof on the same substrate, for example, a semiconductor device including a signal driver circuit and a display region.

[Embodiment 7] An active matrix substrate and a liquid crystal display device manufactured by implementing the present invention can be used for various electro-optical devices. The present invention can be applied to all electronic devices in which such an electro-optical device is incorporated as a display medium. Examples of electronic devices include personal computers, digital cameras, video cameras, portable information terminals (mobile computers, mobile phones, electronic books, etc.), navigation systems, and the like. An example of them is shown in FIG.

  FIG. 17A illustrates a personal computer which includes a main body 2001 including a microprocessor and a memory, an image input portion 2002, a display device 2003, and a keyboard 2004. The present invention can form the display device 2003 and other signal processing circuits.

  FIG. 17B shows a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102 and other signal control circuits.

  FIG. 17C illustrates a portable information terminal which includes a main body 2201, an image input portion 2202, an image receiving portion 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.

  FIG. 17D shows a player that uses a recording medium (hereinafter referred to as a recording medium) in which a program is recorded, and includes a main body 2401, a display device 2402, a speaker unit 2403, a recording medium 2404, and operation switches 2405. A recording medium such as a DVD (Digital Versatile Disc) or a compact disc (CD) can be used to play music programs, display images, display video games (or video games), and display information via the Internet. . The present invention can be suitably used for the display device 2402 and other signal control circuits.

  FIG. 17E illustrates a digital camera which includes a main body 2501, a display device 2502, an eyepiece unit 2503, an operation switch 2504, and an image receiving unit (not shown). The present invention can be applied to the display device 2502 and other signal control circuits.

  Thus, the applicable range of the present invention is extremely wide and can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using any combination of the first to sixth embodiments.

[Embodiment 8] In this embodiment, a self-luminous display panel (hereinafter referred to as an EL display device) using an electroluminescence (EL) material is manufactured using the same active matrix substrate as that in Embodiment 1. An example will be described. FIG. 18A shows a top view of the EL display panel. In FIG. 18A, reference numeral 10 denotes a substrate, 11 denotes a pixel portion, 12 denotes a source side driver circuit, 13 denotes a gate side driver circuit, and each driver circuit reaches the FPC 17 via wirings 14 to 16 to the external device. Connected.

  A cross-sectional view corresponding to the line AA ′ in FIG. 18A is shown in FIG. At this time, the counter plate 80 is provided at least above the pixel portion, preferably above the driver circuit and the pixel portion. The counter plate 80 is bonded to an active matrix substrate on which a self-luminous layer using a TFT and an EL material is formed with a sealing material 19. A filler (not shown) is mixed in the sealing agent 19, and the two substrates are bonded to each other with a substantially uniform interval. Further, the outside of the sealing material 19 and the upper surface and the periphery of the FPC 17 are sealed with a sealant 81. The sealant 81 is made of a material such as silicone resin, epoxy resin, phenol resin, or butyl rubber.

  Thus, when the active matrix substrate 10 and the counter substrate 80 are bonded together by the sealant 19, a space is formed between them. The space is filled with a filler 83. This filler 83 also has the effect of bonding the opposing plate 80. As the filler 83, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), EVA (ethylene vinyl acetate), or the like can be used. In addition, since the self-luminous layer is weak and easily deteriorated due to moisture including moisture, it is desirable to mix a desiccant such as barium oxide in the filler 83 because the moisture absorption effect can be maintained. In addition, a passivation film 82 formed of a silicon nitride film, a silicon oxynitride film, or the like is formed over the self-light-emitting layer so that corrosion due to an alkali element or the like contained in the filler 83 is prevented.

  The counter plate 80 includes a glass plate, an aluminum plate, a stainless steel plate, a FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a Mylar film (trade name of DuPont), a polyester film, an acrylic film, an acrylic plate, etc. Can be used. Moreover, moisture resistance can also be improved using the sheet | seat of the structure which pinched | interposed several tens micrometer aluminum foil with the PVF film or the mylar film. In this way, the EL element is hermetically sealed from the outside air.

  In FIG. 18B, a driving circuit TFT (however, a CMOS circuit in which an n-channel TFT and a p-channel TFT are combined is illustrated) 22 and a pixel on the substrate 10 and the base film 21 are illustrated. The part TFT 23 (however, only the TFT for controlling the current to the EL element is shown here) is formed. Among these TFTs, in particular, n-channel TFTs are provided with an LDD region having the structure shown in this embodiment in order to prevent a decrease in on-current due to the hot carrier effect and a decrease in characteristics due to Vth shift and bias stress. .

  For example, the p-channel TFT 201 and the n-channel TFT 202 shown in FIG. Further, depending on the driving voltage, the TFT in the pixel portion may be the first n-channel TFT 204 shown in FIG. 5 or a p-channel TFT having the same structure as shown in FIG. The first n-channel TFT 202 has a structure in which an LDD that overlaps the gate electrode is provided on the drain side. However, if the drive voltage is 10 V or less, the TFT degradation due to the hot carrier effect can be almost ignored. There is no need to provide it.

  In order to manufacture an EL display device from the active matrix substrate in the state of FIG. 1, an interlayer insulating film (planarization film) 26 made of a resin material is formed on the source wiring and drain wiring, and the pixel portion TFT 23 is formed thereon. A pixel electrode 27 made of a transparent conductive film electrically connected to the drain is formed. A compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used for the transparent conductive film. Then, after the pixel electrode 27 is formed, an insulating film 28 is formed, and an opening is formed on the pixel electrode 27.

  Next, the self-luminous layer 29 is formed. The self-light emitting layer 29 may have a laminated structure or a single layer structure by freely combining known EL materials (a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer). A known technique may be used to determine the structure. EL materials include low-molecular materials and high-molecular (polymer) materials. When a low molecular material is used, a vapor deposition method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.

  The self-luminous layer is formed by a vapor deposition method, an inkjet method, a dispenser method, or the like using a shadow mask. In any case, color display is possible by forming light emitting layers (red light emitting layer, green light emitting layer, and blue light emitting layer) capable of emitting light having different wavelengths for each pixel. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, but either method may be used. Needless to say, an EL display device emitting monochromatic light can also be used.

  When the self-luminous layer 29 is formed, the cathode 30 is formed thereon. It is desirable to remove moisture and oxygen present at the interface between the cathode 30 and the self-luminous layer 29 as much as possible. Therefore, it is necessary to devise such that the self-luminous layer 29 and the cathode 30 are continuously formed in a vacuum, or the self-luminous layer 29 is formed in an inert atmosphere and the cathode 30 is formed in a vacuum without being released to the atmosphere. . In this embodiment, the above-described film formation can be performed by using a multi-chamber type (cluster tool type) film formation apparatus.

  In this embodiment, a laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used as the cathode 30. Specifically, a LiF (lithium fluoride) film having a thickness of 1 nm is formed on the self-light-emitting layer 29 by vapor deposition, and an aluminum film having a thickness of 300 nm is formed thereon. Of course, you may use the MgAg electrode which is a well-known cathode material. The cathode 30 is connected to the wiring 16 in a region indicated by 31. The wiring 16 is a power supply line for applying a predetermined voltage to the cathode 30, and is connected to the FPC 17 through an anisotropic conductive paste material 32. A resin layer 80 is further formed on the FPC 17 to increase the adhesive strength of this portion.

  In order to electrically connect the cathode 30 and the wiring 16 in the region indicated by 31, it is necessary to form contact holes in the interlayer insulating film 26 and the insulating film 28. These may be formed when the interlayer insulating film 26 is etched (when the pixel electrode contact hole is formed) or when the insulating film 28 is etched (when the opening before the self-light emitting layer is formed). Further, when the insulating film 28 is etched, the interlayer insulating film 26 may be etched all at once. In this case, if the interlayer insulating film 26 and the insulating film 28 are the same resin material, the shape of the contact hole can be improved.

  Further, the wiring 16 is electrically connected to the FPC 17 through a gap (but sealed with a sealing agent 81) between the sealing material 19 and the substrate 10. Although the wiring 16 has been described here, the other wirings 14 and 15 are similarly electrically connected to the FPC 17 through the sealing material 18.

  Here, a more detailed cross-sectional structure of the pixel portion is shown in FIG. 19, a top structure is shown in FIG. 20A, and a circuit diagram is shown in FIG. 20B. In FIG. 19A, a switching TFT 2402 provided over a substrate 2401 is formed with the same structure as the pixel TFT 204 of FIG. The double gate structure has a structure in which two TFTs are substantially connected in series, and there is an advantage that an off-current value can be reduced by forming an LDD provided with an offset region that does not overlap with the gate electrode. . In this embodiment, a double gate structure is used, but a triple gate structure or a multi-gate structure having more gates may be used.

  The current control TFT 2403 is formed using the first n-channel TFT 202 shown in FIG. This TFT structure is a structure in which an LDD that overlaps with the gate electrode is provided only on the drain side, and has a structure in which the parasitic capacitance between the gate and the drain and the series resistance are reduced to increase the current driving capability. From another point of view, the structure is very important. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows, and it is also an element with a high risk of deterioration due to heat or hot carriers. Therefore, by providing an LDD region that partially overlaps the gate electrode in the current control TFT, it is possible to prevent the TFT from being deteriorated and to improve the operation stability. At this time, the drain line 35 of the switching TFT 2402 is electrically connected to the gate electrode 37 of the current control TFT by the wiring 36. A wiring indicated by 38 is a gate line for electrically connecting the gate electrodes 39a and 39b of the switching TFT 2402.

  In this embodiment, the current control TFT 2403 is illustrated with a single gate structure, but a multi-gate structure in which a plurality of TFTs are connected in series may be used. Further, a structure may be employed in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of portions so that heat can be emitted with high efficiency. Such a structure is effective as a countermeasure against deterioration due to heat.

  Further, as shown in FIG. 20A, the wiring to be the gate electrode 37 of the current control TFT 2403 overlaps the drain line 40 of the current control TFT 2403 with an insulating film in the region indicated by 2404. At this time, a capacitor is formed in a region indicated by 2404. This capacitor 2404 functions as a capacitor for holding the voltage applied to the gate of the current control TFT 2403. The drain line 40 is connected to a current supply line (power supply line) 2501, and a constant voltage is always applied.

  A first passivation film 41 is provided on the switching TFT 2402 and the current control TFT 2403, and a planarizing film 42 made of a resin insulating film is formed thereon. It is very important to flatten the step due to the TFT using the flattening film 42. Since the self-light-emitting layer formed later is very thin, a light emission failure may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the self-luminous layer can be formed as flat as possible.

  Reference numeral 43 denotes a pixel electrode (EL element cathode) made of a highly reflective conductive film, which is electrically connected to the drain of the current control TFT 2403. As the pixel electrode 43, it is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a laminated film thereof. Of course, a laminated structure with another conductive film may be used. Further, the light emitting layer 44 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) may be formed separately. A π-conjugated polymer material is used as the organic EL material for the light emitting layer. Typical polymer materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene. There are various types of PPV organic EL materials such as “H. Shenk, H. Becker, O. Gelsen, E. Kluge, W. Kreuder, and H. Spreitzer,“ Polymers for Light Emitting ”. Materials such as those described in “Diodes”, Euro Display, Proceedings, 1999, p. 33-37 ”and Japanese Patent Laid-Open No. 10-92576 may be used.

  As a specific light emitting layer, cyanopolyphenylene vinylene may be used for a light emitting layer that emits red light, polyphenylene vinylene may be used for a light emitting layer that emits green light, and polyphenylene vinylene or polyalkylphenylene may be used for a light emitting layer that emits blue light. The film thickness may be 30 to 150 nm (preferably 40 to 100 nm). However, the above example is an example of an organic EL material that can be used as a light emitting layer, and is not necessarily limited to this. A self-luminous layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a polymer material is used as the light emitting layer is shown, but a low molecular weight organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. As these organic EL materials and inorganic materials, known materials can be used.

  In this embodiment, a self-luminous layer having a laminated structure in which a hole injection layer 46 made of PEDOT (polythiophene) or PAni (polyaniline) is provided on the light-emitting layer 45 is used. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of the present embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (upward of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used, but it is possible to form after forming a light-emitting layer or hole injection layer with low heat resistance. What can form into a film at low temperature as much as possible is preferable.

  When the anode 47 is formed, the self-luminous element 2405 is completed. Note that the EL element 2405 here refers to a capacitor formed by the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 46, and the anode 47. As shown in FIG. 20A, since the pixel electrode 43 substantially matches the area of the pixel, the entire pixel functions as an EL element. Therefore, the use efficiency of light emission is very high, and a bright image display is possible.

  By the way, in the present embodiment, a second passivation film 48 is further provided on the anode 47. The second passivation film 48 is preferably a silicon nitride film or a silicon nitride oxide film. This purpose is to cut off the EL element from the outside, and has both the meaning of preventing deterioration due to oxidation of the organic EL material and the meaning of suppressing degassing from the organic EL material. This increases the reliability of the EL display device.

  As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 20, and includes a switching TFT having a sufficiently low off-current value and a current control TFT resistant to hot carrier injection. Have. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

  FIG. 19B shows an example in which the structure of the self-luminous layer is inverted. The current control TFT 2601 is formed in the same structure as the p-channel TFT 201 in FIG. For the manufacturing process, Embodiment Mode 1 may be referred to. In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film made of a compound of indium oxide and zinc oxide is used. Of course, a conductive film made of a compound of indium oxide and tin oxide may be used.

  Then, after banks 51a and 51b made of insulating films are formed, a light emitting layer 52 made of polyvinylcarbazole is formed by solution coating. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode 54 made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, the EL element 2602 is formed. In the case of the present embodiment, the light generated in the light emitting layer 53 is emitted toward the substrate on which the TFT is formed as indicated by an arrow. In the case of the structure as in this embodiment, the current control TFT 2601 is preferably a p-channel TFT.

  The EL display device described in this example as described above can be used as a display portion of the electronic device of the seventh embodiment.

[Embodiment Mode 9] In this embodiment mode, an example of a pixel having a structure different from the circuit diagram shown in FIG. 20B is shown in FIG. In this embodiment, 2701 is a source wiring of the switching TFT 2702, 2703 is a gate wiring of the switching TFT 2702, 2704 is a current control TFT, 2705 is a capacitor, 2706 and 2708 are current supply lines, and 2707 is an EL element. .

  FIG. 21A shows an example in which the current supply line 2706 is shared between two pixels. In other words, the two pixels are formed so as to be symmetrical about the current supply line 2706. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.

  FIG. 21B illustrates an example in which the current supply line 2708 is provided in parallel with the gate wiring 2703. In FIG. 21B, the current supply line 2708 and the gate wiring 2703 are provided so as not to overlap. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, since the exclusive area can be shared by the power supply line 2708 and the gate wiring 2703, the pixel portion can be further refined.

  In FIG. 21C, a current supply line 2708 is provided in parallel with the gate wiring 2703 as in the structure of FIG. 21B, and two pixels are symmetrical with respect to the current supply line 2708. It is characterized in that it is formed. It is also effective to provide the current supply line 2708 so as to overlap any one of the gate wirings 2703. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined. In FIGS. 21A and 21B, a capacitor 2705 is provided to hold a voltage applied to the gate of the current control TFT 2704; however, the capacitor 2705 can be omitted.

  Since the n-channel TFT of the present invention as shown in FIG. 19A is used as the current control TFT 2403, it has an LDD region provided so as to overlap with the gate electrode through the gate insulating film. A parasitic capacitance generally called a gate capacitance is formed in the overlapping region, but this embodiment is characterized in that this parasitic capacitance is actively used in place of the capacitor 2404. The capacitance of this parasitic capacitance 21 varies depending on the area where the gate electrode and the LDD region overlap, and is determined by the length of the LDD region included in the overlapping region. Similarly, the capacitor 2705 can be omitted.

  Note that the circuit configuration of the EL display device shown in this embodiment mode may be selected from the TFT configuration shown in Embodiment Mode 1 to form the circuit shown in FIG. In addition, the EL display panel of this example can be used as the display unit of the electronic device of the seventh embodiment.

  As shown in the first embodiment, the gate electrode and the gate wiring of the TFT are in contact with each other without being in contact with the contact hole outside the island-like semiconductor layer. Tables 1 and 2 show the results of evaluating the resistance of the gate electrode and the gate wiring in such a structure. Table 1 shows sheet resistance values of materials forming the gate electrode and the gate wiring.

  Table 2 shows the results obtained by forming contact chains (number of contacts 100 to 200) in order to evaluate the contact resistance between the gate electrode and the gate wiring, and obtaining the contact resistance per contact portion from the measured values. The area of one contact part was 4 μm × 10 μm or 6 μm × 10 μm.

Two types of gate electrodes were produced: a TaN film and a Ta film laminated film and a W film. The gate wiring was made of Al. However, 1% by weight of Nd is added to this Al (hereinafter referred to as an Al—Nd film). From the values shown in Table 2, assuming that the area of the overlapping portion of the gate electrode and the gate wiring is 40 μm ² , the film obtained by stacking the TaN film and the Ta film has a thickness of about 200Ω and the W film has a value of about 0.1Ω.

  FIG. 22 shows a result obtained by observing an overlapping portion of a gate electrode formed by stacking a TaN film and a Ta film and an Al—Nd film with a transmission electron microscope (TEM). FIG. 23 is an enlarged view of the interface between the Ta film and the Al—Nd film, and energy dispersion X-ray spectroscopy (EDX) at points * 1 to * 4 shown in the figure. The composition was examined. As a result, Al was confirmed in * 1 and Ta in * 4, but Al and oxygen were detected in * 2, Ta and oxygen were detected in * 3, and a layer containing oxide was formed. Turned out to be. This is considered to be because the surface of the Ta film is oxidized by performing a heat treatment step for activating the impurity element after forming the Ta film as the gate electrode. Furthermore, it is considered that when an Al—Nd film is formed, oxygen on the surface of the Ta film oxidizes the Al—Nd film. Such an increase in contact resistance was a result that was particularly noticeable when Ta was used.

  However, when the influence of contact resistance on the signal waveform was examined by simulation, it was confirmed that there was not much influence at about 200Ω. 26A and 26B show changes in the rising waveform and the falling waveform depending on the resistance value. The equivalent circuit used for the calculation is shown inserted in the figure. Here, R2 corresponding to the contact resistance was calculated from 1Ω to 1MΩ, but it was confirmed that there was almost no influence of the contact resistance up to about 10 kΩ.

  In addition, an energization test was performed as a reliability test of the contact portion, and changes in contact resistance were examined. A test sample with a contact area of 40 μm 2 and 200 contacts was prepared, and a current of 1 mA was applied in an atmosphere at 180 ° C. for 1 hour. The above two types of gate electrode materials were examined, but almost no change in contact resistance was observed.

  The reliability of the fabricated TFT was examined by a bias-thermal stress test (hereinafter referred to as BT test). The TFT has a channel length of 8 μm and a channel width of 8 μm. Test conditions were maintained at 150 ° C. for 1 hour with a gate voltage of +20 V and a drain voltage of 0 V for an n-channel TFT. 24A and 24B show the results of the n-channel TFT and the p-channel TFT, respectively, but in any case, deterioration due to bias stress is hardly observed.

The effect of signal delay due to the difference of gate wiring materials was evaluated. FIG. 25 shows signal waveforms at the input part and the terminal part, FIG. 25 (A) shows the rising waveform, and FIG. 25 (B).
Indicates a falling waveform. The distance between the input part and the terminal part is 83 mm. In FIG. 25, a characteristic denoted by J2 is a sample in which a TaN film and a Ta film are stacked to form a gate wiring, and a sample denoted by J4 is a sample in which a gate wiring is formed by an Al—Nd film. The width of the gate wiring is 10 μm. In the former sample, there is a large difference in the rise and fall times of the input part and the terminal part, whereas in the latter sample, the difference is very small. Table 3 shows a summary of the delay time. The delay time of the J2 sample is about ten times that of the J4 sample, and as can be seen from the sheet resistance values shown in Table 1, it can be determined that the resistance of the wiring material has an influence.

  From this result, it was shown that when the screen size is 4 inch class or more, it is necessary to form the gate wiring connected to the gate electrode with a low resistance material as in the present invention.

9 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a driver circuit TFT. FIG. 9 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a driver circuit TFT. FIG. 9 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a driver circuit TFT. FIG. 9 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a driver circuit TFT. FIG. FIG. 5 is a cross-sectional view of a pixel TFT, a storage capacitor, and a driver circuit TFT. FIG. 9 is a top view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a driver circuit TFT. FIG. 9 is a top view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a driver circuit TFT. FIG. 9 is a top view illustrating a manufacturing process of a TFT of a driver circuit. FIG. 6 is a top view illustrating a manufacturing process of a pixel TFT. The top view which shows the input-output terminal of a liquid crystal display device, and wiring circuit arrangement | positioning. Sectional drawing which shows the structure of a liquid crystal display device. The perspective view which shows the structure of a liquid crystal display device. Top view showing pixels in display area Circuit block diagram of liquid crystal display device The figure which shows the positional relationship of a gate electrode and a LDD area | region. The figure which shows the connection of a gate electrode and gate wiring. FIG. 11 illustrates an example of a semiconductor device. 4A and 4B are a top view and a cross-sectional view illustrating a structure of an EL display device. FIG. 6 is a cross-sectional view of a pixel portion of an EL display device. FIG. 6 is a top view and a circuit diagram of a pixel portion of an EL display device. 7 is an example of a circuit diagram of a pixel portion of an EL display device. The cross-sectional TEM photograph in the overlapping part of a gate electrode and gate wiring. Sectional TEM photograph in the vicinity of the interface between the gate electrode (Ta) and the gate wiring (Al-Nd). The graph which is a VG-ID characteristic of TFT and shows the result of a bias-thermal stress test. The graph which shows the rise time (A) and fall time (B) of the signal waveform in the input part and terminal part of gate wiring. The graph which shows the result of having calculated the influence of the contact resistance of a gate electrode and gate wiring by simulation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Substrate 102 Base film 103b Crystalline semiconductor layer 104-107 Island-like semiconductor layer 128-131 Gate electrode, 132 Capacity wiring 128a-132a Conductive layer (A)
128b to 132b conductive layer (B)
128c to 132c conductive layer (C)
147, 148 Gate wiring, 149 capacitance wiring 147a-149a Conductive layer (D)
147b-149b conductive layer (E)
150 First interlayer insulating films 151 to 154 Source wirings 155 to 158 Drain electrode 159 Passivation film 160 Second interlayer insulating films 161 and 162 Pixel electrode

Claims (9)

The display region includes a semiconductor layer, a gate insulating film, a gate electrode and a gate wiring in contact with the gate insulating film, and a silicon oxide film in contact with the gate electrode and the gate wiring.
The gate electrode made of the first to third conductive layers is electrically connected to the gate wiring made of the fourth and fifth conductive layers at a connection portion, and the connection portion forms a channel of the semiconductor layer. Provided outside the area,
The first conductive layer includes at least one selected from tantalum, tungsten, titanium, and molybdenum and nitrogen,
The second conductive layer is formed on the first conductive layer, and has at least one selected from tantalum, tungsten, titanium, and molybdenum as a main component,
Said third conductive layer comprises tantalum, tungsten, titanium, at least one nitrogen selected from molybdenum,
The fourth conductive layer is in contact with the third conductive layer and includes aluminum or copper;
The fifth conductive layer is formed on the fourth conductive layer and includes at least one selected from tantalum, tungsten, titanium, and molybdenum. The display region includes a semiconductor layer, an insulating film containing silicon, a gate electrode and a gate wiring in contact with the insulating film containing silicon, and a silicon oxide film in contact with the gate electrode and the gate wiring.
The gate electrode made of the first to third conductive layers is electrically connected to the gate wiring made of the fourth and fifth conductive layers at a connection portion, and the connection portion forms a channel of the semiconductor layer. Provided outside the area,
The first conductive layer includes at least one selected from tantalum, tungsten, titanium, and molybdenum and nitrogen,
The second conductive layer is formed on the first conductive layer, and has at least one selected from tantalum, tungsten, titanium, and molybdenum as a main component,
Said third conductive layer comprises tantalum, tungsten, titanium, at least one nitrogen selected from molybdenum,
The fourth conductive layer is in contact with the third conductive layer and includes aluminum or copper;
The fifth conductive layer is formed on the fourth conductive layer and includes at least one selected from tantalum, tungsten, titanium, and molybdenum. In claim 1,
The semiconductor device, wherein the gate insulating film is a single layer or a stacked layer. In claim 2,
The semiconductor device is characterized in that the insulating film containing silicon is a single layer or a stacked layer. In any one of Claims 1 thru | or 4,
The semiconductor device, wherein the third conductive layer overlaps and contacts the fourth conductive layer without a contact hole outside the channel formation region of the semiconductor layer. In any one of Claims 1 thru | or 5 ,
The silicon oxide film has wirings electrically connected to a source region and a drain region of the semiconductor layer, respectively, and the wiring has a three-layer structure in which titanium, aluminum containing titanium, and titanium are continuously formed. A semiconductor device comprising a laminated film. In any one of Claims 1 thru | or 6 ,
The semiconductor layer has a channel formation region, an LDD region, a source region and a drain region,
The LDD region is provided so as not to overlap with the gate electrode. In any one of Claims 1 thru | or 6 ,
The semiconductor layer has a channel formation region, an LDD region, a source region and a drain region,
The LDD region has a first region that overlaps with the gate electrode and a second region that does not overlap with the gate electrode. Electronic device using a semiconductor device according to any one of claims 1 to 8.

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