JP3092133B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and in particular, is applied to a master slice type gate array having a plurality of gate-isolated insulated gate field-effect transistors as basic cells. The improvement of the gate shape.

[Conventional technology]

As shown in FIG. 15, a chip internal configuration of a conventional channelless gate array includes a cell row in which a plurality of gate-separated basic cells 2 are arranged vertically and horizontally in the center of a silicon chip (die) 1; It comprises a plurality of input / output buffers B arranged around the periphery of the silicon chip 1. FIG. 16 is an enlarged view of the above-mentioned cell row. The basic cells 2 are arranged in a matrix. In this type of gate array, insulated gate field effect transistors (hereinafter, referred to as MOSFETs) in the basic cell 2 or adjacent or remote basic cells 2 are appropriately connected to each other by a first layer or second layer Al wiring. Thus, a desired large-scale logic circuit is formed.

FIG. 17 is a circuit diagram of the gate-separated basic cell 2. The basic cell 2 is a complementary insulated gate field effect transistor (hereinafter referred to as CMOSFET) 2a, 2b in which two pairs of gates are separated.
The gates G of the respective CMOSFETs are separated from each other, and the drains S or the sources D of the MOSFETs of the same conductivity type are shared. As shown in FIG. 18, the conventional layout configuration of the gate-separated basic cell 2 is such that a P-well 3 occupying a planar rectangular area formed by diffusion of a P-type impurity on an N-type substrate, The polysilicon gates 4N, 5N, which extend substantially over the well 3 and are line-symmetrically parallel to each other, are formed via the gate oxide film, and both the polysilicon gates 4N, 4N, Five
Self-alignment (self-alignment) by ion implantation of N-type impurities using the polysilicon gates 4P and 5P formed at the N-parallel translation position in the channel width direction via the gate oxide film and the polysilicon gates 4N and 5N as a mask ) And the polysilicon gates 4P, 5P
P-type diffusion region 7 formed in a self-aligned manner by ion implantation of P-type impurities using
A high-concentration P-type stopper 8 is formed adjacent to the high-concentration P-type diffusion region 7 and is formed by diffusion adjacent to the high-concentration P-type diffusion region 7 to supply the power supply potential V _DD to the N-type substrate. High-concentration N-type guard ring 9 that supplies power supply potential V _CC 9
And

Each of the polysilicon gates 4N, 5N, 4P, and 5P has a substantially U-shape, and includes a substantially narrow gate electrode portion g and substantially square gate terminal extraction portions T ₁ and T ₂ connected to both ends thereof. It is configured. Immediately below each gate electrode portion g, a channel region is formed.
The region sandwiched between two gate electrode parts g is two N-channels
The region shared by two gate electrode portions g parallel to each other in the high-concentration P-type diffusion region 7 is also shared by two P
It is shared as the drain or source region of the channel MOSFET.

In the gate array having the conventional gate-separated basic cell 2 described above, for example, a CMOS which is horizontally adjacent in the basic cell is used.
When wiring the gates of the opposite FETs,
As shown in FIG. 19, the adjacent gate terminal take-out portion
T ₁ and T ₂ are connected through contact holes (shown as x marks)
A short distance connection can be made with the Al wiring l ₁ (shown as a solid line) in the layer. Also, the CM adjacent to the diagonal position in the basic cell 2
In the case where the gates of the OSFETs are cross-connected to each other, for example, as shown in FIG. 20, the gate terminal extraction portions T ₁ and T ₂ adjacent to one diagonal position are connected to the first layer of the first layer through the contact holes. while connected by the Al wiring l _11, the Al wiring of the first layer l ₁₂ via the gate terminal lead-out portion T ₁ adjacent the other diagonal line, T ₂ a contact hole and a via (shown as ○ mark), l
₁₃ and a second layer Al wiring l ₂ (shown as a parallel double solid line). The gate-separated basic cell 2 can be easily reduced to the common gate basic cell if the wiring pattern shown in FIG. 19 is adopted, and the cross-connection wiring pattern shown in FIG. 20 cannot be realized with the common gate basic cell. In the basic cell 2. In particular, the possibility of this cross connection is advantageous when configuring a functional cell such as a transmission gate.

[Problems to be solved by the invention]

However, in the gate array having the gate-separated basic cell 2 described above, when the wiring layout of the cross connection between the adjacent gates as shown in FIG. the formation of the eyes of the Al wiring l ₂ or more multi-layer wiring are unavoidable due. If in the circuit configuration in a close area would use the Al wiring l ₂ of the second layer, passing prohibition region (prohibited tracks) next to the external wiring to which the second-layer wiring regions intensive second layer wiring, this When the passage prohibition area increases in the chip, the external wiring property (easiness of connection between the functional cells over a long distance or between the functional cell and the input / output buffer) is reduced. For example, when a D flip-flop (delayed flip fiop) shown in FIG. 21 is configured as a functional cell, two basic cells 2 are required.
As shown in the drawing, a second layer wiring prohibited track is inevitably generated in a part of the area, and it is no longer possible to pass the second layer external wiring on this prohibited track.

Of course, even when a wiring layout of cross connection between adjacent gates is formed, the wiring of one first layer is replaced by the wiring of the other first layer from the wiring of the other first layer without using the Al wiring of the second layer. Although it is possible to temporarily form a detour outside the region, if the first-layer wiring is laid over a long distance, the wiring occupation area is inevitably increased. (Ease of wiring between cells). When the first-layer wiring is complicated and long, especially in the trend of fine processing of wiring, the wiring capacitance increases due to an increase in wiring resistance and wiring area, and the wiring time constant increases. . When this wiring time constant increases,
A delay in the operation speed (wiring delay time) becomes apparent.

SUMMARY OF THE INVENTION Accordingly, the present invention is to solve the above-mentioned problem, and an object of the present invention is to improve the gate shape in a gate-separated basic cell, thereby forming a wiring layout of cross-connection between adjacent gates in the basic cell. It is an object of the present invention to provide a master slice type semiconductor device which can be realized only by the first layer wiring having a short distance, and can improve both internal wiring characteristics and external wiring characteristics as compared with the related art.

[Means for solving the problem]

In a semiconductor device having a plurality of basic cells arranged and forming a desired logic circuit by appropriately connecting the inside of the basic cells and between the basic cells by wiring, the basic cells are of a first conductivity type. At least one insulated gate type field effect transistor and a second conductive type second insulated gate type field effect transistor adjacent thereto are provided, and each gate electrode of both transistors has a gate terminal lead-out portion on an adjacent side. In the above configuration, the means taken by the present invention is such that the gate terminal extraction portion of the first insulated gate field effect transistor includes at least a first wiring contact region and a second wiring contact region. The shape and the area are provided with.

Usually, each gate electrode is formed of polysilicon in consideration of the formation of the source or drain region by self-alignment. However, the gate terminal extraction portion is formed in a region that does not substantially contribute to the formation of the channel inversion layer. The gate terminal extraction portion may be formed above the gate electrode formation layer. However, from the standpoint of eliminating a single process, it is desirable to form the gate terminal extraction portion at the same layer level as the gate electrode with the aid of the gate formation step.

In a general semiconductor device of this kind, since it is meaningful to reduce the on-resistance, the shape and size of the gate electrode will be narrow with a short channel length and a long channel width. The layout relationship between the effect transistor and the second insulated gate field effect transistor is based on the necessity of automatic placement and routing in which wiring is laid in a vertical or horizontal grid in a straight line or at right angles.
The channel regions (gate electrodes) are arranged so as to be oriented in the same direction (vertical grid direction or horizontal grid direction). Of course, both channel regions may be located in the same vertical grid direction or horizontal grid, or may be located in adjacent parallel grids.

As described above, the gate terminal take-out portion is formed on a region other than the source region or the drain region. However, since the gate electrode will have a narrow width, the width of the gate terminal take-out portion formed at the end thereof is reduced. Is generally wider than the width (channel length) of the gate electrode. In such a case, generally, the minimum area of the gate terminal take-out portion will be set to at least approximately one grid area (one vertical and one horizontal grid length).

When the shape of the gate terminal extraction portion of the first insulated gate field effect transistor is substantially a crank shape, the first wiring contact region is located closer to the gate electrode as in the conventional case, but the second wiring contact region is formed. The contact area is located at the end of the crank shape. Here, the first and second wiring contact regions occupy both ends of the crank shape.
A region connecting the two can be used as a third wiring contact region. Therefore, when the gate terminal take-out portion is formed in a crank shape, it generally has at least three wiring contact regions.

On the other hand, when the gate terminal extraction portion of the first insulated gate field effect transistor is substantially rectangular,
The first wiring contact region is located closer to the gate electrode as in the prior art, while the second wiring contact region is located at the end of the rectangle. In such a case, the rectangular footprint would require at least two grid areas. In the case of having the above-mentioned crank-shaped gate terminal take-out portion, the vertical or horizontal grid of the wiring that can be connected to the second wiring contact region is different from that of the wiring that can be connected to the first wiring contact region. One of the vertical or horizontal grids of the wiring that can be connected to the second wiring contact region, the vertical or horizontal grid of the wiring that can be connected to the first wiring contact region. Is equal to either of

By the way, in the gate terminal take-out part, as the number of wirings that can be connected to the gate terminal take-out part increases, the internal and external wiring properties improve, but conversely, the occupation area of the gate terminal take-out part increases, and the degree of element integration deteriorates. . In the case of constructing a logic circuit, it is extremely rare that a large number of wiring connections are made to one gate terminal lead-out part. In general, it is generally possible to freely draw wiring from a gate terminal lead-out part to a vertical grid or a horizontal grid. This is meaningful in automatic placement and routing in which wiring is connected along a grid. In such a situation, when the gate terminal take-out portion is substantially rectangular, four wires are drawn in different grid directions in the vertical and horizontal directions substantially in the same manner as in the case of the substantially crank shape. A wiring relay region is formed in a region sandwiched between the gate terminal extraction portions. It is desirable that the wiring relay region is also formed of polysilicon or the like in the same layer as the gate electrode.

[Action]

As described above, since the gate terminal take-out portion has the second wiring contact region in addition to the first wiring contact region, for example, the first layer wiring is connected to the second wiring contact region via the contact hole. Is performed, the wiring distance is shorter than when the first wiring contact region is used, and the first wiring contact region can be used as a passage region of the first layer wiring. Therefore, the gate cross connection can be realized with only the first layer wiring and with a short detour distance. The advantage of shortening the wiring distance suppresses the wiring delay time and improves the internal wiring property. Further, the advantage that the first wiring contact region is used as it is as the passage region for the first wiring layer is that the generation of prohibited tracks due to the decrease in the number of formation locations of the second wiring layer is suppressed, and the external wiring performance is improved.

When the shape of the gate terminal take-out portion is substantially hook-shaped or crank-shaped, it does not protrude into the source or drain region within the area occupied by the adjacent gate terminal take-out portion, but intersects only with the first layer wiring. Connection is achieved.

In the case where the gate terminal take-out portion extends substantially in a rectangular shape and the wiring relay region is formed, the first layer wiring is connected to both ends of the wiring relay region via contact holes, In addition, by passing another first layer wiring over the central portion of the wiring relay area, cross connection between gates is realized only by the first layer wiring. Even in such a case, the first layer wiring required for the cross connection does not protrude into the source or drain region. In such a case, although there is no cross connection, even when the connection is made between the adjacent gate terminal take-out portions, there may be an empty grid through which other first layer wirings pass during the connection. Not only the prohibited tracks of the wiring but also the prohibited tracks of the first layer wiring can be suppressed.

In other words, according to the present invention, the connection wiring between the gates is not burdened by the first layer and the second layer wiring as in the related art, but is substantially less than one grid length below the formation layer of the first layer wiring. A second wiring contact region, which is a region where a connection wiring or a relay wiring or a contact hole is to be formed, is connected to the first wiring contact region in advance, and the first and second wiring contact regions reduce the burden of the first layer wiring. By substituting, the formation area of the first-layer wiring and the like are reduced, and the
This is intended to reduce the formation area of the layer wiring and the like, thereby suppressing the occurrence of prohibited tracks.

〔Example〕

Next, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

First Embodiment FIG. 1 is a view showing a gate-separated basic cell row according to a first embodiment of the present invention, and FIG. 2 is an enlarged plan view showing the basic cell. FIG. 3 (A) is a cross-sectional view showing a state cut along the line AA 'in FIG. 2, and FIG. 3 (B) is a cross section cut along the line BB' in FIG. It is sectional drawing which shows the state which performed.

The plurality of gate-separated basic cells 12 are arranged in a matrix. The planar configuration of the gate-separated basic cell 12 is such that a pair of N-channel MOSFETs (F _N1 ,
F _N2 ) and a pair of these adjacent and parallel P channels M
It consists of a pair with OSFET (F _P1 , F _P2 ). N-channel MOSFET
The (F _N1 , F _N2 ) formation portion includes a low-concentration P well 3 occupying a planar rectangular area formed by diffusion of a P-type impurity on a low-concentration N-type silicon substrate 20; Parallel polysilicon gates 14N and 15N formed on the well 3 via the gate oxide film 13 and the polysilicon gate 1
A high-concentration N-type diffusion region 6 serving as a source or drain region formed by self-alignment (self-alignment) by ion implantation of N-type impurities using 4N and 15N as a mask, and diffusion formation adjacent to the high-concentration N-type diffusion region 6 The structure has a high-concentration P-type stopper 8 for supplying the power supply potential V _SS to the P well 3 and a local oxide film (LOCOS) 10 deposited on the P well 3 thickly. On the other hand, P-channel MOSFET (F _P1 , F _P2 )
Are formed on the substrate in the region adjacent to the P-well 3 through the parallel polysilicon gates 14P and 15P formed via the gate oxide film 13, and the P-type impurity using the polysilicon gates 14P and 15P as a mask. Of high concentration P as a source or drain region formed by self-alignment by ion implantation of
Voltage diffusion region 7 and power supply voltage V _DD to N-type substrate 20 for holding a withstand voltage and diffusion formed adjacent to high-concentration P-type diffusion region 7.
This structure has a high-concentration N-type stopper 9 for supply and a local oxide film 10 deposited thickly on the substrate 20. The polysilicon gates 14P and 15P are substantially U-shaped, and are symmetrically spaced from each other. As shown in FIG. 4, each of the polysilicon gates 14P and 15P has a narrow gate electrode portion g having a length of substantially 4 grids and a gate terminal having a substantially square grid area connected to both ends thereof. It is composed of take-out sections T ₁ and T ₂ . These gate terminal extraction portions T ₁ and T ₂ have a single wiring connection position, that is, an area in which wiring can be attached via a single contact hole for ohmic contact. Immediately below the gate electrode portions g, g, which are separated and parallel by one grid, are channel regions each having a channel width of approximately 4 grid lengths.
A region sandwiched between two gate electrode portions g, g in parallel with each other in the mold diffusion region 7 is shared as a drain or source region of two P-channel MOSFETs. The drain or source regions of the two P-channel MOSFETs are respectively connected to four wiring connection positions (4
Grid area) and a high concentration N-type stopper 9
Has two wiring connection positions (two grid areas) connected in the channel width direction. The gates 14P and 15P themselves are symmetrical with respect to the center line of the channel width.

On the other hand, the polysilicon gates 14N and 15N are formed at positions shifted from the polysilicon gates 14P and 15P, respectively, but the planar shapes of the gates 14N and 15N are the gates 14P and 1N.
Different from that of 5P. That is, the gate 14N has a shape in which the hatched area shown in the figure is connected to the shape of the gate 14P, and a narrow gate electrode portion g having a substantially 4 grid length and a crank-shaped gate terminal connected to both ends thereof. Extraction unit
T ₁ ′ and T ₂ ′. Terminal lead-out portion T ₁ adjacent to the gate 14P 'is terminal lead portion of the gate 14P T ₁
First wiring connection positions (one grid area) t ₁ corresponding, this position t ₁ second wiring connection position extending in the channel length direction outward from (1 grid area) t _2, this extending from position t ₂ to the gate 14P side of the channel width direction, the third wire connecting positions (one grid area) of which is adjacent to the terminal take-out portion T ₁ of the gate 14P t ₃
It is composed of The 'terminal lead-out portion T ₂ of the opposite side of the' terminal lead-out portion T _1, the first wiring connection positions corresponding to the terminal lead-out portion T ₂ of the gate 14P (1
A grid area) t _1, the second wiring connection position extending from the position t ₁ to the channel length direction outward (1
A grid area) t _2, and a third wiring connecting position from the position t ₂ extending in the channel width direction outward (one grid area) t ₃ Prefecture. The second and third wiring connection positions t ₂ , t in the hatched area of the gate 14N in the figure.
₃ is formed on the grid where the stoppers 8, 9 are located. The gate 14N itself has a symmetrical shape with respect to the center line of the channel width.

Terminal take-out portion T ₁ ″ of gate 15N adjacent to gate 15P
The first wiring and connection positions (one grid area) t _1, the second wiring connection position extending from the position t ₁ to the channel length direction outward corresponding to the terminal lead-out portion T ₁ of the gate 15P 'and, the position t _2' (1 grid area) t ₂ extending from the gate 14P side of the channel width direction, sandwiched between the terminal lead-out portion T ₂ of the terminal lead-out portion T ₂ and the gate 15P gate 14P And a third wiring connection position (one grid area) t ₃ ′. Also the terminal lead-out portion T ₁ "and the opposite side terminal extraction portion T _2"
The first wiring and connection positions (one grid area) t _1, the second wiring connection position extending from the position t ₁ to the channel length direction outward corresponding to the terminal lead-out portion T ₂ of the gate 15P (1 grid area) t ₂ ′ and a third extending outward from the position t ₂ ′ in the channel width direction.
And a wiring connection position (one grid area) t ₃ ′. The second and third wiring connection positions t ₂ ′, t ₃ ′ in the hatched area shown in the figure are formed in a grid sandwiched between the parallel gate electrodes g, g. And gate 15N
It is itself symmetrical with respect to the center line of its channel width. The second and third wiring connection positions t ₂ ′ and t ₃ ′ of the gate 15N have a shape obtained by chamfering the corners of the second and third wiring connection positions t ₂ and t ₃ of the gate 14N.

In the basic cell 12 having such a planar configuration, the gates 14P,
As a method of connecting the terminal take-out portions T ₂ , T _{2 of the} 15P and the terminal take-out portions T ₁ ′, T ₁ ″ of the adjacent gates 14 N, 15 N, the fifth method is used.
As shown in the figure, the terminal extraction portions T ₂ , T ₂ and the first wiring connection position t _{1 of the} terminal extraction portions T ₁ ′, T ₁ ″ are connected via contact holes (indicated by “x” in the figure). 1st layer Al wiring l _1Y
In the first case (similar to the conventional case) in which the connection is made in the horizontal grid (Y grid) direction, and for the third wiring connection of the terminal extraction portions T ₂ , T ₂ and the terminal extraction portions T ₁ ′, T ₁ ″ Position t ₃
Through a contact hole (indicated by a cross in the figure).
Vertical grid (X grid) in the second connecting direction is present in the wiring l _1X. In other words, even though it is an isolation gate type basic cell, a pair of gates adjacent to each other in the cell are separated.
When connecting the CMOSFETs as a common gate, two kinds of shortest connections are possible only with the first layer wiring having a length of one grid. Therefore, the degree of freedom in wiring is higher than before. The occupied space of the basic cell 12 according to the first embodiment is 4 in the X direction.
The grid is 12 grids in the Y direction, which is the same as that of the conventional basic cell 2 shown in FIG. The difference from the conventional basic cell 2 is that the gates 14N and 15N as shown in FIG.
(The second and third wiring connection positions t ₂ , t
₃ , t ₂ ′, t ₃ ′) at the point where they are additionally coupled, but this shaded area is located in the grid where the stoppers 8 and 9 are conventionally located as unused areas or in the area where the source and drain are shared. Since it is formed in the grid, an increase in cell area could be avoided.

Next, the gate cross connection in the basic cell 12, that is, the gate 14
Terminal lead-out portion T ₁ of the P terminal lead-out portion T ₂ and the gate 15N for "
Wire connection method and the terminal extraction portion T ₁ of the terminal lead-out portion T ₂ and the gate 14N gate 15P ', for example, as shown in FIG. 6, the gate 15N adjacent to the terminal lead-out portion T ₂ of the gate 14P vertical grid (X in the third wiring connecting position t ₃ 'and terminal lead-out portion T ₁ "first layer Al wirings l _1X
While connected to the grid) direction, the gate 15P terminal extracting portion T ₂ and the gate 14N terminal extraction portion T ₁ third wire connecting position t ₁ and the terminal lead-out portion T in the first layer Al wirings l _1XY of ' ₁ 'the first wiring connection position t ₁ and the second
Via the wiring connection position t ₂ ′.
Such in gate diagonal connection, terminal lead-out portion T ₂ of the gate 14P, the terminal extracting portion T ₂ of the gate 15P, a first wiring connecting position t ₁ and the gate 14N terminal extraction portion T ₁ "of the gate 15N terminal the X-direction third grid -Y direction 2 grid in space and the first wiring connection position t ₁ of the take-out portion T ₁ 'to make the first layer Al without using a second layer Al wiring
Interconnection became possible only with wiring. The advantage that the gate diagonal connection can be made only by the first layer Al wiring is that the generation of the prohibited track due to the formation of the second layer Al wiring can be suppressed as much as possible. Therefore, it contributes to improvement of the external wiring property.
As is apparent from a comparison between FIG. 6 and FIG.
In the conventional connection method shown in FIG., The first layer Al wirings l ₁₃
When wiring section extends on the gate electrode g it has caused inevitably as the second layer Al wiring l ₂ of the reciprocating wire section and the first layer Al wirings l _12, the X-direction third grid -Y direction second grid The total wiring does not fit in the space. On the other hand, in the present embodiment, since the second layer Al wiring is not used, a round-trip wiring section does not occur, and the wiring does not extend over the gate electrode g, so that the wiring length can be reduced. Therefore, since the wiring capacitance and the wiring resistance can be suppressed at the same time, the internal wiring property is high and the wiring delay time is reduced.

FIG. 7 is a layout diagram showing a state in which the D flip-flop shown in FIG. 21 as a functional cell is composed of two basic cells 12 according to the present embodiment, and the conventional layout shown in FIG. It should be noted that the wiring length is much shorter than that of the first embodiment, and that the second layer wiring prohibited track does not occur.

By the way, the gates 14N, 15
Each of the N terminal take-out portions T ₁ ′, T ₂ ′, T ₁ ″, T ₂ ″ has second and third wiring connection positions, respectively. Thus, for example, even when a basic cell lacking the gate 14N terminal extraction portions T ₁ ′, T ₂ ′ and the gate 15 N terminal extraction T ₂ ″ is used, the internal wiring property and the external wiring property are improved as compared with the conventional case. Needless to say, I get it.

Second Embodiment FIG. 8 is a diagram showing a gate-separated basic cell row according to a second embodiment of the present invention, and FIG. 9 is an enlarged plan view of the basic cell. In FIG. 9, the same portions as those shown in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

A plurality of basic cells 22 are arranged in a matrix. The planar configuration of the gate-separated basic cell 22 is similar to that of the first embodiment, and a pair of N-channel MOSFETs
(F _N1 , F _N2 ) and a pair of adjacent P-channel MOSFETs (F _P1 , F _P2 ) in parallel with each other.

The polysilicon gates 24N and 25N of the N-channel MOSFET are substantially U-shaped, and are spaced symmetrically from each other. No.
As shown in FIG. 10, each of the polysilicon gates 24N and 25N has a narrow gate electrode portion g having a length of substantially 4 grids.
And terminal extraction portions T ₁ and T ₂ having a substantially square grid area connected to both ends thereof. These terminal take-out portions T ₁ and T ₂ have a single wiring connection position, that is, an area where wiring can be performed through a single contact hole. The gate electrode parts g, which are separated and parallel by one grid
Immediately below g is a channel region having a channel width of approximately 4 grid lengths. In the high-concentration N-type diffusion region 6, a region sandwiched between two gate electrode portions g, g parallel to each other is two N-channels. It is shared as the drain or source region of the MOSFET.

On the other hand, the polysilicon gate 24P of the P-channel MOSFET,
25P has a substantially U-shape, and each polysilicon gate 24
The gates 24P and 25P are formed at adjacent positions where the N and 25N are laterally shifted, but the plane shapes of the gates 24P and 25P are different from the shapes of the gates 24N and 25N. That is, the gate 24P has a shape in which the hatched area shown in the figure is combined with the shape of the gate 24N, and a narrow gate electrode portion g having a length of substantially 4 grids and a substantially rectangular two grids connected to both ends thereof. Terminal take-out parts T ₁₁ , T having an area
₂₂ . Terminal lead-out portion T ₂₂ adjacent to the gate 24N has a first wiring connection positions (one grid area) corresponding to the terminal lead-out portion T ₂ of the gate 24N t
₁ and the second wiring connection position extending from the position t ₁ to the channel width direction outward (1 grit area)
and a t ₁₂ Metropolitan. The terminal lead-out portion T ₁₁ opposite to the terminal lead-out portion T ₂₂ includes a first wiring connection positions corresponding to the terminal lead-out portion T ₁ of the gate 24N (1
A grid area) t _1, the second wiring connection position extending from the position t ₁ to the channel width direction outward (1
And a grid area) t ₁₂ Metropolitan.

Terminal lead portion of the gate 25P adjacent to the gate 25 N T ₂₂
Also, the first wiring and connection positions (one grid area) t _1, the second wiring connection position extending from the position t ₁ to the channel width direction outward corresponding to the terminal lead-out portion T ₂ of the gate 25N and a (one grid area) t ₁₂ Metropolitan. The terminal lead-out portion T ₁₁ opposite to the terminal lead-out portion T ₂₂ includes a first wiring connection positions corresponding to the terminal lead-out portion T ₁ of the gate 25 N (1 grid area)
and t _1, the second wiring connection position extending from the position t ₁ to the channel width direction outward (one grid area)
and a t ₁₂ Metropolitan. Gate 24P, 25P has a channel width direction 8 grid length by adding the second wiring connection positions (one grid area) t _12. Terminal taking-out parts T ₁ , T ₁ , T ₂₂ , T of four gates 24N, 25N, 24P, 25P
_In a region sandwiched between the wirings ₂₂ , a wiring relay band 28 extending in the channel width direction in an island shape is formed. The wiring relay band 28 is an impurity-doped polysilicon formed in parallel with the gate forming process, and includes a first wiring relay position P ₁ sandwiched between the terminal extraction portions T ₁ and T ₁ , second wiring connecting position t _12, t ₁₂ and the second wiring relay position P ₂ sandwiched by the third wiring relay sandwiched between the first wiring connection position t _1, t ₁ and It is composed of a position P _3.

Gates 24P, 25 in the basic cell 22 having such a configuration
P with the adjacent gate 24N, method of connecting the 25N, as shown in FIG. 11, the gate 24P, a second wire connecting position t ₁₂ of the terminal take-out portion T _22, T ₂₂ of 25P, t ₁₂ and the gate The terminal extraction portions T ₁ , T _{1 of the} 24N, 25N are connected in the horizontal grid (Y grid) direction by a first layer Al wiring l _1Y via contact holes (indicated by “x” in the figure). This horizontally adjacent connection can be realized with the shortest length (one grid length) as in the conventional case, but the first wiring connection positions t ₁ and t ₁ not used in this connection are in the vertical direction (X direction). ) it can be passed through the first layer Al wirings l _X of. Gate take-out part T ₁ of gate 24P, 25P
In the state where the second wiring connection positions (one grid area) t ₁₂ and t ₁₂ are missing at T ₁ as shown in FIG.
Although there is no passage area of the first layer Al wiring in the X direction between the adjacent terminal take-out portions, the track becomes a forbidden track of 3 grid lengths of the first layer Al wiring. The take-out portions T ₁ , T ₁ are the first wiring connection positions t ₁ ,
The second wiring connection position t ₁₂ , which is an additional area together with t ₁ ,
Since a t _12, it can be next to adjacent connecting wirings shortest length and to the second wiring connection position t ₁₂ vacated on the, t ₁₂ on the X-direction first layer wiring l _X also pass .

Next, the gate cross connection in the basic cell 22, that is, the gate 24
P terminal extraction portion T ₂₂ and the terminal lead-out portion T ₁ of the gate 25N
And wiring connection of pin extraction portion T ₁ of the terminal lead-out portion T ₂₂ and the gate 24N gate 25P, for example, as shown in FIG. 13, a first wiring connecting position terminal lead-out portion T ₂₂ of the gate 24P t ₁ and the third wiring relay zone 28 adjacent to this
Of the wiring relay position P ₃ is connected to the X-direction in the first layer Al wirings l _1X1, moreover a terminal lead-out portion T ₁ of the first wiring relay position P ₁ and the gate 25N wiring relay zone 28 second One layer A
while connected to the X-direction at l wiring l _1X2, second wiring of the second wiring connection position t ₁₂ and the gate 24N terminal extraction portion T ₁ and the wiring relay zone 28 of the terminal lead-out portion T ₂₂ of the gate 25P terminal lead portion T of the relay position P ₂ and the gate 24P
The through over the ₂₂ second wiring connecting position t ₁₂ 1
Connect with layer Al wiring _l1XY .

In such a gate cross connection, interconnection is possible only in the first layer Al wiring without using the second layer Al wiring in the space of three grids in the X direction and three grids in the Y direction. Compared to the basic cell 12 according to the first embodiment, the basic cell 22 can be connected to the gate diagonally with only the first layer Al wiring, and can be connected to the second layer.
Similarly, the generation of the prohibited track due to the formation of the Al wiring can be suppressed as much as possible. Since the length is increased by one grid in the Y direction, the cell occupation area is slightly increased. However, as shown in FIG. in the X-direction path of the first layer wiring l _X is characterized in that secured between the take-out unit. The advantage of allowing the first layer wiring to pass between the terminal take-out portions is that the degree of freedom in the distributed formation of the first layer wiring in the X direction is increased, so that the external wiring property is improved as compared with the first embodiment. .

FIG. 14 is a layout diagram showing a state in which the D flip-flop shown in FIG. 21 is composed of two basic cells 22 according to the present embodiment. This layout is substantially the same as the layout shown in FIG. 7 and is simplified as compared with the conventional layout shown in FIG. 21. It is excellent in that no occurrences occur.

The gate 24P of the basic cells 22, terminal lead-out portion T having a second wiring connecting position t ₁₂ respectively 25P
Is provided with the _22, so that it can be easily inferred from FIG. 13, alone terminal lead-out portion T ₂₂ having a second wiring connecting position t ₁₂ only one of the gate is formed, the Needless to say, gate cross connection can be realized only by one layer wiring.

〔The invention's effect〕

As described above, according to the present invention, at least one gate terminal take-out portion of at least one insulated gate field effect transistor in a gate separation type basic cell is provided.
And the area and shape of the second wiring contact region have the following effects.

Although at most one first-layer wiring can be formed in either the X or Y grid direction on the first wiring contact area, the wiring direction of the gate wiring is diversified due to the presence of the second wiring contact area. Automatic placement and routing becomes easy. When the first layer wiring is connected to the second wiring contact area, there is an advantage of shortening the wiring distance and an advantage that the first wiring contact area can be used as a passage area of the first layer wiring as it is. The cross connection of gates can be realized with only the wiring and with a short detour distance, and both the suppression of the delay time by shortening the wiring and the suppression of the forbidden track by reducing the number of formation locations of the second layer wiring are achieved. And external wiring properties are improved.

In the case where the extension of the gate terminal take-out portion is substantially hook-shaped or crank-shaped, the dense wiring laying area of only the first-layer wiring without the first-layer wiring protruding into the source region or the drain region. As a result, cross-connection between gates within a basic cell or between adjacent basic cells becomes possible, and the above-mentioned effect becomes remarkable.

In the case where the shape of the gate terminal take-out portion extends substantially in a rectangular shape and the wiring relay region is formed, the first layer wiring does not protrude into the source region or the drain region, and the first layer wiring does not protrude. The cross connection between gates within the basic cell or between adjacent basic cells can be achieved by the dense wiring laying region of only one layer wiring, and the above-mentioned effect becomes remarkable. In such a case, although there is no cross connection, even when the connection is made between the adjacent gate terminal take-out portions, there may be an empty grid through which other first layer wirings pass during the connection. Not only forbidden tracks on wiring, but also
It is also possible to suppress the generation of the prohibited track of the layer wiring.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing a gate-separated basic cell column in a gate array according to a first embodiment of the present invention. FIG. 2 is an enlarged plan view showing the same gate-separated basic cell. FIG. 3A is a sectional view of the basic cell showing a state cut along the line AA 'in FIG. 2, and FIG. 3B is a sectional view taken along the line BB' in FIG. FIG. 3 is a cross-sectional view of the basic cell showing a state cut along the line. FIG. 4 is a plan view showing the layout configuration of the gate-separated basic cell in detail. FIG. 5 is a plan view showing a wiring connection mode between horizontally adjacent gates in the same gate-separated basic cell. FIG. 6 is a plan view showing a wiring connection mode between gates arranged in an intersection in the same gate-separated basic cell. FIG. 7 is a plan view showing a wiring connection mode in which the D flip-flop is constituted by two basic cells according to the first embodiment. FIG. 8 is a layout diagram showing a gate-separated basic cell column in a gate array according to a second embodiment of the present invention. FIG. 9 is an enlarged plan view showing the same gate-separated basic cell. FIG. 10 is a plan view showing the layout configuration of the gate-separated basic cell in detail. FIG. 11 is a plan view showing a wiring connection mode between horizontally adjacent gates in the same gate-separated basic cell. FIG. 12 is a plan view showing a wiring connection mode between horizontally adjacent gates in a mode in which the terminal extraction portion of the gate-separated basic cell does not have the second wiring connection position. FIG. 13 is a plan view showing a wiring connection mode between diagonally arranged gates in the same gate-separated basic cell. FIG. 14 is a plan view showing a wiring connection mode in which a D flip-flop is composed of two basic cells according to the second embodiment. FIG. 15 is a schematic plan view showing the internal structure of a chip in a general channelless gate array. FIG. 16 is a layout diagram showing a gate-separated basic cell column in a conventional gate array. FIG. 17 is a circuit diagram of a gate-separated basic cell according to the conventional example. FIG. 18 is an enlarged plan view showing a gate-separated basic cell according to the conventional example. FIG. 19 is a plan view showing a wiring connection mode between horizontally adjacent gates in the gate-separated basic cell according to the conventional example. FIG. 20 is a plan view showing a wiring connection state between diagonally arranged gates in the gate-separated basic cell according to the conventional example. FIG. 21 is a circuit diagram showing a state in which the D flip-flop is constituted by a MOSFET. FIG. 22 is a plan view showing a wiring connection mode in which a D flip-flop is constituted by two basic cells according to the related art. [Explanation of Symbols] 1 ... Silicon chip of channelless gate array 2a, 2b ... CMOSFET with separated gate 3 ... P well 6 ... High concentration N type diffusion region 7 ... High concentration P type diffusion region 8 High-concentration P-type stopper 9 High-concentration N-type stopper 10 Local oxide film 12,22 Gate-separated basic cell 14N, 15N, 14P, 15P, 24N, 25N, 24P, 25P ...... Polysilicon
Gate 20 ...... N-type silicon substrate 28 ...... wiring relay zone B ...... output buffer F _N1, F _N2 ...... N-channel MOSFET F _P1, F _P2 ...... P-channel _{MOSFET T 1, T 2, T} 1 ', T ₂ ′, T ₁ ″, T ₂ ″, T ₁₁ , T ₂₂ ... Gate terminal lead-out part g ...... Gate electrode part t ₁ ...... First wiring connection position t ₂ , t ₂ ′, t ₁₂ ... Second wiring connection position t ₃ , t ₃ ′... Third wiring connection position P ₁ ... First wiring relay position P ₂ ... Second wiring relay position P ₃ . wiring relay position N _ch ...... P-channel MOSFET P _ch ...... N-channel _{MOSFET l 1X, l 1Y, l} 1XY, l 1X1, l 1X2, l X ...... first layer Al wirings X ...... X grid direction (longitudinal grid Direction) Y ... Y grid direction (horizontal grid direction).

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Yasuhisa Hirabayashi 3-5-5 Yamato, Suwa-shi, Nagano Seiko Epson Corporation (56) References JP-A-61-35535 (JP, A) JP-A Sho 63-306639 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 27/118

Claims (10)

(57) [Claims] 1. A gate-separated basic cell including at least a first insulated gate field effect transistor of a first conductivity type and a second insulated gate field effect transistor of a second conductivity type, arranged vertically and horizontally. A semiconductor device in which a desired logic circuit is to be formed by appropriately connecting the inside of the basic cell and between the basic cells by wiring, wherein the first insulated gate field effect transistor and the second
The insulated gate field effect transistor has a gate isolation structure in which the gate electrodes are separated from each other at least between the two adjacent transistors, and has a gate terminal extraction part on at least the adjacent side. The gate terminal take-out portion of the first insulated gate field effect transistor has at least a second wiring contact region in addition to the first wiring contact region, and each of the first and second insulated gate field effect transistors The gate terminal take-out part is formed in the same layer as each gate electrode of the first and second insulated gate field effect transistors, and is configured to be connected to each gate electrode. The channel regions of the insulated gate field effect transistor are oriented in the same direction, and the first and second insulating gates are arranged in the same direction. The gate terminal extraction portion of the gate type field effect transistor is formed in a region other than the source and drain regions, and has a width wider than the width (channel length) of the gate electrode. The first wiring contact region in the gate terminal take-out portion of the insulated gate field effect transistor and the gate terminal take-out portion of the second insulated gate field effect transistor extend in parallel along the channel length direction. The first wiring contact region and the second wiring contact region in a gate terminal take-out portion of the first insulated gate field effect transistor, which are arranged on a second grid column, respectively, Second
A third extending parallel to the direction perpendicular to the grid row of
And a fourth grid row. 2. A gate-separated basic cell including at least a first insulated gate field effect transistor of a first conductivity type and a second insulated gate field effect transistor of a second conductivity type. A semiconductor device in which a desired logic circuit is to be formed by appropriately connecting the inside of the basic cell and between the basic cells by wiring, wherein the first insulated gate field effect transistor and the second
The insulated gate field effect transistor has a gate isolation structure in which the gate electrodes are separated from each other at least between the two adjacent transistors, and has a gate terminal extraction part on at least the adjacent side. The gate terminal take-out portion of the first insulated gate field effect transistor has at least a second wiring contact region in addition to the first wiring contact region, and each of the first and second insulated gate field effect transistors The gate terminal take-out part is formed in the same layer as each gate electrode of the first and second insulated gate field effect transistors, and is configured to be connected to each gate electrode. The channel regions of the insulated gate field effect transistor are oriented in the same direction, and the first and second insulating gates are arranged in the same direction. The gate terminal extraction portion of the gate type field effect transistor is formed in a region other than the source and drain regions, and has a width wider than the width (channel length) of the gate electrode. The first wiring contact region in the gate terminal take-out portion of the insulated gate field effect transistor and the gate terminal take-out portion of the second insulated gate field effect transistor extend in parallel along the channel length direction. The first wiring contact region and the second wiring contact region in a gate terminal take-out portion of the first insulated gate field effect transistor, which are arranged on a second grid column, respectively, Second
A semiconductor device arranged on a third grid row extending along a direction orthogonal to the grid columns. 3. The third insulated gate field effect transistor of the first conductivity type, wherein the basic cell shares one of a source region and a drain region with the first insulated gate field effect transistor and has a gate electrode parallel to each other. A fourth insulated gate field effect transistor sharing one of a source region and a drain region with the second insulated gate field effect transistor and having a gate electrode parallel to each other; 3. The semiconductor according to claim 2, wherein a wiring relay region is provided in a region between the four gate terminal extraction portions of the third and fourth insulated gate field effect transistors. apparatus. 4. The semiconductor device according to claim 3, wherein said wiring relay region is formed of the same layer as said four gate electrodes. 5. The first insulated gate field effect transistor according to claim 1, wherein a gate terminal take-out portion includes a first wiring contact region, a second wiring contact region, a first wiring contact region, and a channel length. 2. The semiconductor device according to claim 1, wherein said second wiring contact region is connected to said second wiring contact region and said third wiring contact region is connected in a channel width direction, and is bent in a crank shape. 13. The semiconductor device according to claim 1. 6. The semiconductor device according to claim 4, wherein the gate terminal take-out portion of said first insulated gate field effect transistor extends in a rectangular shape. 7. A semiconductor device having a plurality of gate-separated basic cells arranged therein, wherein a desired logic circuit is to be formed by appropriately connecting the basic cells within and between the basic cells by wiring. The basic cell includes first and second insulated gate field effect transistors of a first conductivity type in which gate electrodes are parallel to each other, and third and fourth insulated gate type field effect transistors of a second conductivity type in which gate electrodes are parallel to each other. A field effect transistor, wherein the first, second, third and fourth insulated gate field effect transistors have a gate terminal extraction part of each gate electrode on a side adjacent to each other, The gate terminal take-out portion of the insulated gate field effect transistor at least includes a first wiring contact region conductively connected to the gate electrode near the gate electrode and the third and fourth insulated gate field effect transistors. Wherein a has a second wire contact region between the gate terminal lead-out portion of the transistor. 8. A semiconductor device having a plurality of gate-separated basic cells arranged therein, wherein a desired logic circuit is to be formed by appropriately connecting the basic cells within and between the basic cells by wiring. The basic cell includes first and second insulated gate field effect transistors of a first conductivity type in which gate electrodes are parallel to each other, and third and fourth insulated gate type field effect transistors of a second conductivity type in which gate electrodes are parallel to each other. A field effect transistor, wherein the first, second, third and fourth insulated gate field effect transistors have a gate terminal extraction part of each gate electrode on a side adjacent to each other, And a gate terminal extraction portion of a gate electrode of the second insulated gate field effect transistor has at least first and second wiring contact regions, respectively, and the first, second, third, and fourth insulated gates A semiconductor device, wherein a wiring relay region is formed in a region between the four gate terminal extraction portions of the field effect transistor. 9. A semiconductor device having a plurality of arranged basic cells, wherein a desired logic circuit is to be formed by appropriately connecting the inside of the basic cells and between the basic cells by wiring, wherein the basic cells are A first conductive type first insulated gate field effect transistor having a gate terminal take-out portion composed of at least a first wiring contact region and a second wiring contact region; and the first insulated gate field effect transistor A gate lead-out portion separated from the gate electrode and adjacent to the first insulated gate field effect transistor, and having a second conductivity type second electrode adjacent to the first insulated gate field effect transistor. An insulated gate field effect transistor, wherein the gate electrode and the second insulated gate field effect of the first insulated gate field effect transistor A semiconductor device, wherein each of the gate electrodes of the transistor has a line-symmetric shape with respect to a center line of a channel width extending in a channel length direction of each of the gate electrodes. 10. A semiconductor device which has a plurality of gate-separated basic cells arranged in a channelless manner and in which a desired logic circuit is formed by appropriately connecting the basic cells within and between the basic cells by wiring. The basic cell includes first and second insulated gate field effect transistors of a first conductivity type having gate electrodes parallel to each other, and third and fourth insulated gate field effect transistors of a second conductivity type having gate electrodes parallel to each other. An insulated gate type field effect transistor, wherein the first, second, third and fourth insulated gate type field effect transistors have gate terminal take-out portions on sides adjacent to each other; The gate terminal take-out portion of the insulated gate field effect transistor is connected to the first insulated gate field effect transistor near the gate electrode by a first terminal.
A wiring contact region, a second wiring contact region sandwiched between gate terminal extraction portions of the third and fourth insulated gate field effect transistors, and a first wiring contact region connected to the first wiring contact region in a channel length direction. And the second
A third wiring contact region connected in the channel width direction to a third wiring contact region, wherein a corner of the second wiring contact region and a corner of the third wiring contact region are chamfered. A semiconductor device, characterized in that: