KR900017195A - Semiconductor devices - Google Patents

Semiconductor devices Download PDF

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KR900017195A
KR900017195A KR1019900005234A KR900005234A KR900017195A KR 900017195 A KR900017195 A KR 900017195A KR 1019900005234 A KR1019900005234 A KR 1019900005234A KR 900005234 A KR900005234 A KR 900005234A KR 900017195 A KR900017195 A KR 900017195A
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South Korea
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semiconductor device
transistor
gate
gate electrode
transistors
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KR1019900005234A
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Korean (ko)
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KR0184262B1 (en
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다까시 사꾸다
야스히로 오꾸찌
까즈히꼬 오오까와
야스히사 히라바야시
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야마무라 가쯔미
세이꼬 엡슨 가부시끼가이샤
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits
    • H01L27/11803Masterslice integrated circuits using field effect technology
    • H01L27/11807CMOS gate arrays

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

반도체 장치Semiconductor devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 제1실시예에 게이트 분리형 유니트 장치의 어레이를 도시한 다어그램,1 is a diagram showing an array of gate detachable unit devices in a first embodiment of the present invention;

제2도는 제1도의 유니트 장치를 확대한 평면도,2 is an enlarged plan view of the unit apparatus of FIG. 1;

제3A도는 제2도에서 선 (A-A')을 따라 취해진 유니트 장치의 단면도.3A is a cross-sectional view of the unit device taken along line A-A 'in FIG.

Claims (13)

다수의 배열된 유니트 반도체 장치를 포함하는 반도테장치로서, 상기 반도체장치내의 상기 유니트 반도체장치 및 소자는 와이어에 의해 서로 선택적으로 접속되어, 바람직한 논리회로를 구성하는 반도체장치에 있어서, 상기 유니트 반도체장치는 제1도전형의 적어도 하나의 제1 절연-게이트형 전계효과트랜지스터 및 제2전도형의 제2절연-게이트형 전계효과 트랜지스터를 포함하며, 상기 제2절연-게이트형 전게효과 트랜지스터는 상기 제1트랜지스터에 인접 배치되고, 제1트랜지스터의 게이트 전극으로 부터 분리 게이트 전극을 가지며, 각 트랜지스터의 상기 게이트 전극은 서로 인접한 측면에서 적어도 하나의 게이트 단자부를 가지며, 제1전계효과 트랜지스터의 상기 게이트 단자부가 적어도 하나의 제1와이어 접속부 및 제2와이어 접속부를 갖는 것을 특징으로 하는 반도체 장치.A semiconductor device comprising a plurality of arranged unit semiconductor devices, wherein the unit semiconductor device and the elements in the semiconductor device are selectively connected to each other by a wire, so as to constitute a preferable logic circuit, wherein the unit semiconductor device And at least one first insulated-gate field effect transistor of a first conductivity type and a second insulated-gate field effect transistor of a second conductivity type, wherein the second insulated-gate type field effect transistor comprises: Disposed adjacent to one transistor, having a separate gate electrode from a gate electrode of the first transistor, wherein the gate electrode of each transistor has at least one gate terminal portion at a side adjacent to each other, and the gate terminal portion of the first field effect transistor Having at least one first wire connection and a second wire connection The semiconductor device according to claim. 제1항의 반도체장치에 있어서, 상기 제1 및 2트랜지스터의 상기 게이트 단자부가 상기 게이트 전극에 완전하게 접속되고, 각각 상기 게이트 전극의 동일한 층으로 형성되는 반도체장치.The semiconductor device according to claim 1, wherein the gate terminal portions of the first and second transistors are completely connected to the gate electrode, and are each formed of the same layer of the gate electrode. 제2항의 반도체장치에 있어서, 상기 제1 및 제2트랜지스터가 동일한 방향으로 향해져 있는 채널 영역을 갖는 반도체장치.3. The semiconductor device of claim 2, wherein the semiconductor device has a channel region in which the first and second transistors face in the same direction. 제3항의 반도체장치에 있어서, 제1 및 제2트랜지스터의 상기 게이트 전극이 상기 트랜지스터의 소스 또는 드레인영역과는 다른 영역내에 형성되고, 상기 게이트 전극보다 넓게 디자인된 상기 게이트 단자부를 갖추고 있는 반도체장치.4. The semiconductor device according to claim 3, wherein the gate electrodes of the first and second transistors are formed in regions different from the source or drain regions of the transistor and have the gate terminal portion designed wider than the gate electrode. 제4항의 반도체장치에 있어서, 제1트랜지스터의 상기 제1와이어 접속부 및 제2트랜지스터의 상기 게이트 단자부가 각각 제1 및 2평행 그리드선상에 배열되고, 상기 제1 및 제2그리드 선이 차후 배열될 상기 와이어를 따라 취해질 루트에 의해 한정되는 다수의 측선 및 세로선내에 포함되는 반도체장치.The semiconductor device according to claim 4, wherein the first wire connection portion of the first transistor and the gate terminal portion of the second transistor are arranged on first and second parallel grid lines, respectively, and the first and second grid lines are subsequently arranged. And a semiconductor device included in a plurality of side and vertical lines defined by a route to be taken along the wire. 제5항의 반도체장치에 있어서, 제1트랜지스터의 게이트 단자부의 상기 제1 및 제2와이어 접속부가 각각 제3 및 제4그리드선상에 배열되며, 상기 제3 및 제4그리드선이 상기 제1 및 제2그리더선에 수직인 반도체장치.6. The semiconductor device of claim 5, wherein the first and second wire connecting portions of the gate terminal portion of the first transistor are arranged on third and fourth grid lines, respectively, and the third and fourth grid lines are arranged on the first and fourth grid lines. 2 A semiconductor device perpendicular to the grid line. 제5항의 반도체장치에 있어서, 제1트랜지스터의 게이트 단자부의 상기 제1 및 2와이어 접속부가 상기 제1 및 2그리드선에 수직인 제3 그리드선상에 배열되는 반도체장치.The semiconductor device according to claim 5, wherein the first and second wire connecting portions of the gate terminal portion of the first transistor are arranged on a third grid line perpendicular to the first and second grid lines. 제7항의 반도체장치에 있어서, 상기 유니트 반도체장치가 상기 제1 트랜지스터의 것과 공통인 소스 또는 드레인 영역 및 상기 제1트랜지스터의 게이트 전극에 평행하게 배열된 게이트 전극을 가진 제1도전형외 제3절연-게이트형 전계효과트랜지스터 및 상기 제2트랜지스터의 것과 공통인 소스 또는 드레인 영역 및 상기 제2트랜지스터의 게이트 전극에 평행하게 배열된 게이트 전극을 가진 제2도전형 의 제4절연-게이트형 전계효과 트랜지스터를 포함하며, 더우기 상기 유니트 반도체 장치가 상기 제1, 2, 3 및 4트랜지스터의 제1, 2, 3 및 4게이트 전극에 의해 둘러싸인 영역내에 헝성된 와이어 접합 영역을 포함하는 반도체장치.The semiconductor device of claim 7, wherein the unit semiconductor device has a source or drain region common to that of the first transistor, and a first non-conductive type third insulator having a gate electrode arranged in parallel with a gate electrode of the first transistor. A fourth insulated-gate field effect transistor of a second conductivity type having a source or drain region common to that of the gate type field effect transistor and the second transistor, and a gate electrode arranged parallel to the gate electrode of the second transistor, is provided. And further comprising a wire junction region formed in an area surrounded by the first, second, third and fourth gate electrodes of the first, second, third and fourth transistors. 제8항의 반도체장치에 있어서, 상기 와이어 접합 영역이 상기 게이트 전극의 동일한 층으로 형성되는 반도체장치.The semiconductor device according to claim 8, wherein the wire junction region is formed of the same layer of the gate electrode. 제6항의 반도체장치에 있어서, 제1트랜지스터의 상기 게이트 단자부가 거의 크랭크형인 반도체장치.The semiconductor device according to claim 6, wherein the gate terminal portion of the first transistor is substantially crank-type. 제9항의 반도체장치에 있어서, 제1트랜지스터의 상기 게이트 단자부가 거의 장방형인 반도체장치.The semiconductor device according to claim 9, wherein the gate terminal portion of the first transistor is substantially rectangular. 다수로 배열된 유니트 반도체장치를 포함하는 반도체장치, 즉 상기 반도체장치내의 상기 유니트 반도체장치 및 소자가 바람직한 논리 회로를 구성하도록 와이어에 의해 서로 선택적으로 접속되는 반도체장치에 있어서, 상기 각 유니트 반도체장치가 제1도전형의 제1 및 제2절연게이트형 전계효과 트랜지스터 및 제2도전형의 제3 및 절연게이트형 전계효과 트랜지스터를 포함하는데, 상기 제1 및 2트랜지스터는 서로 평행하게 배열된 게이트 전극을 갖추고 있으며, 상기 제3 및 4트랜지스터는 서로 평행하게 배열된 게이트 전극을 갖추고 있고, 상기 각 트랜지스터가 다른 한 트랜지스터에 인접한 측면에 게이트 단자부를 갖추고 있으며, 제1트랜지스터의 게이트 전극의 상기 게이트 단자부가 상기 게이트 전극의 단부에 완전하게 형성된 적어도 하나의 제1와이어 접속부 및 상기 와이어 접속부로 부터 연장되어 제3 및 4트랜지스터외 게이트 전극의 상기 게이트 단자 부분 사이에 위치한 제2와이어 접속부를 포함하는 것을 특징으로 하는 반도체장치.A semiconductor device comprising a plurality of unit semiconductor devices arranged in a plurality, that is, a semiconductor device in which the unit semiconductor device and the elements in the semiconductor device are selectively connected to each other by wires so as to constitute a desired logic circuit, wherein each unit semiconductor device is The first and second insulated gate field effect transistors of the first conductivity type and the third and insulated gate type field effect transistors of the second conductivity type include the gate electrodes arranged in parallel with each other. And the third and fourth transistors have gate electrodes arranged in parallel with each other, each transistor has a gate terminal portion on a side adjacent to the other transistor, and the gate terminal portion of the gate electrode of the first transistor is At least one first formed completely at an end of the gate electrode Following connection, and semiconductor device characterized in that it extends from the wire connecting portion and a second wire connection portion located between the third and fourth outer gate transistor wherein the gate terminal portions of the electrodes. 다수로 배열된 유니트 반도체장치를포함하는 반도체장치, 즉 상기 반도체 장치내의 상기 유니트 반도체장치 및 소자가 바람직한 논리회로를 구성하도록 와이어에 의해 서로 선택적으로 접속되는 반도체장치에 있어서, 상기 각 유니트 반도체장치가 제1도전형의 제1 및 제2절연 게이트형 전계효과 트랜지스터 및 제2도전형의 제3 및 제4절연 게이트형 전계효과 트랜지스터를 포함하는데, 상기 제1 및 제2트랜지스터가 서로 평행하게 배열된 게이트 전극을 갖추고 있으며, 상기 제3 및 4트랜지스터가 서로 팽행하게 배열된 게이트 전극을 갖추고 있고, 상기 각 트랜지스터가 다른 한 트랜지스터에 인접한 측면에 게이트 전극의 게이트 단자부를 갖추고 있고, 재1 및 제2트랜지스터에 게이트 전극의 상기 게이트 단자부가 적어도 하나의 제1 및 제2와이어 접속부를 포함하며, 와이어 접합 영역이 상기 제1,2,3 및 4트랜지스터의 게이트 전극에 둘러싸인 영역내에 헝성되는 것을 특징으로 하는 반도체장치.A semiconductor device comprising a plurality of unit semiconductor devices arranged in a plurality, that is, a semiconductor device in which the unit semiconductor device and the elements in the semiconductor device are selectively connected to each other by wires so as to constitute a desired logic circuit, wherein each unit semiconductor device is First and second insulated gate field effect transistors of the first conductivity type and third and fourth insulated gate type field effect transistors of the second conductivity type, wherein the first and second transistors are arranged in parallel with each other. A gate electrode having a gate electrode arranged such that the third and fourth transistors are arranged parallel to each other, each transistor having a gate terminal portion of the gate electrode on a side adjacent to the other transistor, and a first and second transistors At least one first and second wire connection of the gate terminal portion of the gate electrode to Including, to the wire bonding area, the semiconductor device characterized in that the heongseong in the area surrounded by the gate electrode of the first, second, and third and fourth transistors. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900005234A 1989-04-19 1990-04-16 Semiconductor device KR0184262B1 (en)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
JP125839 1980-09-10
JP99130 1987-04-22
JP89-99130 1989-04-19
JP9913089 1989-04-19
JP89-125839 1989-05-19
JP12583989 1989-05-19
JP02027785A JP3092133B2 (en) 1989-04-19 1990-02-07 Semiconductor device
JP90-27785 1990-02-07
JP27785 1990-02-07

Publications (2)

Publication Number Publication Date
KR900017195A true KR900017195A (en) 1990-11-15
KR0184262B1 KR0184262B1 (en) 1999-03-20

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Application Number Title Priority Date Filing Date
KR1019900005234A KR0184262B1 (en) 1989-04-19 1990-04-16 Semiconductor device

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JP (1) JP3092133B2 (en)
KR (1) KR0184262B1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2694920B1 (en) * 1992-08-20 1994-10-28 Oreal Device for keeping at least two products separated from each other and for mixing them at a desired time.

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KR0184262B1 (en) 1999-03-20
JPH0372678A (en) 1991-03-27
JP3092133B2 (en) 2000-09-25

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