KR0184262B1 - Semiconductor device - Google Patents

Abstract

The semiconductor device of the present invention has a plurality of arranged unit semiconductor devices designed to constitute a desired logic circuit by selectively connecting between elements of a unit semiconductor device and between the unit semiconductor devices. Each of the unit semiconductor devices includes at least a first insulated gate field effect transistor of a first conductivity type, and a second conductivity provided adjacent to the first transistor and having a gate electrode away from the gate electrode of the first transistor. And a second insulated gate field effect transistor of a type. The gate electrode of each transistor has at least a gate terminal portion adjacent to each other, and the gate terminal portion of the first field effect transistor has at least a first wire connection portion and a second wire connection portion. By using the second wire connecting portion, the wiring in the unit semiconductor device can be performed through the shortest aluminum wiring of the first layer, and thus the ease of wiring can be improved.

Description

Semiconductor devices

1 shows an array of gate detachable unit devices of a first embodiment of the present invention.

2 is an enlarged plan view of the unit device of FIG.

FIG. 3a is a sectional view of the unit apparatus taken along line A-A in FIG.

3b is a cross-sectional view of the unit apparatus taken along line B-B in FIG.

4 is a layout view of the gate detachable unit device of FIG.

FIG. 5 is a view showing a wiring scheme between gates located laterally adjacent to each other in the gate detachable unit device of FIG.

FIG. 6 is a view showing diagonal wiring between adjacent gates in the gate detachable unit device of FIG.

7 is a plan view of a D flip-flop constructed by the two unit apparatus of the first embodiment of the present invention.

8 shows an array of gate detachable unit devices of a second embodiment of the present invention.

9 is an enlarged plan view of the unit apparatus of FIG. 8;

FIG. 10 is a layout view of the gate detachable unit apparatus of FIG.

FIG. 11 is a diagram illustrating a wiring scheme between gates located laterally adjacent to each other in the gate detachable unit apparatus of FIG.

FIG. 12 is a view showing different wiring schemes between gates which are laterally adjacent to each other in the gate-separable unit device of FIG. 9, and where a second wire connection is not provided.

FIG. 13 is a view illustrating a wiring method between gates diagonally positioned in the gate detachable unit device of FIG.

14 is a plan view of a D flip-flop constructed by the two unit devices of the second embodiment of the present invention.

Fig. 15 is a schematic plan view showing the internal structure of a semiconductor chip of a conventional channelless gate array.

FIG. 16 shows an array of gate detachable unit devices of FIG.

17 is a circuit diagram of the unit apparatus of FIG.

18 is an enlarged plan view of the unit apparatus of FIG.

FIG. 19 shows an example of wiring between gates located laterally adjacent to each other in the unit apparatus of FIG.

FIG. 20 shows an example of wiring between gates diagonally located in the unit apparatus of FIG.

21 is a circuit diagram of a D flip-flop constructed by a MOSFET.

FIG. 22 shows an example of wiring between the two unit devices of FIG. 15 for constructing a D flip-flop. FIG.

* Explanation of symbols for main parts of the drawings

F _P1 , F _P2 : P channel MOSFET F _N1 , F _N2 : N channel MOSFET

6, 7: N-type and P-type diffusion region 8, 9: stopper

3: P type well T ₁ , T ₁ , T ₁ , T ₂ , T ₂ , T ₂ ,: gate terminal

g: gate electrode

Field of Invention

The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device having a densely located gate array having a plurality of unit semiconductor devices of gate-separated insulated gate field effect transistors with improved gate structure.

[Related Technologies]

Conventional semiconductor chips of channelless gate array type have an internal arrangement as shown in FIG. It is provided on the silicon chip substrate 1 which has the some input / output buffer part B provided along the area | region. 16 is an enlarged view of a portion of the matrix. In this type of gate array, insulated gate field effect transistors of the same unit device are connected to each other, or transistors belonging to different unit devices are connected by first and / or second layers of aluminum wire provided on the gate array. Thus, the desired large-scale logic circuit can be obtained.

17 is a block diagram of a unit device of a gate separation type. The unit device 2 is composed of two pairs of gate-separated complementary insulated gate field effect transistors 2a and 2b (hereinafter referred to as CMOSFETs). The gates G of these CMOSFETs are independent of each other, but FETs of the same conductivity type have a common drain D or source S. FIG. 18 shows a conventional structure of the gate detachable unit device 2. As shown in this figure, an N-type substrate is formed together with the rectangular region of the P-type well 3 formed by diffusing P-type impurities into the substrate.

Polysilicon gates 4N and 5N are formed in the P type well 3 through the gate oxide film so as to be symmetrical with each other across the P type well.

Adjacent to the P-type well 3, another pair of polysilicon gates 4P and 5P is formed at a position in which the gates 4N and 5N are moved in parallel in the channel width direction. A strongly diffused N-type region 6 is formed in a self-aligned manner by ion implanting N-type impurities into the P-type well using the pair of polysilicon gates 4N and 5N. Similarly, a strongly diffused P-type region 7 is formed in a self-aligning manner by ion implanting P-type impurities into the N-type substrate using the pair of polysilicon gates 4P and 5P. In addition, a strongly doped P-type stopper 8 is provided adjacent to the N-type region 6 by diffusion in order to supply the voltage VDD to the N-type substrate, and a heavily doped N-type stopper ( 9) is provided adjacent to the P-type region 7, wherein the stopper 9 is for supplying a voltage VSS to the P-type well.

Each of the polysilicon gates 4N, 5N, 4P, 5P has a narrow gate electrode portion g and a longitudinal gate output terminal portion T ₁ and T ₂ extending from both ends of the electrode portion g. It is U-shaped structure provided with). The region immediately below each gate electrode portion g functions as a channel. The region located in the strongly diffused N-type region 6 between the gate electrode portions g provided in parallel serves as a common drain region or source region of the two N-channel MOSFETs. Similarly, the common drain region or source region of the two P channel MOSFETs is located between the parallelly installed gate electrode portions g of the strongly diffused P-type region 7.

As shown in FIG. 19, in the gate array of the gate-separated unit device 2, adjacent CMOSFETs of the same unit device, the gate output terminal portions T ₁ , T ₂ are indicated by contact holes (X in the figure). Are wired between the gates arranged opposite to each other so as to be connected via the aluminum wire l ₁ (shown in straight lines) of the first layer, wherein the first layer is located on the gate, The shortest wire connection between adjacent CMOSFETs can be obtained. In the same unit arrangement, diagonal wire connection between the terminal portions T ₁ , T ₂ can be obtained as shown in FIG. 20, wherein a pair of diagonally positioned terminal portions T ₁ , T _{2 form} a contact hole. It is connected by the aluminum wire ₁₁ of the 1st layer through. On the other hand, another pair of diagonally positioned terminal portions T ₁ , T ₂ are connected to the first layer of aluminum wire l ₁₂ , l ₁₃ and the first layer laid on the first layer via contact holes and connecting portions marked 0. It is connected by the two-layered aluminum wire l ₂ (indicated by a double straight line). The detachable unit device has the advantage that it can be easily modified to the common gated unit device by the wiring as shown in FIG. 19, and as shown in FIG. 20, which is not applicable to the common gated unit device. It has the advantage that it can be applied by diagonal wiring. In particular, the applicability of the diagonal wiring is useful for constructing a functional device such as a transmission gate.

However, diagonal wiring requires a second or more layered aluminum wire if the wire length should be as short as possible. When the second layered aluminum wire 12 is arranged for connection between elements of the unit device, the area occupied by these second layer wires is connected between the functional unit device and the input / output between the functional unit device located far from each other. It cannot be used to arrange other wires for connection between buffers, so these areas are called wire prohibited tracks. Thus, the outer wiring feasibility (defined as wiring between remotely located functional unit devices, and ease of wiring between the unit device and the input / output buffer) is defined as a second or more layer of internal wire. It decreases as the number or area of n increases. For example, the D flip-flop shown in FIG. 21 may be constituted by two unit devices 2. In this case, the wire inhibiting track occurs on the aluminum of the second layer shown in FIG. 22 due to the diagonal wiring between the internal elements, thereby reducing the possibility of external wiring.

Of course, the two unit devices may be connected without using the second layer aluminum wire. In this case, however, the aluminum wires of the first layer must be arranged so that they do not cross each other, which means that the overall wire length becomes long, and thus the area occupied by such long wires becomes wide. Accordingly, the possibility of internal wiring (defined by the ease of wiring between elements of each unit device and wiring between adjacent unit devices) is reduced. As the first layer wire becomes more complicated and longer, the wire resistance and the wire capacitance caused by the increase in the wiring area are increased, and thus the wire time constant is also increased. This results in a significant amount of delay in device operation.

[Overview of invention]

Accordingly, an object of the present invention is to provide a gate-separated unit semiconductor device designed to improve the gate shape so that adjacent gates of the gate-separated unit semiconductor device can be diagonally wired using only the first layer wire without increasing the wire length. To provide.

Another object of the present invention is to provide a semiconductor device having a gate array of a plurality of unit semiconductor devices having a gate of an improved shape in order to improve not only external wiring possibilities but also internal wiring possibilities.

In order to achieve the above object and other objects, according to the present invention, there is provided a semiconductor device having a plurality of unit semiconductor devices arranged on a semiconductor substrate, and these unit semiconductor devices have the same unit device to constitute a desired logic circuit. Are designed to selectively connect between devices and unit devices, wherein the unit semiconductor device comprises at least a first insulated gate field effect transistor of a first conductivity type and a second insulated gate field effect transistor of a second conductivity type. Each gate electrode of the two kinds of transistors has a gate terminal portion formed at an end facing the other gate electrode, and the first insulated gate field effect transistor includes a gate electrode portion and the gate electrode terminal portion. Has a gate electrode, before the gate The pole terminal portion is characterized by having at least a first wire connecting portion and a second wire connecting portion.

Each gate electrode is typically made of polysilicon, taking into account the self-alignment formation of the source or drain regions. The remaining region of the semiconductor substrate which does not substantially contribute to the formation of the channel inversion layer is used as a place where the gate terminal portion of the gate electrode is provided. The gate terminal portion may be a layer deposited on the layer of the gate electrode, but requires another process in addition to the gate electrode forming process. Therefore, it is preferable to form the gate terminal portion on the same layer of the gate electrode as the gate electrode is formed.

The general semiconductor device of the master slice arrangement is provided with a gate electrode designed to have a shape of short channel length and wide channel width in order to reduce on-resistance value. On the other hand, an automatic wiring process is used to connect the elements of the unit device and the unit devices, wherein the wires are arranged along the length and lateral direction of the grid, and thus the first and second insulated gate field effects The transistors need to be arranged such that the channel regions (gate electrodes) of each transistor are directed in the same direction or in the longitudinal or lateral direction of the grid. The channel region of each transistor may be provided between the same vertical lines or side lines of the grid, or may be provided in adjacent parallel grid lines, respectively.

As mentioned above, the gate terminal portion is formed on a region other than the source or drain region, and the gate electrode portion is usually narrow in shape. Gate terminal portions formed at both ends of the gate electrode are wider in the channel length direction than the gate electrode. In this case, the gate terminal portion is generally designed to have a minimum area of 1 square grid.

In a preferred embodiment of the present invention, the first insulated gate field effect transistor has a crank type gate terminal portion, wherein each gate terminal portion is positioned adjacent to the gate electrode in such a manner as to form a crank shape. It has a 1st wire connection part and the 2nd wire connection part extended from this 1st wire connection part. The crank terminal portion may have a connecting portion between the first and second wire connecting portions, and the third connecting portion may be another wire connecting portion as necessary.

In another preferred embodiment of the present invention, the gate terminal portion of the first insulated gate field effect transistor is formed in a long direction, wherein the first terminal portion is located adjacent one end of the gate electrode and the second terminal portion It extends from the outer edge of the said 1st terminal part. The gate terminal portion of this shape occupies at least two grid areas. In this kind of gate terminal portion, the first wire connecting portion is used to be connected to wires arranged along grid lines in the longitudinal direction and the lateral direction, respectively. The second terminal portion is also used to connect to the wires in the longitudinal and lateral directions, all of which are identical to one of the wires that can be connected to the first terminal portion. On the other hand, in the case of the crank terminal part, the wire that can be connected to the first terminal part is different from the wire that can be connected to the second terminal part.

It is clear that the internal and external wiring possibilities are improved depending on the number of wires that can be connected with the gate terminal portion. However, as the number of wires increases, the area of the gate terminal portion increases, and thus device integrity of the semiconductor device may decrease. In the automatic wiring of the gate terminal portion, wires are arranged along grid lines in the longitudinal direction and in the lateral direction. It is therefore desirable if the gate terminal portions are designed to be connected to wires of different grid lines. Therefore, in a preferred embodiment of the present invention, a semiconductor device in which a longitudinal gate terminal portion is formed on one side of a gate electrode of a unit semiconductor device is provided, wherein a wire junction is provided in an area surrounded by four gate terminal portions. Each wire junction is characterized by having an area of at least three grids. It is preferable that the wire joint is formed on the same layer of the gate electrode by polysilicon or the like.

According to the present invention, each gate terminal portion includes not only the first wire connecting portion but also the second wire connecting portion. For example, the second connection part may be used to connect the wire of the first layer through the contact hole, and thus the wire length may be reduced as compared with the case of using only the first connection part for wiring. The unit device can thus be connected diagonally using only the wires of the first layer in such a way that the wire length is not increased, as described previously. By this short wiring, the delay time caused by the wiring is reduced, and the possibility of internal wiring is improved. Also, since the second connection can be used for the passage of the wire of the first layer, fewer wires of the second layer are required and the number of wire inhibiting tracks is reduced, thereby reducing the possibility of external wiring. Is improved.

In the case where the gate terminal portions are crank type, diagonal wiring between the gate terminal portions can be achieved by using only the wire of the first layer arranged in the region on the adjacent gate terminal portion.

On the other hand, when the gate terminal portion is long and the wire junction is provided, diagonal wiring between the gates is performed by connecting the wires of the first layer to both ends of the wire junction through a contact hole, The other wires of the first layer can be arranged to pass through the middle of the wire bond. According to this arrangement, the wires of the first layer necessary for the diagonal arrangement do not protrude onto the source region or the drain region. In addition, when the adjacent gate terminal portions are connected, a space may be formed between the wire connection gate terminal portions. This space can be used to arrange the other wires of the first layer.

The above and other objects and advantages of the present invention will become apparent from the following detailed description of the accompanying drawings.

[Preferred Embodiments of the Invention]

While the invention has been described in conjunction with the preferred embodiments, it will be appreciated that the invention is not intended to be limited to these embodiments. On the contrary, the invention is intended to cover all modifications, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the claims.

1 and 4 illustrate a first embodiment of the present invention. As shown by these figures, a plurality of gate-separated unit semiconductor devices 12 are arranged along the longitudinal direction and the lateral direction at equal intervals to form a matrix of unit devices. Each unit device 12 comprises a pair of N channel MOSFETs F _N1 , F _N2 arranged parallel to each other, and a pair of P channels arranged parallel to each other and located adjacent to each N channel MOSFET It has a planar structure having MOSFETs F _P1 and F _P2 . In the region where the N-channel MOSFET is formed, the P-type well 3 in the square region is provided by diffusing the P-type impurity onto the N-type silicon substrate 20 having the low concentration impurity. A pair of polysilicon gates 14N and 15N are formed parallel to each other on the P-type well 3 via the gate oxide film 13. The high concentration N-type diffusion region 6 is formed in a self-aligned manner by ion implantation of N-type impurities using the polysilicon gates 14N and 15N as a mask, and this region 6 is a source region or a drain region. to be. Adjacent to the high concentration diffusion region, a high concentration P-type stopper 8 is formed by diffusion, which is used to supply voltage Vss to the P-type well 3. In addition, an oxide film 10 is partially deposited thickly on the P-type well 3. Similarly, in the region where the P-channel MOSFETs F _P1 and F _P2 are formed, a pair of polysilicon formed adjacent to the P-type well 3 via the gate oxide film 13 and parallel to each other on the substrate is formed. Gates 14P and 15P are provided. A high concentration P-type diffusion region 7 is formed by self-alignment by ion implantation of P-type impurities using the polysilicon gates 14P and 15P as a mask, and this region 7 is a source region or a drain. Area. Adjacent to the high concentration diffusion region, a high concentration P-type stopper 9 is formed by diffusion, and the stopper is used to supply the voltage V _DD to the N-type substrate 20. In addition, an oxide film 10 is partially deposited thickly on the P-type well 3.

The polysilicon gates 14P and 15P are formed to be substantially flat U-shaped and arranged symmetrically. As shown in FIG. 4, each of the polysilicon gates 14P and 15P is integrally connected to both narrow gate electrodes g of 4 grid lengths and both ends of the gate electrodes g, and is square. Square gate terminal portions T ₁ and T ₂ having an area of one grid are provided. The gate terminal portions T ₁ , T ₂ have an area sufficient for a single wire connection, that is, a sufficient area made through a single contact hole to form a resistance contact. The area immediately below the gate electrodes g, g, which are one grid distance from each other, is for a four grid wide channel region. Among these, the region between the gate electrodes g and g of the high concentration N-type diffusion region 7 is used as a common source or drain region of two P-channel MOSFETs. These drain regions or source regions of the P-channel MOSFET have four wire connections arranged in the channel width direction. The stopper 9 has two wire connecting portions arranged in the same direction.

The polysilicon gates 14N and 15N are formed at positions where the polysilicon gates 14P and 15P are laterally moved by a predetermined distance. The gates 14N and 15N have a different shape than the gates 14P and 15P, that is, the gate 14N is part of the same shape as the gate 14P and integrally added to this part, It has the part shown by the diagonal line in FIG. In other words, the gate 14N is a narrow gate electrode portion g having a length of approximately 4 grids, and a crank type gate terminal portion T ₁ ′ and T ₂ ′ integrally connected to both ends of the gate electrode portion g. ). The terminal portion T ₁ ′ adjacent to the gate 14P includes a first wire connecting portion t ₁ of a square 1 grad corresponding to the terminal portion T ₁ of the gate 14P, and the first terminal portion t _1. A second wire connecting portion t ₂ of a square 1 grid extending in a channel length direction from the cross-section, and extending from the connecting portion t _{2 in} the channel width direction toward the gate 14P, A third wire connection t ₃ of a square 1 grid located adjacent to the terminal portion T ₁ . From the terminal portion (T ₁ ') opposite the terminal portion of the (T _2') is a terminal portion (T ₂₎ m first wire connecting portion of the first grid (t ₁₎ corresponding to the first terminal portion (t ₁₎ of the gate (14P) It includes a square third wire connecting portion of the first grid (t ₃₎ extends in the second wire connecting portion (t ₂₎ and the channel from the terminal (t ₂₎ in the width direction of the first grid square extending in the channel length direction. The second and third wire connections t ₂ , t ₃ , indicated by oblique lines in FIG. 4, are located on the same grid line on which the stoppers 8, 9 are located. The gate 14N itself has a symmetrical form in the channel width direction with respect to the line passing through the center thereof. The gate 15N is provided with a terminal portion T ₁ adjacent to the gate 15P, which is the first wire of a square 1 grid corresponding to the terminal portion T ₁ of the gate 15P. A connecting portion t ₁ , a second wire connecting portion t 2 ′ of a square 1 grid extending from the first terminal portion t _{1 in the} channel length direction, and from the second terminal portion t 2 ′ toward the gate 14P. The third wire connecting portion t ₃ ′ of the square 1 grid extends in the channel width direction and is positioned between the terminal portions T ₂ of the respective gates 14P and 15P. The terminal portion (T ₂₎ is m the first wire connecting portion of the first grid (t _1), the first wire connecting portion corresponding to the terminal portion (T ₂₎ of the gate (15P) that it faces the terminal portion (T ₁₎ ( the second wire connection t ₂ ′ of the square grid extending from t _{1 in the} channel length direction, and the third wire connection t ₃ of the square 1 grid extending outward in the channel width direction from this connection t2 ′. '). The second and third wire connections t ₂ ′, t ₃ ′, shown diagonally in FIG. 4, are located on the grid line between the parallel gates g, g. The gate 15N itself has a symmetrical shape in the channel width direction with respect to the line passing through the center. Further, the wire connections t ₂ ′, t ₃ ′ of the gate 15N are formed to have a chamfered shape of the wire connections t ₂ , t ₃ .

The terminal portions T ₂ and T ₂ of the gates 14P and 15P may be connected to the terminal portions T ₁ ′ and T ₂ in two wiring schemes described below as illustrated in FIG. 5. The first wiring scheme is connected to the terminal portions T ₁ ′, T ₂ ′ through the contact holes (shown as 'X') by the aluminum wire l _1Y of the first layer arranged along the Y grid direction. That's how. Another wiring scheme is through the contact hole (shown as 'X') by the aluminum wire l _1Y of the first layer in which the terminal portions T ₂ , T ₂ are arranged in the X grid direction perpendicular to the Y grid direction. The third connection part t _{3 is} connected to the terminal parts T ₁ ′ and T ₁ . Thus, when a pair of adjacent gate-separated CMOSFETs of the same unit device are connected to each other to form a common gate, two shortest wiring schemes can be obtained by using only the first layer of wire having one grid length. This means that the wiring possibilities are greatly improved compared to the conventional apparatus. The space occupied by the unit device 12 of this embodiment is a space of four grid lengths in the X direction and 12 grid widths in the Y direction, and therefore is the same as the space of the conventional unit device in FIG. The unit apparatus of the present embodiment has the gates 14N, shown in diagonal lines in FIG. 4, located in unused areas of grid lines where stoppers 8, 9 are located and unused areas of grid lines where common areas of the source or drain are located. The second and third wire connecting portions t ₂ , t ₃ , t ₂ ′, t ₄ are added to 15N. Therefore, in this embodiment, an increase in the area of the unit apparatus can be avoided.

Next, diagonal wiring of the gate of the unit device 12 can be executed as shown in FIG. 6, where the terminal portion T ₂ of the gate 14P is connected to the terminal portion T ₁ . The terminal portion T ₂ of the gate 15P is connected to the terminal portion T ₁ of the gate 14N. In the diagonal wiring shown, the terminal portion T ₂ is formed at the third wire connecting portion t3 'by the aluminum wire l _1Y of the first layer arranged along the longitudinal grid line (X grid direction). It is connected to an adjacent terminal portion T ₁ of the gate 15N, and the terminal portion T ₂ of the gate 15P is in this order on the first and second wire connecting portions l _1Y of the terminal portion T ₁ ′. It is connected to the terminal portion T ₁ ′ of the gate 14N at the first wire connecting portion t ₁ by a wire l _1Y to the aluminum of the first layer arranged to pass therethrough. In the present embodiment, the space of three grid lengths in the X direction and the two grid widths in the Y direction includes the terminal portions T ₂ of the respective gates 14P and 15P, the terminal portions T ₁ of the gate 15N, and Is defined by the first wire connecting portion t ₁ of the terminal portions T ₁ and T ₁ ′ of the gates 15N and 14N of the gates, wherein diagonal wirings between the gates are located on the first aluminum layer in this space. It can be performed by the aluminum wire of the first layer without using the aluminum wire of the second layer. The advantage obtained by using only the first aluminum layer is that wire inhibiting tracks that may occur due to the use of the second aluminum layer are avoided, contributing to the improvement of the external wiring possibilities. As shown in FIG. 20, according to the conventional wiring, the wires should be arranged in such a manner as to arrange other wires on one wire in a direction facing the aluminum wires (l ₁₂ , l ₁₃ ) of the first and second layers. A wire such as wire l _1Y must be arranged on the gate electrode g, so that the wire cannot be arranged in a space having three grid lengths and two grid widths. In contrast to this, according to the present embodiment, the aluminum wire of the second layer does not need to be used, and the wiring length can be reduced because the wires do not cross the gate electrode g. Therefore, the capacitance and resistance caused by the wiring can be reduced at the same time, and thus the delay time caused by the wiring can be reduced as well as the possibility of internal wiring can be improved.

FIG. 7 shows a D flip flop constituted by the two unit semiconductor devices of this embodiment, which is the same as that of FIG. It should be noted that in FIG. 7 the wiring length is greatly reduced and no inhibiting track of the second wire is generated. Terminal portions T ₁ ′, T ₂ ′, T ₁ , T ₂ of the respective gates 14N, 15N are all provided with second and third wire connections. Further, as is apparent from the wiring shown in FIG. 6, the unit devices without the terminal portions T ₁ ′, T ₂ ′, T _{2 of the} respective gates 14N, 15N are internal and in comparison with those of the conventional unit devices. It can be used to improve the possibility of external wiring.

8 to 10 illustrate another embodiment of the present invention, in which elements corresponding to the embodiment are denoted by the same reference numerals. As shown in FIG. 8, a plurality of unit semiconductor devices 22 are arranged to form a matrix. Each unit semiconductor device 22 is shown in FIG. The unit semiconductor device 22 includes a pair of parallel N-channel MOSFETs F _N1 and F _N2 , and a pair of parallel P-channels F _N1 and F _N2 . The N-channel MOSFETs have polysilicon gates 24N and 25N, respectively, and these gates are flat U-shape and are arranged symmetrically with each other. As shown in FIG. 10, each of the polysilicon gates 14N and 15N is integrally connected to both narrow gate electrode portions g of approximately four grid lengths and both ends of the gate electrode portions g. The terminal portions T ₁ and T ₂ of the square 1 grid are provided. These terminal portions T ₁ and T ₂ have a sufficient area for wiring through a single wire connecting portion, that is, a single contact hole. The gate electrode g is separated by one grid distance, and a channel region having a length of four grids is formed below it. Among them, the channel region between the parallel gate electrodes g and g of the high concentration N type diffusion region 6 is a common drain or source region of the N channel MOSFET.

On the other hand, the polysilicon gates 24P and 25P of the P-channel MOSFETs are substantially flat U-shaped, and are installed at positions where the polysilicon gates are moved laterally by a predetermined distance. The gates 24P and 25P are designed to have different shapes from the gates 24N and 25N. The gate 24P has a portion having the same shape as that of the gate 24N, and a portion indicated by an oblique line in FIG. That is, the gate 24P includes a substantially narrow gate electrode portion g having a width of 4 grids and a rectangular terminal portion T ₁₁ , T ₂₂ having a width of 2 grids. The terminal portion T ₂₂ is located adjacent to the gate 24N and also has a first wire connecting portion t1 of a square 1 grid corresponding to the terminal portion T ₂ of the gate 24N, and the first wire connecting portion. It is from (t1) formed of a second wire connecting portions (t ₁₂₎ of the first grid square extending outwardly in the channel width direction. The other terminal portion (T ₁₁₎ is in the channel width direction from the terminal part the first wire connecting portion of the square first grid corresponding to _{(T 1) (t 1)} , and the first wire connecting portion (t ₁₎ of the gate (24N) claim 2 is composed of a wire connecting portion (t ₁₂₎ of the first grid square extending outwardly.

Similarly, 25P adjacent to the gate 25N is the first wire connection t ₁ of the square 1 grid corresponding to the terminal portion T ₂ of the gate 25N, and the first wire connection t ₁ . from and has a terminal portion (T ₂₂₎ in a second wire connecting portions (t ₁₂₎ of the first grid square extending outwardly in the channel width direction. The terminal portion T ₁₁ opposite to the terminal portion T22 is a first wire connecting portion t ₁ of a 4 square 1 grid, and a square extending outwardly from the first wire connecting portion t _{1 in} the channel width direction. The second wire connecting portion T ₁₂ of one grid is provided.

By adding the second wire connecting portion T ₁₂ , the gates 24P and 25P have eight grid lengths in the channel width direction. One region is defined by the surrounding terminal portions T ₁ , T ₁ , T ₂₂ , T ₂₂ of the gates 24N, 25N, 24P, 25P, where separate wire bond regions 28 are arranged. have. The wire junction region 28 is formed at the same time as the gates are formed, and is thus formed by polysilicon doped with impurities. This wire bonding region 28 is a first wire bonding portion P ₁ between the terminal portions T ₁ , T ₂ , and a second wire bonding portion between the second wire connecting portions t ₁₂ , t ₁₂ . (P ₂ ), and the third wire bonding portion (P ₃ ) between the first wire connection positions (t ₁ , t ₁ ).

In the unit semiconductor device of the above structure, the gates 24P and 25P are connected to the adjacent gates 24N and 25N shown in FIG. 11, and at this time, the second wire connection portion (each of the gates 24P and 25P) ( t ₁₂ , t ₁₂ are the terminal portions of the gates 24N, 25N by means of aluminum wire l _1r of the first layer arranged laterally (along the Y grid direction) through contact holes marked 'X'. It is connected to (T ₁ , T ₁ ). Lateral wiring between the gates may be performed by the shortest wire, ie by one grid length wire. In addition, the first wire connections t1 and t1 remain unused, and thus are arranged in the longitudinal direction (X grid direction) through which the aluminum wire l _1r passes through the connections t ₁ and t ₂ . Can be. In contrast, if the terminal portions T ₁ , T ₁ of the gates 24P, 25P are not provided with the second wire connecting portions t ₁₂ , t ₁₂ of the square 1 grid shown in FIG. There is no space for passing the aluminum wire in the X direction between them, which means that a three grid length wire inhibiting track occurs between adjacent terminal portions of the first aluminum layer.

Next, in the unit semiconductor device 22 of the present embodiment, diagonal wiring between the gates can be executed, as shown in FIG. 13, wherein the terminal portion T ₂₂ of the gate 24P is connected to the gate. It is connected to the terminal portion (T ₁₎ of (25N) and the terminal portion of the gate (25P) (T ₂₂₎ is connected to the terminal portion (T ₁₎ of the gate (24N). As shown in FIG. 13, the terminal portion T ₂₂ of the gate 24P is connected to the wire bonding region 28 through the aluminum wire l _1r arranged in the X direction at the first wire connecting portion t ₁ . It is connected to an adjacent third wire junction P ₃ , and the wire junction region 28 is connected to the terminal portion of the gate 25N through an aluminum wire 1 arranged in the X direction at the first wire junction position P 1. (T ₁ ), the terminal portion T ₂₂ of the gate 25P is connected to the second wire junction portion P ₂ and the terminal portion T ₂₂ of the region 28 at the second wire connecting portion t ₁₂ . Is connected to the terminal portion T ₁ of the gate 24N through the aluminum wire l _1r arranged so as to pass through the second wire connecting portion t12 in this order. The aluminum wires are all wires of the first layer.

The diagonal wiring of the gates may be performed in a space having three grid lengths in the X direction and three grid widths in the Y direction using only the first aluminum layer. Compared with the unit semiconductor device 12 of FIG. 2, although the unit semiconductor device 22 is as long as 1 grid and has an increased area in the Y direction, the passage of the aluminum wire l _1r is laterally adjacent. There is an advantage that it is guaranteed between the terminal parts. Thus, according to the present embodiment, the first layer wires can be easily distributed so that improved external wiring possibilities can be obtained.

In FIG. 14, the D flip-flop in FIG. 21 constituted by two unit semiconductor devices 22 is illustrated. As can be seen from FIG. 14, the arrangement of the flip-flop is simplified, so that the overall wiring length is greatly reduced and no inhibiting track is produced in the second layer.

Gates 24P and 25P of the unit device 22 are provided with terminal portions T ₂₂ having the second wire connecting portion t ₁₂ , respectively. In addition, one of the gates 24P and 25P is provided with a terminal portion T ₂₂ having a second wire connecting portion t ₁₂ for performing diagonal wiring between the gates using only the first layer wire. This is evident from FIG. 13.

Claims (10)

A plurality of unit semiconductor devices 12 each having a first insulated gate type field effect transistor F _{P2 of} a first conductivity type and a second insulated gate type field effect transistor F _N2 of a second conductivity type are provided. A semiconductor device comprising: the unit semiconductor device and a transistor are selectively connected to each other by wires to form a desired logic circuit, wherein the first and second transistors are provided adjacent to each other, and the first transistor Has a first gate terminal portion T ₂ on the side facing the second transistor and a first gate electrode 15P having a second gate terminal portion T ₁ on the side away from the second transistor; The second transistor is on the third gate terminal portion T ₁ adjacent to the first gate terminal portion and on a side away from the first transistor. Fourth a gate terminal portion (T ₂₎ A semiconductor device having a second gate electrode (15N) which have the third and fourth gate terminal portions of the first wire connecting portion (t ₁₎ which are connected to each other integrally And a second wire connection part t ₂ ′ and a third wire connection part t ₃ ′, respectively, one of the source and drain regions of the first transistor, the first gate terminal part T ₂ , The first wire connecting portion t ₁ of the third gate terminal portion T ₁ and one of the source region and the region of the second transistor are arranged on a first straight line, and the source region of the first transistor is provided. The other of the drain region and the drain region, the second and third wire connection portions t ₂ ′, t ₃ ′ of the third and fourth gate terminal portions T ₁ and T ₂ , and a source region of the second transistor. The other one of the and drain regions The first gate terminal portion T ₂ and the third wire connection portion T ₃ ′ arranged on a second parallel straight line are perpendicular to the first and second straight lines. Are arranged on three straight lines, and the first and second wire connecting portions t ₁ and t ₂ ′ of the third gate terminal portion are arranged on a fourth straight line parallel to the third straight line. Semiconductor device. The semiconductor device according to claim 1, wherein the gate terminal portions of the first and second transistors are integrally connected to the gate electrode and are formed on the same layer of the gate electrode, respectively. The semiconductor device according to claim 2, wherein the first and second transistors have channel regions facing the same direction. The gate electrodes of the first and second transistors are provided with the gate terminal portions, and the gate terminal portions are formed in regions other than the source region or the drain region of the transistor, and the gate electrode is provided. Semiconductor devices designed to be wider. First and second insulated gate field effect transistors F _P1 and F _{P2 of} the first conductivity type and third and fourth insulated gate type field effect transistors F _N1 and FN2 of the second conductivity type, respectively; A semiconductor device comprising a plurality of unit semiconductor devices 22, wherein the unit semiconductor device and the transistors are selectively connected to each other by wires to form a desired logic circuit, and that the first transistor F _P1 The gate electrode 24P is arranged in parallel with the gate electrode 25P of the second transistor F _P2 , and the gate electrode 24N of the third transistor F _N1 is connected to the fourth transistor F _N2. ) and it is arranged parallel to the gate electrode (25N), of the first transistor has a gate terminal portion (T ₁₎ of the gate electrode (24N) of the third transistor is provided adjacent to the third transistor and also It is installed but has a gate terminal portion (T ₂₂₎ of the gate electrode (24P) away to the gate terminal portion (T ₁₎ and has the second transistor is provided adjacent to the fourth transistor, and the fourth transistor The gate terminal portion T ₂₂ of the gate electrode 25P is provided adjacent to the gate terminal portion T ₁ of the gate electrode 25N, but is separated from the gate terminal portion T ₁ . In a semiconductor device in which each gate terminal portion T ₂₂ of each of the two transistors F _P1 and F _P2 has at least first and second wire connection portions t ₁ and t ₁₂ , a separate wire junction region 28 is provided. ) the first, second, third and fourth respective gate terminals of the transistors (T _22, T _22, T _1, T are arranged in a region surrounded by the _first), the first and the one Gate of three transistors The female and the other of the second and lies fourth on the opposite side of the gate terminal portion the wire bonding regions of the transistors of the first and second transistors (F _P1, F _P2) may have a common source or drain region, And the third and fourth transistors (F _N1 , F _N2 ) have a common source or drain region. The semiconductor device according to claim 5, wherein the wire bonding region is formed on the same layer of the gate electrode. The semiconductor device according to claim 1, wherein said gate terminal portion of said first transistor is substantially crank type. The semiconductor device according to claim 6, wherein the gate terminal portion of the first transistor is substantially rectangular. A semiconductor device having a plurality of unit semiconductor devices arranged in a semiconductor device, wherein the unit semiconductor device and the elements of the unit semiconductor device are selectively connected to each other by wires to form a desired logic circuit. The unit semiconductor device includes first and second insulated gate field effect transistors of a first conductivity type and third and fourth insulated gate type field effect transistors of a second conductivity type, and the first and second transistors. Is provided with gate electrodes arranged in parallel to each other, and the third and fourth transistors are provided with gate electrodes arranged in parallel with each other, and each of the transistors has a gate terminal portion of the gate electrode adjacent to another transistor. Is provided, the gate electrode of the first transistor The gate terminal portion at least a first wire connection portion integrally formed at an end of the gate electrode, and a second extending from the first wire connection portion and located between the gate terminal portions of the gate electrodes of the third and fourth transistors; A semiconductor device comprising a wire connecting portion. A semiconductor device having a plurality of unit semiconductor devices arranged in a semiconductor device, wherein the unit semiconductor device and the elements of the unit semiconductor device are selectively connected to each other by wires to form a desired logic circuit. The unit semiconductor device includes first and second insulated gate field effect transistors of a first conductivity type and third and fourth insulated gate type field effect transistors of a second conductivity type, and the first and second transistors. Is provided with gate electrodes arranged in parallel with each other, and the third and fourth transistors are provided with gate electrodes arranged in parallel with each other, and each of the transistors is provided with a gate terminal portion of the gate electrode adjacent to another transistor. And gate electrodes of the first and second transistors. Each said gate terminal part has at least 1st and 2nd wire connection part, and the wire junction area | region is formed in the area | region enclosed by each gate electrode of the said 1st, 2nd, 3rd and 4th transistor. A semiconductor device, characterized in that.

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