JP3018410B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a master slice type semiconductor integrated circuit device.

[Summary of the Invention]

The present invention relates to a master slice type semiconductor integrated circuit device in which a plurality of transistors are formed on a semiconductor substrate and a circuit is determined by selectively contacting the wiring with the plurality of transistors. Contact holes are formed in the wiring contact portions of the plurality of transistors, and an insulating film is formed in at least the wiring contact portions of transistors other than the selected transistor. As a result, the turnaround time of the master slice type semiconductor integrated circuit device can be significantly reduced.

[Conventional technology]

A master slice type semiconductor integrated circuit device that determines a circuit by selectively contacting wiring with a plurality of transistors formed on a semiconductor substrate includes a gate array and a mask ROM (Read Only Memory).
And so on. In such a master slice type semiconductor integrated circuit device, it is required to reduce a time required from completion of circuit design to completion thereof, that is, a turn around time (Turn Around Time).

7A to 7E show a method of manufacturing a conventional master slice type semiconductor integrated circuit device.

According to this conventional manufacturing method, as shown in FIG. 7A, first, a field oxide film 102 is selectively formed on the surface of a semiconductor substrate 101 such as a p-type silicon (Si) substrate to separate elements. After that, a gate oxide film 103 is formed on the surface of the active region surrounded by the field oxide film 102. Next, after the gate electrodes 104 and 105 are formed, n
By implanting a high-concentration impurity at a high concentration, for example, n ⁺ -type semiconductor regions 106, 107, 108, and 109 used as a source region or a drain region are formed. Here, an n-channel MOS is formed by the gate electrode 104 and the semiconductor regions 106 and 107.
A transistor is formed. Similarly, the gate electrode 105 and the semiconductor regions 108 and 109 form an n-channel MOS transistor. Thereafter, an interlayer insulating film 110 is formed on the entire surface. In this state, it waits until the circuit is determined. After the circuit is determined, a resist pattern for contacting the source, drain and gate of the selected n-channel MOS transistor is formed on the interlayer insulating film 110 according to the circuit.
Form 111.

Next, as shown in FIG.
By etching the interlayer insulating film 110 using 111 as a mask, the selected, that is, the n-channel MOS to be used
Contact holes C ₁ ′ and C ₂ ′ are formed only on the semiconductor regions 106 and 107 of the transistor. After that, the resist pattern 111 is removed.

Next, as shown in FIG. 7C, after covering the surface of the portion other than the portion corresponding to the selected n-channel MOS transistor with the resist pattern 112, the contact holes C ₁ ′ and C ₂ ′ are indicated by arrows. As shown by the symbol, an n-type impurity is ion-implanted. Here, the contact holes C ₁ ', C _2' ion implantation into the if the contact holes C ₁ ', C _2' is formed so as to etch a portion of the field oxide film 102 , These contact holes
Since there is a possibility that portions where the semiconductor regions 106 and 107 are not formed may exist in C ₁ ′ and C ₂ ′, this is performed to prevent this. After that, the resist pattern 112 is removed.

In this manner, as shown in FIG. 7D, the semiconductor regions 106 and 107 extending over the entire portions of the contact holes C ₁ ′ and C ₂ ′ are formed.
Is formed. Thereafter, the surface of the interlayer insulating film 110 is flattened by reflow.

Next, as shown in FIG.
Wirings 113 and 114 such as aluminum (Al) wirings are formed on the semiconductor regions 106 and 107 through C ₁ ′ and C ₂ ′, respectively.

[Problems to be solved by the invention]

As described above, in the semiconductor integrated circuit device of a conventional master slice method, after the end of the circuit design up to its completion, the contact holes C ₁ ', C _2' forming the contact holes C ₁ ', C ₂ ′ ion implantation, interlayer insulating film 110
Many steps such as reflow were required, and the turnaround time was long.

Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit device capable of greatly reducing a turnaround time.

[Means for solving the problem]

In order to achieve the above object, according to the present invention, a plurality of transistors are formed on a semiconductor substrate (1), and a circuit is determined by selectively contacting the arrangement (15, 16) with the plurality of transistors. The wiring (15,1)
6) contact holes (C ₁ -C
₄ ) are formed in the wiring contact portions of the plurality of transistors, and contact holes (C ₃ , C ₄ ) are formed in at least the wiring contact portions of the transistors other than the selected transistor.
An insulating film (13) is formed via a conductive material (17) embedded in the inside.

According to another aspect of the present invention, a plurality of transistors are formed on a semiconductor substrate (1), and a circuit is determined by selectively contacting wirings (15, 16) with the plurality of transistors. in the semiconductor integrated circuit device of the master slice method, the wiring contact hole for the (15, 16) to contact (C ₁ -C ₄₎ is formed in the wiring contact portions of the plurality of transistors, the wiring contact portions of selected transistors In the contact holes (C ₁ , C ₂ ) of the semiconductor, an impurity-doped semiconductor (1
8) is buried, and a semiconductor (18) not doped with impurities is buried in the contact holes (C ₃ , C ₄ ) of the wiring contact portions of transistors other than the selected transistor.

Here, the wiring contact portion of the transistor includes a wiring contact portion of a gate electrode in addition to a wiring contact portion of a diffusion layer such as a source region and a drain region.

[Action]

According to the semiconductor integrated circuit device of the present invention configured as described above, formation of contact holes (C ₁ , C ₂ , C ₃ , C ₄ )
After ion implantation into the contact holes (C ₁ , C ₂ , C ₃ , C ₄ ) and reflow of the interlayer insulating film (10), the circuit design is completed with the insulating film (13) formed on the entire surface When the circuit design is completed, a photomask corresponding to the photomask is manufactured, and a resist pattern (14) having a predetermined shape is formed on the insulating film (1) by lithography using the photomask.
3) Form on top. Then, this resist pattern (1
The insulating film (13) is etched using 4) as a mask. As a result, the insulating film (13) is left at least in the wiring contact portion of the transistor other than the selected transistor. Thereafter, wirings (15, 16) such as Al wirings are formed. This determines the circuit. In this case, ion implantation into the contact hole in the interlayer insulating film _{(10) (C 1, C} 2, C 3, C 4) forming a contact hole _{(C 1, C 2, C} 3, C 4), Since the step of reflowing the interlayer insulating film (10) can be completed in advance, the steps required from completion of circuit design to completion of the semiconductor integrated circuit device are etching of the insulating film (13). Only the steps following the step of As a result, the turnaround time of the master slice type semiconductor integrated circuit device can be significantly reduced. In addition, contact holes (C ₁ to
Since C ₄₎ embedded conductive material inside (17) via an insulating film (13) is formed, the surface portion of the contact holes (C ₁ -C ₄₎ is flattened , contact holes during the etching of the insulating film _{(13) (C 1 ~C 4} )
The insulating film (13) is left in a sidewall spacer shape on the sidewall of the lower, the contact holes (C ₁ -C ₄₎
And the wiring (15,1
6) There is no risk of step breakage.

Further, according to the semiconductor integrated circuit device according to another aspect of the present invention, formation of contact holes _{(C 1, C 2, C} 3, C 4), contact holes _{(C 1, C 2, C} 3, C 4 ), The reflow of the interlayer insulating film (10), and the burying of the undoped semiconductor (18) into the contact holes (C ₁ , C ₂ , C ₃ , C ₄ ). Waits for the circuit design to be completed, and when the circuit design is completed, creates a photomask corresponding to the photomask and forms a resist pattern (19) by lithography using this photomask.
By performing ion implantation using the resist pattern (19) as a mask, impurities are implanted into the semiconductor (18) embedded in the contact holes (C ₁ , C ₂ ) of the wiring contact portion of the selected transistor. Dope.
Thereafter, wirings (15, 16) such as Al wirings are formed. This determines the circuit. In this case, ion implantation into the contact hole in the interlayer insulating film _{(10) (C 1, C} 2, C 3, C 4) forming a contact hole _{(C 1, C 2, C} 3, C 4), step inside impurities to embed the semiconductor (18) of undoped step and contact hole reflow of the interlayer insulating film _{(10) (C 1, C} 2, C 3, C 4) is kept finish previously Therefore, the steps required from the completion of circuit design to the completion of the semiconductor integrated circuit device are embedded in the contact holes (C ₁ , C ₂ ) of the wiring contact portions of the selected transistors. Only the steps after the step of doping the semiconductor (18) with impurities by ion implantation are performed. As a result, the turnaround time of the master line type semiconductor integrated circuit device can be significantly reduced.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1A to 1G show a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.

In the first embodiment, as shown in FIG. 1A,
First, a field oxide film 2 such as an SiO ₂ film is formed on a surface of a semiconductor substrate 1 such as a p-type Si substrate by a thermal oxidation method.
Is selectively formed to perform element isolation, and a gate oxide film 3 such as a SiO ₂ film is formed on the surface of the active region surrounded by the field oxide film 2 by a thermal oxidation method. Next, for example, a polycrystalline Si film is formed on the entire surface by the CVD method, and the polycrystalline Si film is doped with an impurity such as phosphorus (P) to reduce the resistance, and then the polycrystalline Si film is etched. The gate electrodes 4 and 5 are formed by patterning. The gate electrodes 4 and 5 are formed of a polycide film in which a high melting point metal silicide film such as a tungsten silicide (WSi ₂ ) film is stacked on a polycrystalline Si film doped with an impurity such as P. It is also possible to
In this case, patterning is performed after forming a refractory metal silicide film on a polycrystalline Si film doped with impurities. Next, an n-type impurity such as arsenic (As) is ion-implanted at a high concentration into the semiconductor substrate 1 using the gate electrodes 4 and 5 as a mask, for example, n ⁺ used as a source region or a drain region. Semiconductor region 6,
7,8,9 are formed. Here, the gate electrode 4 and the semiconductor region
6 and 7 form an n-channel MOS transistor.
Similarly, the gate electrode 5 and the semiconductor regions 8 and 9 form an n-channel MOS transistor. Next, an interlayer insulating film 10 such as a phosphor silicate glass (PSG) film or a boron phosphor silicate glass (BPSG) film is
To form Thereafter, on the interlayer insulating film 10, a resist pattern 11 is formed by lithography in which portions corresponding to all places where contact holes are likely to be formed are opened.

Next, as shown in FIG.
By etching the interlayer insulating film 10 using 119 as a mask, contact holes C ₁ , C ₂ , C ₃ , and C ₄ are formed in all places where a contact hole may be formed.
After that, the resist pattern 11 is removed.

Next, as shown in FIG. 1C, after forming a resist pattern 12 in which at least portions corresponding to the contact holes C ₁ , C ₂ , C ₃ , C ₄ are opened, the contact holes C ₁ , C ₂ , C ₃ , C
₄ is ion-implanted with an n-type impurity such as As or P, for example. Thereafter, the resist pattern 12 is removed.

In this way, as shown in FIG. 1D, the semiconductor regions 6, 7 and 7 extending over the entire portions of the contact holes C ₁ , C ₂ , C ₃ and C ₄ are formed.
8,9 are formed. Thereafter, heat treatment is performed to reflow the interlayer insulating film 10 to flatten the surface.

Next, as shown in FIG. 1E, an insulating film 13 is formed on the entire surface. As the insulating film 13, for example, a Si ₃ N ₄ film formed by a plasma CVD method and having a thickness of, for example, about 1000 ° can be used. In this state, it waits until the circuit design is completed.

When the circuit design is completed, as shown in FIG. 1F, an n-channel MOS transistor selected on the insulating film 13 according to the circuit is selected.
A resist pattern for contacting the source, drain and gate of the transistor is formed.

Next, using the resist pattern 14 as a mask, the insulating film
Etch 13 Thereby, as shown in FIG. 1G, the selected or used n-channel MOS
The insulating film 13 in the transistor portion is removed, and the insulating film 13 remains in the other n-channel MOS transistor portions. Next, for example, an Al film is formed on the entire surface by, for example, a sputtering method, and the Al film is patterned by etching to form wirings 15 and 16 that contact the semiconductor regions 6 and 7 through the contact holes C ₁ and C ₂ , respectively. .

Thereafter, if necessary, an upper layer wiring is formed via an interlayer insulating film, and finally, a passivation film is formed, thereby completing the intended master slice type semiconductor integrated circuit device.

As described above, according to the first embodiment, the contact holes C ₁ , C ₂ , C ₃ , and C ₄ are formed in advance in all places where the contact holes may be formed, and then these contact holes are formed. After the ion implantation into the contact holes C ₁ , C ₂ , C ₃ , and C ₄ , the reflow of the interlayer insulating film 10, and the formation of the insulating film 13, the process waits until the circuit design is completed. That is, according to the first embodiment, the formation of the contact hole, the ion implantation into the contact hole, and the reflow of the interlayer insulating film, which are conventionally performed after the circuit design is completed, are performed before the circuit design is completed. Already done. For this reason, the steps required from the end of circuit design to the completion of the semiconductor integrated circuit device are only the steps after the etching step of the insulating film 13. As a result, the turnaround time of the master slice type semiconductor integrated circuit device can be significantly reduced as compared with the related art.

 Next, a second embodiment of the present invention will be described.

In this second embodiment, after proceeding to the step shown in FIG. 1D in the same manner as in the above-mentioned first embodiment, as shown in FIG. 2A, all the contact holes C ₁ , C ₂ , C ₃ , C ₄
In the inside of the substrate, for example, tungsten (W) 17
Embed Thereafter, the insulating film 13 is formed on the entire surface.

Next, as shown in FIG. 2B, after the insulating film 13 of the selected n-channel MOS transistor is removed by etching in the same manner as in the first embodiment, the insides of the contact holes C ₁ and C ₂ are removed. Wirings 15 and 16 are formed on W17 embedded in.

According to the second embodiment, the contact holes C ₁ , C ₂ ,
Since embed C _3, W17 inside the C _4, these contact holes _{C 1, C 2, C 3} , the surface of the portion of the C ₄ is flattened. Therefore, in the first embodiment, when the insulating film 13 is etched, the insulating film 13 is left in the form of a sidewall spacer on the side wall below the contact holes C ₁ , C ₂ , C ₃ , and C ₄ , and these contact holes are formed. While there is a possibility that the sizes of C ₁ , C ₂ , C ₃ and C ₄ may be reduced, according to the second embodiment, such a problem does not occur.
Further, since the surfaces of the contact holes C ₁ , C ₂ , C ₃ , and C ₄ are flattened, there is no possibility that the wirings 15 and 16 formed thereon may be disconnected.

It should be noted that the following method may be used to contact the wiring only to the semiconductor region of the selected n-channel MOS transistor.

That is, after the process is advanced to the process shown in FIG. 1D in the same manner as in the first embodiment, as shown in FIG. 3A, the insides of the contact holes C ₁ , C ₂ , C ₃ , and C ₄ are made It is buried with insulating polycrystalline Si18 not doped with impurities. Next, a resist pattern 19 having an opening corresponding to the selected n-channel MOS transistor is formed, and the resist pattern 19 is used as a mask only in the polycrystalline Si 18 inside the contact holes C ₁ and C ₂ , for example, P Such n-type impurities are ion-implanted. Next, after removing the resist pattern 19, a heat treatment is performed. As a result, the polycrystalline Si 18 inside the contact holes C ₁ and C ₂ becomes n ₊ -type and becomes conductive.

Next, as shown in FIG. 3B, the contact holes C ₁ , C
Wirings 20, 21, 22, and 23 are formed on polycrystalline Si 18 embedded in ₂ , C ₃ , and C ₄ , respectively. In this case, since the polycrystalline Si 18 embedded in the contact holes C ₁ and C ₂ is conductive, the wirings 20 and 21 make ohmic contact with the semiconductor regions 6 and 7, respectively, but the contact holes C ₃ and C ₄ Since the polycrystalline Si18 embedded inside is insulating, the wiring 22, 23
Are not electrically connected to the semiconductor regions 8 and 9, respectively.

As described above, according to this example, the contact hole
Depending on whether or not impurities are ion-implanted into the polycrystalline Si 18 embedded in C ₁ , C ₂ , C ₃ , C ₄ , wiring contact can be selectively performed.

By the way, there is a problem of so-called halation at the time of exposure in a lithography step for forming an Al wiring. As a countermeasure for preventing this halation, a method of using a resist with a die or forming an antireflection film on an Al film has been conventionally used. However, as the width of the Al wiring has become smaller due to the progress of high integration, it has become difficult to prevent halation only by using the above-described die-containing resist. Is becoming more common.

As the antireflection film, an amorphous Si film, a titanium oxynitride (TiON) film, or the like is generally used. However, when this anti-reflection film is formed on the first-layer Al film, it is necessary to remove the anti-reflection film in the contact hole portion for connecting the first-layer Al wiring and the second-layer Al wiring. is there. This is because the resistance of the above-mentioned amorphous Si film or TION film used as an anti-reflection film is high,
This is because the presence of this antireflection film in the contact hole increases the contact resistance of the wiring.

As a method for removing the antireflection film in the contact hole portion, there is the following method. The first method is to remove the anti-reflection film in the contact hole by performing over-etching when forming a contact hole for connecting the first-layer Al wiring and the second-layer Al wiring. The second method is to remove the antireflection film in the contact hole by performing reverse sputtering before forming the second layer of Al wiring by sputtering. However, the first method has a drawback that the shape of the contact hole is deteriorated because the overetching time is long in order to remove the antireflection film. Further, the second method has a disadvantage that the uniformity of the reverse sputtering in the wafer is poor and it is difficult to uniformly remove the antireflection film, so that the contact resistance varies in the plane due to the contact holes.

Therefore, after forming the first layer of Al wiring by etching the Al film by RIE method, the entire surface is etched by RIE method using CHF ₃ or C ₂ F ₆ as an etching gas, so that everything on the Al wiring is The method of removing the antireflection film has come to be used, but this method has the following problems. That is, as shown in FIG. 8A, after forming the barrier metal film 203, the Al wiring 204, and the antireflection film 205 on the interlayer insulating film 202 formed on the semiconductor substrate 201, the antireflection film 205 is removed. For this reason, when the entire surface is etched by RIE using CHF ₃ or C ₂ F ₆ as an etching gas, the barrier metal film 203 is side-etched as shown in FIG. 8B. There is a disadvantage that the shape of the first-layer wiring including the barrier metal film 203 is deteriorated. Then, next, a method capable of solving such a problem will be described with reference to FIGS. 4A to 4C.
This will be described with reference to FIG.

That is, according to this method, as shown in FIG. 4A, a barrier metal film 33, a first-layer Al wiring 34, and an antireflection film 35 were formed on an interlayer insulating film 32 formed on a semiconductor substrate 31. Thereafter, a low-viscosity resist 36 is applied to the entire surface.

Next, etch back is performed by the RIE method using CHF ₃ , C ₂ F ₆ , SF ₆ or the like as an etching gas. Thereby, as shown in FIG. 4B, the antireflection film 35 is etched away. During this etching, the barrier metal film 33
Is covered with the resist 36, so that side-etching of the barrier metal film 33 can be effectively prevented.

Thereafter, the resist 36 is removed to obtain a state shown in FIG. 4C.

By the way, as the aspect ratio of a contact hole increases with miniaturization of elements of a semiconductor integrated circuit device,
The step coverage of the Al wiring in the contact hole portion is deteriorated. As a countermeasure against this problem, for example, a method of improving the step coverage by depositing Al at a high temperature of about 450 ° C. has been used. But,
In this high-temperature deposition, since Al crystal grains grow extremely large, alignment in performing exposure by a reduced projection exposure apparatus in a lithography process of, for example, a second-layer Al wiring after the formation of the Al wiring occurs. That is, alignment when performing exposure by the reduced projection exposure apparatus is as follows.
This is performed using an alignment mark composed of a plurality of Al patterns. However, since the crystal grains of the Al film formed by high-temperature deposition are extremely large as described above, this alignment mark is chipped from the crystal grain boundary portion, and as a result, There has been a problem that alignment cannot be performed when performing exposure by the reduction projection exposure apparatus. Therefore, a method that can solve this problem will be described next.

That is, as shown in FIG. 5, after a barrier metal film 43 is formed on an interlayer insulating film 42 formed on a semiconductor substrate 41, an Al film having a large thickness is first formed on the barrier metal film 43 by high-temperature evaporation. Form 44. Next, on this Al film 44, for example, an Al film 45 having a very small thickness at room temperature is deposited. In this case, since the crystal grains of the Al film 45 deposited at room temperature are extremely small, the function of the Al film 45 can effectively prevent the alignment mark from being chipped from the crystal grain boundary.

As shown in FIG. 6, a high-melting-point metal film 46 having a very small thickness, such as a Ti film or a TiW film, is deposited on the Al film 44 formed by high-temperature deposition to obtain high strength. By the function of the high melting point metal film 46, it is possible to effectively prevent the alignment mark from being chipped from the crystal grain boundary.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible.

For example, the n-channel MOS transistor of the above-described embodiment reduces the electric field in the vicinity of the drain region by forming a low impurity concentration portion in the drain region.
ighly Doped Drain) structure is also possible.

〔The invention's effect〕

As described above, according to the semiconductor integrated circuit device of the present invention, a contact hole for making a wiring contact is formed in a wiring contact portion of a plurality of transistors, and at least in a wiring contact portion of a transistor other than the selected transistor. Since the insulating film is formed, the turnaround time of the master slice type semiconductor integrated circuit device can be greatly reduced. In addition, when the insulating film is etched, the insulating film is left in the form of a sidewall spacer on the side wall below the contact hole, and the size of the contact hole may be reduced, or the wiring may be disconnected. Absent.

Further, according to the semiconductor integrated circuit device according to the invention, inside together with embedded semiconductor (18) is doped with impurities of the contact hole wiring contact portion of the selected transistor (C _1, C ₂₎ Since the semiconductor (18) which is not doped with impurities is buried in the contact holes (C ₃ , C ₄ ) of the wiring contact portions of the transistors other than the selected transistor, a master slice type semiconductor integrated circuit is used. The turnaround time of the device can be greatly reduced.

[Brief description of the drawings]

1A to 1G are cross-sectional views for explaining a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.
2A and 2B are cross-sectional views for explaining a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIGS. 3A and 3B are diagrams showing another method for selectively performing wiring contact. FIGS. 4A to 4C are cross-sectional views for explaining an example, and FIGS. 4A to 4C are cross-sectional views for explaining a method for preventing side etching of a barrier metal film formed below the Al wiring, FIGS. 6
7A to 7E are cross-sectional views for explaining a method for preventing chipping of an alignment mark used when performing alignment at the time of exposure by a reduction projection exposure apparatus. FIGS. 7A to 7E are conventional semiconductor integrated circuits. 8A and 8B are cross-sectional views for explaining a method of manufacturing the device, and FIGS. 8A and 8B are cross-sectional views for explaining a problem that a barrier metal film formed under an Al wiring is side-etched. Description of main reference numerals in the drawings 1: semiconductor substrate, 2: field oxide film, 3: gate oxide film, 4, 5: gate electrode, 6 to 9: semiconductor region, 10: interlayer insulating film, 13: insulating film, 15 , 16: Wiring C _{1 to} C ₄ : Contact holes.

──────────────────────────────────────────────────続 き Continuing on the front page (51) Int.Cl. ⁷ identification code FI H01L 27/118 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 21/28 H01L 21/8234 H01L 27/088 H01L 21/8246 H01L 27/112

Claims (2)

(57) [Claims] 1. A master slice type semiconductor integrated circuit device wherein a plurality of transistors are formed on a semiconductor substrate, and a circuit is determined by selectively contacting wiring with the plurality of transistors. A contact hole for making a wiring contact is formed in a wiring contact portion of the plurality of transistors, and at least the wiring contact portion of the transistor other than the selected transistor is connected via a conductive material embedded inside the contact hole. A semiconductor integrated circuit device, wherein an insulating film is formed. 2. A master slice type semiconductor integrated circuit device wherein a plurality of transistors are formed on a semiconductor substrate, and a circuit is determined by selectively contacting a wiring with the plurality of transistors. A contact hole for contacting a wiring is formed in a wiring contact portion of the plurality of transistors, and a semiconductor doped with impurities is embedded in the contact hole of the wiring contact portion of the selected transistor. A semiconductor integrated circuit device, wherein a semiconductor not doped with an impurity is embedded in the contact hole of the wiring contact portion of the transistor other than the selected transistor.