JPS61105874A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To enable to manufacture a field-effect transistor using the source region and the drain region as the electrodes with a symmetrical inner side surface as seen from the gate electrode by a method wherein the inclination of an implantation direction of impurity ions is set in a perpendicular direction to a direction that links the source region with the drain region. CONSTITUTION:Mask layers 11 with a window 10 are formed on the main surface of a semiconductor substrate 1 and a semiconductor active layer 2 is formed in the side of the main surface performing the ion-implantation treatment of such an N-type impurity as Si, S and Se. Then, a gate electrode 3 is formed on the main surface using a photolithographic technique in such a way that a Schottky junction 4 is formed between the active layer 2 and the gate electrode 3. Moreover, the ion-implantation to ion-implant such an N-type impurity as Si, S and Se in the semiconductor active layer 2 using the gate electrode 3 as a mask is performed in a state that the ion- implantation direction to the semiconductor active layer 2 is slightly inclined in a direction that links a source region 5 with a drain region 6 to the normal line to a contact point on the surface of the active layer 2. According to such a way, the field-effect transistor can be easily manufactured using the source and drain regions 5 and 6 as the electrodes with a symmetrical inner side surface as seen from the gate electrode 3.

Description

[Detailed description of the invention] Production - Ichika Ichino The present invention relates to a method for manufacturing a field effect transistor.

ji %,,-Q 掬蒲电9.1 实召責电电9.1实附1HERANGISTOR, etc., accompanied by Fig. 1 (
A device having the following basic configuration has been proposed.

7i That is, a semi-insulating semiconductor L (having a plate 1, having a required pattern on its main surface side, and containing, for example, n-type impurities only at a low FIW) Layer 2 is formed.

Thus, on the 1: side of the semi-insulating semiconductor substrate 1, one semiconductor active layer 2 having a required pattern is located at the center of the semiconductor substrate 1 in the width direction and extends across the width. A gate electrode 3 is formed to form a Schottky junction 4 between the semiconductor active layers 2 .

Further, in the semiconductor active layer 2, source regions 5 containing the same n-type impurity as the semiconductor active layer 2 in a higher distance than the semiconductor active layer 2 at both positions sandwiching the goo mill electrode 3.
A drain region 6 is formed at a desired depth from the main surface side of the semi-insulating semiconductor substrate 1, for example, to a depth that reaches the region below the semiconductor active layer 2 of the semi-insulating semiconductor substrate 1.

In this case, the inner surfaces of the source region 5 and the drain region 6 are on surfaces that substantially coincide with both side surfaces in the direction connecting the source region 5 and the drain region 6 of the electrode 3 when viewed from the gate electrode tri 3 side. It's located at 101-100-100-1000 in the neighborhood.

Furthermore, a source electrode 7 and a drain electrode 8 are ohmically connected to the source region 5 and the drain region 6, respectively.

According to the field effect 1~rangistor which determines the 174 configuration, the source electrode 5 and Control type n between electrode 3 to goo 1
By applying the voltage to the semiconductor active layer 2 from the shot 4 junction 4,
The expansion of the depletion layer that is expanding or expanding toward the lower region of the JJ layer 2 can be controlled in accordance with the value of the control voltage.

Therefore, in advance, a required power source is connected between the source electrode 7 and the gate electrode 8 through f-1'rji, and the source electrode 5 and the gate electrode 1! By applying a control voltage across i3, a candy current can be supplied to the angle i'I+1 according to the control load.
Idol! fit:

Conventionally, as a manufacturing method for a field effect transistor which is similar in principle to the field effect transistor shown in FIG. 1, the method shown in FIG.
The following principle plastic method has been proposed.

That is, a semi-insulating semiconductor substrate 1 similar to that described above in FIG. 1 is prepared in advance and covered (FIG. 2A).

Thus, a mask layer 11 is formed on the main surface F of the semi-insulating f1 semiconductor substrate 1, forming a window 10 having the same pattern as the semiconductor layer IJJE2 described in FIG. 1 (FIG. 2B).

Next, on the main surface side of the semi-insulating semiconductor substrate 1, a semiconductor active M2 similar to that described above in FIG. 1 is formed using Si, 3. It is formed by ion implantation of n-type impurities such as Sc (FIG. 2C).

Next, on the main surface of the semi-insulating f1 semiconductor I4 substrate 1, electrodes 1 to 3 similar to those in No. 1 described above in FIG. 1 are placed on the semiconductor active layer 2.
to form a Schottky junction 4 between 4, 1 and 1
It is formed using the Trisoglanoy method (Fig. 2D).

Next, implantation of n-type impurity ions such as s+, s, and se into the semiconductor active layer 2 using the goo 1 to the electrode 3 as a mask is performed from the three surfaces of the semi-insulating semiconductor substrate 1. , a source region 5 and a drain electrode 6 similar to those described above in FIG. 1 are formed in the semiconductor active layer 2.

In this case, the impurity ion implantation process is performed in a state where the implantation direction of the impurity ions is inclined with respect to the normal to the surface of the semiconductor active layer 2, as will be described later.

Next, a source electrode 7 and a drain electrode 8 similar to those described above in FIG. 1 are formed in the source region 5 and drain region 6 by using the lithography method (FIG. 2).
.

In the following manner, a field effect transistor 1 similar to that described in FIG. 1 is manufactured.

In the past, we have proposed a method for manufacturing a field effect I transistor that is similar in principle to the field effect I transistor shown in Figure 1, but also proposed a method that follows (next) with Figure 3. There is -C.

That is, as in the case of FIG. 2, a semi-insulating semiconductor substrate 1 similar to that of FIG. 1 is prepared in advance (FIG. 3A).
.

Therefore, a second layer is formed on the main surface side of the semi-insulating semiconductor substrate 1.
In the case of FIG.
Form layer 2 (Figure 3B).

Next, the mask @10 is removed and covered (FIG. 3C).

Next, on the main surface of the root plate 1 with ``+=insulation, for example, Si3N
4, and the insulating layer 2
0-L is a laminate 23 in which a layer 21 made up of layers 1 to 1 and layers 1 to 1 and layers 21 made of, for example, Ti, AI, SiO2, etc. are arranged in that order. (Fig. 3D).

Next, the laminated body 23L has two windows 24 and 25 that allow the insulating layer 20 and the area of the conductive active layer 2-F of the laminated body 23 to be exposed to the outside. mask l1126 in the area 27 between its windows 24 and 25;
However, the same pattern width as the electrodes 1 to 3 described above in FIG. 1 is formed (FIG. 3, 1).

Next (32. Mask the mask layer 26 against the vaginal laminate 23). In the tweezing process, form the mask layer 28 from the laminate 23 with the same pattern as the mask layer 26 ( Figure 3F).

Next (Mask shields 26 and 27 for active layer 2)
118 Insulating half 11A 118 Insulating semi-conductor 11A from the surface of the diode side of the substrate 1. 1i'
, i 20-)-C1 In the semiconductor active layer 2, a source region 5 and a drain region 6 similar to those described above in FIG. 1 are formed (FIG. 3G).

In this case, the impurity ion implantation process is performed in the same way as in the case of FIG.
11j The surface of the layer 20 is tilted with respect to the 'h line, as will be described later.

Next, for the insulation 11η21 of fI′1 layer 1ho2B, 1J
- [To process the mask layer 2 on the insulating layer 21.
Windows 29 and 30 are formed one size larger than the windows 27'l and 25 of No. 6 (see Fig. 3, 1-1).

Next, J,, li /) Iffff egg treatment of the insulation material of the eyes, the windows 29 and 30 of the insulation layer 26 and the insulation layer 21 are
For example, an insulating layer 31 of S f 02 is formed extending over the area 1-1 facing the area 1-1 and the mask rib 26 (the third
Figure I).

Next, in dissolving the insulating layer 21 of the laminate 23,
Therefore, only the area within the windows 29 and 30 of the insulating layer 31 is
The insulating layer 32 remains on the insulating layer 20-L (Fig. 3 ■)
.

Next, by dissolving the insulating layer 21 of the laminate 23, only the regions of the insulating layer 31 within the windows 29 and 30 remain on the insulating layer 20 as the insulating layer 32 (FIG. 3J).

Next, after the source regions 5 and 6 are activated by heat treatment, the insulating layers 30 and 32 are etched.
A window 33 which exposes the region between the source region 5 and the drain region 6 to the outside, and windows 35 and 36 which respectively expose the source regions 5 and 6 to the outside are formed (
Figure 3K).

Next, the semiconductor fil: lfj layer 2 is exposed through the window 33 (
, between the goo 1 and the electrode 3 and the semiconductor active layer 2
Form the junction 4, then attach the source region 5 and drain region 6 to the sheath electrode 7 and the drain electrode 8, respectively (Fig. 3L). .

As above, 81! ′! A field effect 1 helangistor similar to that connected to - in Fig. 1 is manufactured.

According to the manufacturing method of the field effect transistor described above, the source region 5 and the drain region 6 are formed by implanting impurity ions using the goo 1 to the electrode 3 as a mask.
A source region i or 5 and a drain region 6 are positioned and formed by the gate electrode 3. Therefore, the electric field effect transistor can be made with high viscosity and good 1', l
t, 'l can also be declared as having the same name.

However, in the case of the conventional field effect transistor manufacturing method described above in FIG. is formed as.

This 1. : Me, field effect (・The transistor has a source electric current M
li7 and drain electrode 8 are used as the original source electrode and drain electrode, respectively. Effect transistors are manufactured with different characteristics depending on the characteristics. Therefore, the electric field IT transistor has the same characteristics as when the source electrode 7 and the drain electrode 8 are used as the source electrode and the drain electrode, respectively, and vice versa. Recognizing that there is a difference between the characteristics of field-effect transistors, manufacturing It had the disadvantage of being

Accordingly, the present invention aims to propose a novel method for manufacturing a field effect single field effect transistor which overcomes the above-mentioned drawbacks.

According to the manufacturing method of the field effect 1 helangistor according to the present invention,
As in the case of the conventional principle A1 field effect 1~ transistor manufacturing method described above in FIG. Forming a semiconductor active layer containing impurities only at low temperatures ■ The semiconductor active layer is formed with a desired pattern on the main surface -1 of the semi-insulating V1 semiconductor shield plate in the longitudinal direction of the culm. Goo 1~ which extends across the width direction in the central part
Implanting treatment of impurity ions giving the same conductivity type as the semiconductor active layer forming the electrode or mask layer and the semiconductor active layer forming the electrode or mask layer, Starting from the main surface side of the semi-insulating semiconductor substrate, at both positions in the T-mounted active layer, sandwiching the gate electrode or mask layer,
A source region and a drain region containing impurities that give the same conductivity type as the semiconductor active layer at a higher concentration than the 1-square-square conductor active layer are formed at a desired depth from the main surface side of the semi-insulating semiconductor substrate. It contains a V culm that forms in the middle.

However, in contrast, the field effect method 1 to transistor method 1 according to the present invention is a field effect method including this J: process. i! 1~
In the method for manufacturing a transistor, the implantation of impurity ions in the culm is performed such that the direction of implantation of the impurity ions is perpendicular to the surface of the semiconductor active layer. 1, in a state slightly inclined in a direction perpendicular to the direction connecting the source region and the drain region.

Therefore, according to the manufacturing method according to the present invention, the source region and the drain region can be formed without causing a channeling phenomenon by covering the inner surface of the symmetrical T as seen from the electrode. It is formed.

1-IJjp□□1111Nofi Therefore, according to the method of manufacturing a helangister according to the field effect according to the present invention, impurity atoms contained in the source region and drain region become impurity ions when viewed in the depth direction of the source region and drain electrode. Since they are arranged in a straight line along the implantation direction, a channeling effect can be produced. ~Langister special 1'! On the other hand, on the contrary, a region having no difference in characteristics from that of a field effect transistor when used as a drain region and a source region, respectively, is formed.

Therefore, it has the characteristics that it can be manufactured without any restrictions in terms of its use, since it produces a chilennel effect and moves.

A field effect transistor similar to that shown in FIG. 2 or 3 is fabricated using the same steps as those described in FIG. 1. However, the ion implantation process in this case is performed as described in the problem to be solved by the invention.

[Brief explanation of drawings]

Figure 1:1 is a cross-sectional diagram of the principle of a field effect transistor. Fig. ff12 and Fig. 3 are sectional views showing the manufacturing method of the electric W effect 1 helangistor, taken along the culm of 1J sequentially.

Claims (1)

[Claims] A step of forming a semiconductor active layer having a desired pattern and containing only a low concentration of impurities that give a predetermined conductivity type on the main surface side of the semi-insulating semiconductor substrate; forming a gate electrode or a mask layer having a desired pattern and extending widthwise across the semiconductor active layer at a central portion thereof in the longitudinal direction; Implanting impurity ions giving the same conductivity type as the semiconductor active layer using an electrode or a mask layer as a mask is performed from the main surface side of the semi-insulating semiconductor substrate into the semiconductor active layer,
At both positions sandwiching the gate electrode or mask layer, a source region and a drain region containing an impurity having the same conductivity type as the semiconductor active layer at a higher concentration than the semiconductor active layer are connected to the semi-insulating layer. In a manufacturing method for a field effect transistor, which includes a step of forming a field effect transistor to a desired depth from the surface on the main surface side of a semiconductor substrate, the impurity ion implantation process in the step of forming the source region and the drain region is performed by implanting the impurity ions. An electric field characterized in that the ion implantation direction is slightly inclined in a direction perpendicular to the direction connecting the source region and the drain region with respect to the normal to the surface of the semiconductor active layer. Method for manufacturing effect transistors.