JPS6395669A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To form transistor structure in symmetry by uniformly implanting ions to the surface of a semiconductor substrate from both the channel width direction and the channel length direction, made perpendicular in the channel width direction and inclined in the channel length direction while using a gate electrode as a mask. CONSTITUTION:A gate insulating film 2 is formed onto the surface of a semicon ductor substrate 1, a polysilicon film 3 is shaped, and a gate electrode is formed through anisotropic etching. First source region 4s and drain region 4d are shaped through ion implantation, employing the gate electrode as a mask. Ions are implanted at an inclination of 20 deg. to the direction vertical to the surface of the semiconductor substrate at the angle of ion implantation so that an impurity largely intrudes under the gate insulating film 2 at that time (the directions of the arrow A and the arrow B). Second source region 5s and drain region 5d are formed in the same method as mentioned above. The angle of ion implantation is tilted at 7 deg. in order to reduce the quantity of the impurity intruding under the gate insulating film 2 at that time.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor integrated circuit device with high density, high speed, and high reliability.

2. Description of the Related Art In a conventional method for manufacturing a MOSO8 type transistor, in order to obtain high reliability with respect to drain breakdown voltage, etc., after forming a gate electrode, impurity ions at a low concentration are implanted using the gate electrode as a mask. A second source and drain region is formed by forming a second source and drain region, then forming a sidewall using an insulator on the side surface of the gate electrode, and performing high concentration ion implantation using the gate electrode and the sidewall as a mask. and LDD (Lig
htly Doped Drain) structure
It formed an OS type transistor [for example, Paul I
.

Tsaug et al, ” Fabricat
ion of High Perform+anceL
DD FET with Oxido Side
wal I Spacgv Technology”
IEEE TRANSACTIONS
ONE L・ECTR0N D EV I CE S
), Vo 1, ED 29, Is 4
.

April 1982).

Below is an example of the process step for n-MO3LD.
A method for forming a DFET will be explained with reference to FIG.

First, an insulating film 6 is formed on a P-type semiconductor substrate 1 by an element isolation process.
After forming the gate insulating film 2, a polysilicon film 3 and a first CV D S 102 film 7 are formed (FIG. 3(a)). Next, the CVD-3102 film 7
After patterning a gate electrode using a resist, the CVD-S t 0 is anisotropically etched.
2 film 7 is etched. After that, the CVD-S
Using the i02 film 7 as a mask, the polysilicon film 3 is anisotropically etched to form a gate electrode (FIG. 3(b)).
.

Next, L D D (Lightlh Doped D
In order to form (rain) regions (n single layer) 4s and 4d, low concentration ion implantation (here, phosphorus) is performed using the gate electrode as a mask (FIG. 3(C)).

After this, a second CVD-8iO□ film 8 is formed (FIG. s(d)), and anisotropic etching is performed to form a second CVD-8iO□ film 8 on the flat part.
The S102 film 8 is removed and a CV is formed around the gate electrode.
Form sideworms using D-3i02 film (third
Figure (e)). Next, the original source and drain regions (n+
In order to form layers 6g and 6d, high-concentration ion implantation (
here arsenic) (Fig. 3(f))
At this time, the sidewall 8 formed by the CV D S t 02 film prevents ion implantation into the surface of the semiconductor substrate, and the LDD region (n'' layer) is formed between the source and drain regions (n+ layer) 5s and 5d and the channel. 4g and 4d are left. Finally, heat treatment is performed to obtain n-c as shown in Figure 3 (q).
A hLDp structure MOS type transistor is formed.

As mentioned above, in the conventional MO3 type transistor,
By forming a structure having an LDD region, the n layer plays a role of relaxing the drain electric field, and high reliability with respect to drain breakdown voltage and the like can be obtained.

Problems to be Solved by the Invention However, the manufacturing method described above not only complicates the process by increasing the number of steps for forming the sidewalls, but also makes it difficult to control the width of the sidewalls. It had the problem of being clunky.

Furthermore, in the step of forming the source and drain regions,
To avoid the channeling effect of impurities during ion implantation, a certain tilt angle (
In general, ion implantation was performed at around 7). For this reason, the drain (or source) is connected to the gate electrode.
If ion implantation is performed from the opposite side, the part of the source (or drain) region adjacent to the gate electrode on the opposite side becomes a shadow and impurities are not implanted, resulting in an asymmetrical transistor structure and the transistor characteristics depending on the direction of the source or drain. There was a problem in that asymmetry occurred.

In view of the above, an object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that can form an LDD region without forming sidewalls and can form a transistor structure in a symmetrical shape.

Means for Solving the Problems The present invention uses a gate electrode formed on the surface of a semiconductor substrate as a mask, tilts it perpendicular to the channel width direction and enters the source and drain in the channel length direction, and then applies it evenly from both directions. ion implantation into the surface of the semiconductor substrate to form a first source and drain region; and second source and drain regions having different ion implantation angles and impurity concentrations in the same manner as the first source and drain regions. A method of manufacturing a semiconductor integrated circuit device includes a step of forming a drain region.

Function The present invention uses the above-described manufacturing method and does not require a step for forming sidewalls, which not only simplifies the process steps, but also eliminates the need for the width of the sidewalls, which reduces the width of the gate electrode in the channel length direction. The length can be determined only by the width of the polysilicon.

In addition, since ions are evenly implanted from an oblique direction into the source and drain regions of conventional semiconductor devices, the impurity distribution in the source and drain regions can be formed in a symmetrical shape with respect to the gate electrode, and the transistor characteristics can also be improved. It is possible to manufacture semiconductor devices that have symmetry regardless of orientation, and it is possible to increase the density and speed of semiconductor integrated circuits.
High reliability is possible.

Embodiment FIG. 1 shows the process steps of a semiconductor integrated circuit device in a first embodiment of the present invention.
It is related to S FET.

First, a gate insulating film 2 is formed on the semiconductor substrate surface (here, p-type 5i) 1, a polysilicon film 3 is formed, and then a gate electrode is formed by anisotropic etching (
Figure 1(a)).

Next, ion implantation is performed using the gate electrode as a mask to form a first source region 48 and drain region 4d (here, phosphorus is implanted as an impurity to form a single layer) (FIG. 1 Φ, (C)). . Here, the ion implantation angle is such that the direction perpendicular to the semiconductor substrate surface is tilted at 20 degrees with respect to the ion implantation direction so that the impurity penetrates deeply under the gate insulating film 2. First, the implant is perpendicular to the channel width direction and inclined to the source direction in the channel length direction (see Fig. 1(b)).
solid line arrow A), then tilt it into the other drain direction (dotted line arrow B in Figure 1(b)).
, achieve the desired amount of impurity ion implantation (Fig. 1(C)
].

Next, a second source region 6s and a drain region 5d (here, arsenic is implanted as an impurity to form an n+ layer) are formed using the same method as the step of forming the first source region 4s and drain region 4d. (Figure 1(d),
(e) ). Here, in order to reduce the amount of impurities that enter under the gate insulating film 2 and to prevent channeling effects during implantation, the ion implantation angle is set such that the direction perpendicular to the semiconductor surface is 70 degrees with respect to the ion implantation direction. Tilt it and drive it in evenly from both sides in the source and drain directions.

As described above, according to this embodiment, the LDD structure source and drain regions can be formed without a sidewall forming step, and the LDD structure source and drain regions are formed symmetrically with respect to the gate electrode. By doing so, the transistor characteristics can also be symmetrical regardless of the direction of the source or drain.

FIG. 2 shows a part of the process steps of a semiconductor integrated circuit device according to a second embodiment of the present invention, and relates to an ion implantation step. The basic process steps are the same as those in the first embodiment, and only the ion implantation step is different.

In the first embodiment, using the gate electrode as a mask, ions are implanted uniformly into the surface of the semiconductor substrate from both directions at an angle of θ so that they are perpendicular to the channel width direction and enter the source and drain in the channel length direction. (Figure 2(a)). In this example, ions are implanted evenly onto the semiconductor substrate surface perpendicular to the channel length direction and from both sides in the channel width direction at the same angle θ as described above (Fig. 2 Φ)). A desired impurity distribution is obtained by performing four equal oblique implantations.

In an actual integrated circuit, transistor patterns are formed in a direction perpendicular to gate electrodes, but according to this embodiment, it is possible to obtain the same transistor characteristics for all transistors within a wafer.

As described in detail, according to the present invention, an LDD structure MO3 type transistor can be formed without a sidewall forming step, and the source and drain regions can be formed symmetrically with respect to the gate electrode. The transistor characteristics can also be symmetrical regardless of the direction of the source and drain, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a process for explaining a method of manufacturing a semiconductor integrated circuit device in a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of a process for manufacturing a semiconductor integrated circuit device in a second embodiment of the invention. FIG. 3 is a process cross-sectional view for explaining the conventional ion implantation process. 1...p-type St substrate, 2...gate insulating film, 3...polysilicon, 4...L
DD source region, 4d...LDD drain region, 6B...source region, 6d...drain region, 6...element isolation region, 7...・・・
・1st CVD S 102 film, 8...2nd
CVD-5iO2 film, 9... Insulating film. Agent's name: Patent attorney Toshio Nakao and one other person L 4s--Ll) D Sources Negative ＼ Figure 1 Figure 1 Figure 2 Figure 3 Figure 46 4S Figure 3

Claims (1)

[Claims] A step of forming a gate electrode on a gate insulating film formed on a portion of the surface of the semiconductor substrate that will become a MOS type transistor region, and using the gate electrode as a mask, a source and a drain are formed perpendicular to the channel width direction and in the channel length direction. forming a first source and drain region by implanting ions uniformly from both directions onto the surface of the semiconductor substrate; A method of manufacturing a semiconductor integrated circuit device comprising the step of forming second source and drain regions having different angles and impurity concentrations.