JPH02161735A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a T-type gate electrode without damaging a substrate, facilitate the isolation between the gate electrode and resistance layer, and exclude the short channel effect by setting the composition ratio of WSix in a specified range. CONSTITUTION:A pattern 4 composed of WSix film 2 whose composition ratio X is 0.35-0.5 is formed on a semiconductor substrate 1; films 5a-5c are deposited on the whole surface of the substrate in the manner in which a part of the WSix film pattern is exposed from the side surface lower end of the pattern 4; the upper surface of the WSix film pattern and the side surface part of the exposed WSix film pattern are coated with films 6, 7. Next, the films 5a-5c are eliminated by chemical agent solution, and an aperture is so formed in the film 7 that the lower end-portion of the WSix pattern is exposed. Further, the WSix pattern is etched from the aperture by chemical agent solution, and the part 8 is T-shared in section.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to a semiconductor device and a method for manufacturing the same.
Sem+, conduator Fleld Eff
The present invention provides a material constituting a Schottky electrode of a Schottky gate electrode, a method of forming a Schottky gate electrode using the same, and a semiconductor device having this Schottky gate electrode structure.

[Conventional technology]

Schottky (rectification) with WS f x Ga A S
Since the bond can withstand high temperature treatment of around 800℃,
It is widely used as a Schottky gate electrode in high melting point gate self-line structure FETs. Figure 7(a)-(e)
1 is a cross-sectional view of a main part showing a method of manufacturing a conventional WSix gate self-line FET. In Figure 7(a), 2
1 is a semi-insulating Q a A 3 substrate, 22 is an active layer formed by doping the semi-insulating GaAs 1 plate 21 with n-type impurities, and 31 is a WSi layer to be bonded to the semi-insulating GaAs substrate 21.
x film. In the same figure (bl is a photoresist film 3 formed by forming a desired gate electrode pattern using ordinary photolithography technology).
The photoresist film 3 is formed by RIE using the photoresist film 3 as a mask and using, for example, NF3 gas.
(Reactive Ion Etching) The WSix film 31 has been processed into the WSix gate electrode 32 by dry etching. The same figure (dl is the W
For example, Sl ions are implanted using the ion implantation method using the Slx gate electrode 32 as a mask to form a high impurity concentration layer, and then an appropriate heat treatment is applied to activate the implanted ions to form the low resistance layer 24a.
, 24b are formed adjacent to the WSix gate electrode 32. The figure ([1) shows the low resistance layers 24a, 24
After forming the source electrode 25a and drain electrode 25b in ohmic contact on the basic GaAsME
The SFET has just been completed.

WSlx used in GaAs MESFET with this structure
For example, Applied Physics Letter 1983
, Vol. 43, No. 6.600-602 (Appl.
ied Physics Letter 1.983
Vol. 43 No. 6PP, 600-602), it is customary to use materials with a composition ratio X of around 0.6.
Below or above 0.65, it is said that good Schottky characteristics, which are important for FET performance, cannot be obtained. However, according to our experiments, by optimizing the conditions for forming the WSix film, good Schottky characteristics can be obtained in the range of 1,
．． An example using WSix in 4 is also
GaAs IC Symposium 1985 49-52
Page (IE3. GaA s I CSymposium
1985. PP, 49-52).

Dry etching is usually used to process the WSlx gate electrode as shown in FIG. 7(C). CF4 and NF
If a fluorine-based etching gas such as No. 3 is used, WStx can be processed satisfactorily over the entire composition range. In addition, the selectivity with respect to GaAs, which is the substrate, is sufficient for practical use. The reason why dry etching is used for processing is that it is easy to control anisotropy, that is, it is easy to process according to the pattern of the photoresist mask 3 produced by photolithography technology. Another major reason is that WSlx is soluble only in a mixed acid of hydrofluoric acid and nitric acid, and therefore it is difficult to selectively etch the GaAs substrate.

In addition, the WSix gate self-line FET shown in FIG.
Since i24a and 24b are formed, the gate-source parasitic resistance R3, which greatly affects FET performance, can be reduced. However, in this method, the low resistance layer 2
5a and 25b are adjacent to the gate electrode 32 (actually, during the ion implantation/heat treatment process, the low resistance layer laterally extends to the bottom of the gate electrode), so the breakdown voltage between the drain and gate is low. In addition, the short distance between the low resistance layers causes current to flow not only in the active layer 22b but also in the substrate 21 below, which is a factor that deteriorates the characteristics in the case of a short gate length (referred to as short channel effect). Two examples of methods for solving this problem are given below. All of these methods maintain an appropriate distance between the gate electrode and the low resistance layer.

FIG. 8 shows a method using side walls, which is described in, for example, Japanese Patent Application Laid-Open No. 166571/1983. 7(a), the active layer 22 is previously provided on the semi-insulating GaAs substrate 21, and the gate electrode 32 is placed on the semi-insulating GaAs substrate 21.
(This is formed using the same method as explained in BL. Next, for example, a 5tot film 33 is deposited on this upper surface by plasma CVD method, etc., and as shown in BL, the entire surface is etched by anisotropic etching such as RtE. side wall 3
3a and 33b are left on the side surface of the gate electrode 32 ((C1) in the same figure).

Next, impurities are introduced by ion implantation and annealing is performed to form low resistance layers 24a and 24b separated from the gate electrode (FIG. 4(d)). At this time, the appropriate separation width is generally about 0.2 μm.

The same figure (el is with sidewalls 33a and 33b removed,
Source and drain electrodes 25a and 25b have just been formed. The FET manufactured in this manner has the characteristics of a small short channel effect and a high gate breakdown voltage.

In addition, as another typical example of separating the low resistance layer and the gate electrode,
There is a method as shown in Publication No. 70. The method will be explained below using FIG. 9.

FIG. 9 (al) shows a state in which a WSix film 31 is deposited on a semi-insulating GaAs substrate 21 with an active layer 22 provided in advance, and a resist mask 3 is provided by ordinary photolithography. The WSix film 31 is processed into a gate pattern 32 by strong etching, for example, by RtE method (FIG. 2(b)).Next, dry etching with weak anisotropy, for example, under high gas pressure or using a different gas, is performed. , the gate pattern 32 is etched laterally (side etching) to form the gate electrode 40 (FIG. 1(C)). Impurities are then introduced by ion implantation.
By applying heat treatment, low resistance layers 24a and 24b are formed as shown in FIG. Therefore, the gate electrode 40 and the low resistance layers 24a and 24b are separated from each other.

At this time as well, the appropriate separation width is about 0°2 μm. Same figure (
81, the resist mask 3 is removed and the source and drain electrodes 25a and 25b are formed on the low resistance N24a and 24b, respectively. FE produced in this way
As a result, T has the same structure as the FET shown in FIG. 8, and the same effect can be obtained.

[Problem to be solved by the invention]

Conventionally, it was thought that W3ix could not be selectively wet-etched with chemicals against GaAs.
All processing was done by dry etching. In dry etching, the anisotropy can be controlled relatively freely, but the risk of damaging the GaAS substrate cannot be ignored.

Also, care must be taken against contamination by reaction products.

Furthermore, dry etching equipment is large-scale and generally expensive. In addition, shortening the gate length is essential for improving the performance of FET0, but the size of the resist pattern that can be formed by photolithography is limited to approximately 0.8 μm using a general method called optical exposure. It is difficult to stably obtain a gate length smaller than this using the basic method shown in the figure. Further, the method using dry etching as shown in FIG. 9 is a method for solving this problem, but since the dry etching is performed with the GaAs substrate exposed, it suffers from the above-mentioned problem (damage).

products) have a large influence.

Currently, electron beam exposure is mainly used to create resist patterns of 0.5 μm or less, but as is well known, the processing speed is extremely slow, and it takes several hours to process one wafer. There are many cases where this is required. Further, as the gate length is shortened, the cross-sectional area of the gate/electrode becomes smaller, increasing gate resistance, which impedes high-speed operation. Increasing the height of the gate excavation in order to secure the necessary cross-sectional area is possible to some extent, but in reality, it causes problems such as processing control problems and deterioration of wafer surface flatness, especially when the wafer is highly integrated. This is not a realistic direction when configuring an IC.

This invention was made to solve the above-mentioned problems, and it is possible to form a T-shaped gate electrode without fear of damaging the GaAs substrate, and also to easily connect the gate voltage to the GaAs substrate.
It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which have a solid gate electrode structure that can separate low-resistance layers, have a high gate breakdown voltage, and have a small short channel effect.

[Means to solve the problem]

The semiconductor device and the manufacturing method thereof according to the present invention are disclosed in 5, WS
It has been clarified that wet etching is possible at a practical level when the composition X is in the range of 0.35 to 0.45, and using this fact, WSi
We provide a semiconductor device and a method for manufacturing the same having a T-shaped cross-section-shaped Shosotokige-1 electric bridge structure by applying wet etching to the pattern, and furthermore, using this T-shaped gate, we can connect the gate electrode, source, and drain low-resistance layers. A semiconductor device is obtained by separating the two. That is, the method for manufacturing a semiconductor device having a D1-electrode having a T-shaped cross section is a method of manufacturing a semiconductor device having a D1-electrode having a T-shaped cross section.
a step of forming a pattern made of the In the step of providing a second film covering the substrate, the first film on the substrate is removed using a chemical solution, and an opening is formed in the second film so that the lower end of the WSix1l pattern is exposed; , further WSix by chemical solution.
A method including a step of etching the pattern from the opening portion 7 and making the cross-sectional shape T-shaped, or etching the pattern on the semiconductor substrate with a composition ratio X of 0. 35~0.5 first
WSix1! A 2N film consisting of * and a second metal film that is sparingly soluble in 77 acid-based aqueous solution is deposited in a configuration such that the first WSix film is in contact with the semiconductor substrate, and then formed into a gate electrode pattern using normal gluing lithography technology. and a step of etching the first WSix film from the lateral direction by treating it with a hydrofluoric acid-based aqueous solution to process the gate having a T-shaped cross section into a polar pattern, and further, On the semiconductor substrate, the composition ratio
0.5, and the composition ratio X is changed continuously or stepwise so that the composition ratio X is other than 0.35 to 0.5 at least on the top surface. A process of processing into an electrode pattern, and a process of processing with a hydrofluoric acid-based aqueous solution into a gate pattern with a T-shaped cross-sectional shape in which the cross-sectional lateral length of the gate pattern gradually decreases as it approaches the substrate. It consists of a method. Also, a low resistance layer is formed to become a source/drain region by ion implantation using the T-shaped gate electrode formed by this method as a mask.

is formed below the surface of the substrate to obtain a semiconductor device in which the gate electrode and the source and drain low resistance layers are separated.

[Effect]

In this invention, WS iX has a composition ratio X of Oo
35 to 0.5, it is possible to ensure a sufficient selectivity with respect to GaAs in an aqueous solution of fluoride and to perform etching at an appropriate rate.
(1,: A method in which only the lower part of the gate electrode pattern side consisting of lS~o,s is exposed and its cross-sectional shape is made into a T-shape by wet etching, and WS insoluble in a hydrofluoric acid-based aqueous solution
ix film as the upper layer, WSi.

, 5~. ,, side-etch only the lower layer of the gate electrode pattern with the film as the lower layer using a hydrochloric acid solution to make it thinner.
A method of forming a gate electrode with a T-shaped cross section, or changing the composition of the WSi film to the lower end WSio,is~. , S, is determined by the lower end of the gate electrode by forming a polar pattern with a film whose upper end is changed to WSix, which is insoluble in a hydrofluoric acid aqueous solution, and making it into a T-shape with a hydrofluoric acid aqueous solution. A gate electrode with a small effective gate length (less than 0.5 μm) and low gate resistance can be realized without worrying about damaging the GaAs substrate surface.

Furthermore, by using the WSI, T-type gate obtained in this way as it is as a mask when forming a low resistance layer by ion implantation, separation between the gate electrode and the low resistance layer can be automatically achieved, and the gate breakdown voltage is high. A GaAs MESFET with small short channel effect can be easily realized.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an example showing the etching speed of WSix.

In this example, the chemical solution used for etching was 50% hydrofluoric acid (HF).
% aqueous solution and a 40% ammonium fluoride (NH4F) aqueous solution at a mixing ratio of 1=10. For the sake of explanation, a mixed solution having this mixing ratio will be hereinafter referred to as a hydronic acid-based aqueous solution. This hydrofluoric acid aqueous solution has G
aAs can be considered virtually insoluble. In the example shown in Fig. 1, the etching rate of WSi is approximately 0.2 to 0.4 μm/hr, which is a relatively large value when the composition ratio is in the range of 0.35 to 0.5. When X is out of this range, the etching speed decreases rapidly; for example, when
．． So about 0. 01 μm/hr (100 people/h
r) and can be considered virtually insoluble.

An etching rate of 0.2 μm to 0.4 μm/hr is industrially unsuitable for patterning, for example, a 4000-layer thick WSi or gate electrode. That is, 1 for processing
This is because it takes ~2 hours and the etching progresses isotropically. For example, it is not considered that there is any particular significance in using it in the steps shown in FIGS. 7(b) to (C) of the conventional example. However, this etching does not cause any damage to GaAs, and the fact that the etching rate is not high means that precise etching amount control can be easily realized. Wet etching also requires much less expensive equipment than dry etching, and the chemicals used are also safer. Hereinafter, three embodiments of a method for manufacturing a semiconductor device that takes advantage of the fact that wet etching of WSIX is now possible will be described.

First, a first embodiment will be explained using FIG. 2.

FIG. 2(a) shows, for example, WS on a semi-insulating GaAs substrate 1.
i, 0. The film 2 has been deposited by, for example, the 4000-person sputtering method. Next, a resist film 3 with a width of 0.8 μm (in the lateral direction in the drawing) is formed using a normal photolithography technique, and patterned by RIE using a CFJ+0□ mixed gas to form a gate electrode pattern 4. (Figure (C)). Then an anisotropic deposition technique, e.g.
As shown in the figure (dl), for example, Si
Deposit 1000 O films a to 5C. At this time, due to the anisotropy of the deposition, the upper side of the gate electrode pattern 4 is kept exposed. Next, there is a photoresist film 6 on the entire surface.
The gate electrode pattern 4 is formed by a coating method ((e) in the same figure), and the unnecessary portion is removed by a normal exposure/development method so as to cover the upper side of the gate electrode pattern 4 ((f) in the same figure). Next, the SiO films 5c and 5b are removed using a hydrofluoric acid solution.

At this time, the etching rate of the SIO films 5c and 5b is very high, on the order of several thousand to several micrometers/minute, but this varies greatly depending on the deposition conditions. Here, 1μ is used for explanation.
m/min. The same figure (as if it were an illusion, the etching time required to expose the lower side of the gate electrode pattern 4 is that the distance between the edge of the resist film 7 and the gate electrode pattern 4 is 1 μm)
m, it took about 2 minutes. Considering the etching speed, it should be possible to perform etching in about 1 minute, but this is thought to be because the concentration of the etching liquid substantially decreased on the etching surface, resulting in a decrease in the etching speed. However, this decrease in etching speed can be alleviated by forcibly applying a liquid flow so that a sufficient amount of etching solution can be supplied. Etching is then performed to uniformly etch the gate electrode 4 from the lower side. It took about 1 hour to obtain a side etching amount of 0.2 μm. W
From FIG. 1, the etching rate of the Si01 film is about 0. 4μ
m/hr, but this is thought to be the result of a decrease in the etching rate due to insufficient supply of the chemical solution. At this time, as shown in the same figure (h), the gate electrode 4
is side-etched to form a T-shaped gate 8. Resist film 7. A T-shaped gate 8 is formed by removing the SiO film 5a. Since the side etching amount was set to 0.2 μm, the effective gate length was 0.4 μm. Also at this time, T-shaped gate 8
The upper end has a width of 0.8 μm, and the gate cross-sectional area is approximately 1.5 times that of a conventional rectangular gate with the same thickness and gate length, and the resistance is correspondingly low. It is easy to imagine that when the gate length is further shortened, the degree of improvement in resistance increases rapidly. In addition, the dimensions of the resist film 3 that must be formed by claw trilithography are 0.8 in this case.
.mu.m, and the alignment accuracy required when overlapping the resist film 7 on the gate pattern is only about 0.5 .mu.m, which can be easily realized using the apparatus 1 technique currently in practical use industrially.

Next, a second embodiment of the present invention will be described with reference to FIG.

The same figure (al is WSio, 4 on semi-insulating GaAs substrate 1)
Membrane 4 and WSIO-6 membrane 9, for example, which is poorly soluble in hydrofluoric acid aqueous solution.
A two-layer film 10 consisting of the following was formed using a method similar to that described above. The thickness of both is 0.2 μm. Next, the WSlo4 film 4 is side-etched using a hydrofluoric acid aqueous solution to obtain a T-shaped gate as shown in FIG. 4(b). When the width of the double layer film 10 is 0.8 μm, the effective gate length is 0.
．． The time required to obtain 4 μm was approximately 45 minutes.

Next, a third embodiment of the present invention will be described using FIGS. 4 and 5. In FIG. 4(al), 13 is a WSix film whose composition ratio is varied in the thickness direction. Examples of the composition ratio are shown in FIGS. 5(a) and (bl).

In both Figures 5(a) and (11), the composition ratio X is 0°4 at the substrate interface and 0.3 at the top surface.
While the change in al is continuous, the change in (b) is gradual. Such a wsi film can be formed, for example, by a varnish batter method using W and a 5zy-get. That is, the composition ratio is changed by changing the power applied to both targets continuously or stepwise. WSi.

The thickness of the film 13 is set to 0.4. If it is um, then 02μ, which is about half
m is soluble in the hydrofluoric acid aqueous solution, and the etching rate increases as it approaches the substrate surface. ws +,
When the width of the film 13 is 0.8 μm, the etching time is 4
An effective gate length of 0°4 μm was obtained in 5 minutes.

Such as above 1. Second. In the third embodiment,
Utilizing the fact that by setting the composition ratio Since the gate electrode is formed with a cross-sectional shape, the effective gate length determined by the lower end of the gate tti can be as small as 0.5 μm or less, and the gate resistance is low, so there is no need to worry about damaging the GaAs substrate surface. can be formed into

Incidentally, in the T-type gate manufacturing method in the second embodiment among the above embodiments, the upper WSto, h film 9 is not necessarily W.
It does not have to be Si, and may be other materials that are H-soluble in a hydrofluoric acid-based aqueous solution. Furthermore, it is also conceivable to apply a method similar to that shown in the conventional example (FIG. 9) and finally remove the -F portion film.

It goes without saying that the composition, film thickness, etching amount 2, and other conditions described in each of the above examples can be freely selected within a range that does not impair the objects and effects of the present invention.

Next, the first. Second. A method of manufacturing the GaAs MESFET using the T-type gate shown in the third embodiment will be described with reference to FIG. This achieves the purpose of the conventional example shown in FIG. 8 or 9. In FIG. 6(a), 21 is a semi-insulating GaAS substrate, 22 is an active layer formed on this surface, and 23 is the T
It is a type gate. In this embodiment, the active layer 22 is made of 30 keV2
semi-insulating G by heat treatment at 800℃ for 10 minutes
It was formed on the surface of an aAs substrate.

The T-shaped gate 23 has an effective gate length of 0.4 μm, a gate top width of 0.8 μm, and a thickness of 0.4 μm. Then, as shown in Figure 6(b), the Sto voltage was set to 60 keV across the entire surface.
, ion implantation was performed under the conditions of 2 x 1013 cm-1,
C. for 10 minutes to form low resistance layers 24a and 24b. The eaves part of the T-shaped gate 23 has a thickness of 0.
1μ or more, the implanted ions under these conditions are almost completely blocked, and as shown in the figure (bl), the low resistance layers 24a, 24
b is formed separately from the T-shaped gate electrode 23. The separation width is approximately 0.15 μm. FIG. 6(C) shows source and drain electrodes 25a and 25b which are in ohmic contact with the low resistance layers 24a and 24b, and are made of AuGe/N i /
A metal film such as Au is formed by vapor deposition lift-off method, and
It is obtained by alloying with GaAs through heat treatment at about 0°C. GaAsMESF thus obtained
ET is, for example, 0, which is manufactured by the conventional example shown in FIG.
Compared to a 4 μm gate GaAs MESFET, the gate breakdown voltage is improved from 3 V to 10 μm, and the short channel effect is also significantly improved. In addition, the conventional 0.4 μm gate has poor processing accuracy, and for example, even within the 3”φ wafer surface, the standard deviation σ
It varies to about 0.15 μm. On the other hand, according to this embodiment, the variation in effective gate length within the wafer surface is suppressed to about 0.05 μm with standard deviation σ. This is 0.
This value is almost the same as the degree of variation in processing accuracy of an 8 μm resist pattern, and indicates that side etching using a hydrofluoric acid-based aqueous solution can be performed very uniformly.

FET with a gate length variation of about 0.4μ
This is a serious problem, and in fact, using the conventional example,
Industrial use is difficult.

Thus, WSL, GaAs with T-type gate
In the manufacturing method of MESFET, WSi, T
The type gate can be used as a mask when forming a low resistance layer by ion implantation, automatically separating the gate electrode and the low resistance layer, and easily realizing a GaAs MESFET with high gate breakdown voltage and small short channel effect. .

〔Effect of the invention〕

As described above, according to the present invention, the composition ratio X of WSIX used in the Schottky gate electrode is set to 0. 35 to 0.5, it is now possible to etch WSix, which was conventionally thought to be difficult to 7-etch sea urchins, at a practical speed with a hydrochloric acid-based aqueous solution, dramatically expanding the degree of freedom in processing methods. There is.

Further, the Schottky gate electrode is WSio, ss~
. , , to expose only the lower part of the gate electrode pattern side and make the cross-sectional shape T-shaped by wet etching.
S lo, ss~. , a method of side-etching only the lower layer of a gate electrode pattern with an S film as a lower layer using a hydrofluoric acid-based aqueous solution to form a gate electrode with a thin<LT type surface shape;
Furthermore, the composition of WSt and the film is adjusted to the lower end W S f o, x
s~. , 2. The gate electrode pattern is made of a film whose upper end is made of WSi, which is insoluble in a hydrofluoric acid-based aqueous solution, and is manufactured using a method such as making it into a T-shape using a hydrofluoric acid-based aqueous solution. The electrode can be processed into a T-shape without worrying about damaging the GaAs substrate, the increase in gate resistance due to short gates can be alleviated, and short gate lengths of 0.5 μm or less can be realized with high uniformity and controllability. be. Furthermore, if the WSixT type gate obtained in this way is used as a mask when forming a low resistance layer by ion implantation, the gate electrode and the source/drain low resistance layer can be automatically separated without the need for a complicated process. This has the effect of realizing a high-performance QaAs MESFET.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the dependence of the etching rate of WSix on the composition ratio X in the present invention, FIG. 2 is a cross-sectional view of a main part showing the first embodiment of the present invention for manufacturing a T-type gate, and FIG. FIG. 4 is a sectional view of the main part showing the second embodiment, FIG. 4 is a sectional view of the main part showing the third embodiment, and FIG. 5 is for explaining the composition distribution of the gate electrode in the third embodiment. FIG. 6 is a sectional view of a main part showing a method for manufacturing a GaAs MESFET using a T-type gate, and FIGS. 7 to 9 are diagrams showing a method for manufacturing a GaAs MESFET according to a conventional example. 1 is a semiconductor substrate, 2 and 4 are WSlo, 4 films, 5a to 5c
is the first film (Sift), 6.7 is the second film (resist film), 8.12, 14.23 are T-type gates, 9 is WSio1 film, 10 is double layer film, 13 is WSi film, 22 is an active layer, 24a and 24b are low resistance layers, 25a and 25'b
are the source electrode and the drain electrode.

Claims (5)

[Claims] (1) At least a part of it has a composition ratio x of 0.35 to 0.
1. A semiconductor device comprising a Schottky gate electrode containing WSix (tungsten silicide). (2) In a method of manufacturing a semiconductor device having a Schottky gate electrode, WS whose composition ratio x is 0.35 to 0.5 is formed on a semiconductor substrate.
A first step of forming a pattern made of the WSix film and depositing a first film on the entire surface of the substrate so that a part of the WSix film pattern is exposed from the lower end of the side surface; a second step of providing a second film covering the side surface of the film pattern; and forming an opening in the second film so that the first film on the substrate is removed using a chemical solution and the lower end of the WSix film pattern is exposed. A third process is performed in which the WSix pattern is etched from the opening portion using a chemical solution, and its cross-sectional shape is made into a T-shape.
A method for manufacturing a semiconductor device, comprising the steps of: (3) In a method of manufacturing a semiconductor device having a Schottky gate electrode, a first WSix film having a composition ratio x of 0.35 to 0.5 is formed on a semiconductor substrate, and a second WSix film that is sparingly soluble in a hydrofluoric acid-based aqueous solution is provided. A first step of depositing a two-layer film with a metal film such that the first WSix film is in contact with the semiconductor substrate and processing it into a gate electrode pattern by lithography, and treating it with a hydrofluoric acid-based aqueous solution. a second step of laterally etching the first WSix film to form a gate electrode pattern having a T-shaped cross section. (4) In a method for manufacturing a semiconductor device having a Schottky gate electrode, a composition ratio x of 0.35 to 0.5 is formed on the semiconductor substrate at least at a portion in contact with the semiconductor substrate, and 0 at least at the uppermost surface.
．． The composition ratio x is set to a composition ratio x other than 35 to 0.5.
The first step is to form a WSix film in which the WSix film is changed continuously or stepwise, and then process it into a gate electrode pattern by lithography. A second step of processing a gate pattern into a T-shaped cross-sectional shape whose lateral length gradually decreases as it approaches the substrate. (5) The semiconductor device according to any one of claims 2 to 4, characterized in that a low resistance layer to be a source/drain region is formed under the surface of the substrate by ion implantation using the T-shaped gate electrode as a mask. Production method.