JP2000200759A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a plurality of impurity regions simultaneously at desired densities and in desired distributions by reducing the number of stopping parameters of an ion implantation species as for a through film for ion implantation. SOLUTION: Single-layer insulating films 3 and 5 which have different thicknesses are formed at different places on a semiconductor substrate 1, and are implanted with impurity ions to thereby form a plurality of impurity regions on the substrate 1 simultaneously. The film 5 is formed by forming a sacrificial layer 4 which is opened at the insulating film forming place, and is lifted off together with the layer 4. When the film 4 is made of a resist, the film 5 is formed at such a low temperature as not to damage the peel-off property of the resist. The plurality of different impurity regions may be formed simultaneously by partially etching the single-layer insulating films and implanting impurity ions via a plurality of places where the film thicknesses are different.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device including a step of simultaneously forming a plurality of impurity regions having different impurity concentrations and distribution shapes on a semiconductor substrate through a single ion implantation.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices, it is necessary to form various impurity regions in a semiconductor substrate by changing the concentration and distribution shape of impurities. As a typical example of the different impurity regions, there are channel formation impurity regions of transistors having different threshold voltages. FIG. 5 shows an enhancement type ME.
FIG. 9 is a cross-sectional view showing a manufacturing process when an SFET and a depletion-type MESFET are formed on the same GaAs substrate.

In FIG. 5A, a resist pattern 101 having an opening in a partial region is formed on a semiconductor substrate 100 such as a GaAs wafer, and n-type impurities are ion-implanted using the resist pattern 101 as a mask to form an enhancement type MESFET. A channel forming impurity region 102 is formed. After the removal of the resist pattern 101, similarly, as shown in FIG.
Another resist pattern 103 opening in another region is formed, and using this as a mask, an n-type impurity is ion-implanted to form a channel forming impurity region 104 of the depletion type MESFET. After removing the resist pattern 103 and annealing to activate the impurities, as shown in FIG. 5C, the source electrode 105, the drain electrode 106,
A Schottky gate electrode 107 is formed on each of the channel forming impurity regions 102 and 104 to form two types of M
Complete the basic structure of ESFET.

However, in this manufacturing method, when forming the channel forming impurity regions 102 and 104, individual FETs are formed.
Are separately implanted under the condition according to the threshold voltage Vth, the threshold voltage difference between FETs is not always constant due to the variation of the ion implantation (particularly, the variation of the dose amount). For this reason, the enhancement type FE
In designing a circuit in which T and a depletion type FET are mixed, there is a disadvantage that a circuit operation margin is small and a malfunction is likely to occur.

In order to eliminate this disadvantage, it is effective to form the channel forming impurity regions of the enhancement type FET and the depletion type FET simultaneously by one ion implantation. At this time, it is necessary to provide a difference in the way of introducing the ion species. For example, Japanese Patent Application Laid-Open No. Sho 60-130120 discloses a technique for providing a difference in the insulating film as an ion implantation through film. Have been.

FIG. 6 shows a sectional view of the embodiment described in the above publication. In the illustrated example, two impurity regions having different conductive characteristics are formed adjacently and simultaneously by one ion implantation.

In FIG. 6A, a first insulating film 101 and a second insulating film 102 are formed on a semiconductor substrate 100. As shown in FIG. 6B, a resist 103 for forming a desired pattern is formed on the second insulating film 102, and the surrounding second insulating film 102 is removed by etching. In this state, ion implantation is performed to form the first insulating film 10 as shown in FIG.
1, the impurity is introduced into the semiconductor substrate 100, and the impurity region 104 becomes the second insulating film 102 and the resist 103.
Is formed in the semiconductor substrate surface region around the laminated pattern composed of. After removing the resist 103, a second ion implantation is performed as shown in FIG. At this time, impurities are introduced into the surface region of the semiconductor substrate located between the two impurity regions 104 through the first and second insulating films 101 and 102. As a result, the impurity regions 10 having different conductive characteristics are obtained.
4, 105 are formed.

[0008]

However, in this conventional method of manufacturing a semiconductor device, impurity regions having different conductive characteristics are formed by changing the number of insulating films constituting the ion implantation through film. There are always places where impurities are introduced. For example, in FIG. 6D, the impurity region 105 is formed by introducing impurities through the two insulating films 101 and 102. For this reason, in the conventional method for manufacturing a semiconductor device, the amount of impurity introduced into the impurity region 105 depends on the type, film quality (composition), and film thickness of the plurality of insulating films 101 and 102, so that the impurity concentration and distribution shape are different. There was a disadvantage of not being stable.

In general, an ion-implanted through film has an important function as an ion species stop layer to limit the amount of impurities introduced into a semiconductor substrate, and it is preferable that the stopping parameter of the ion-implanted through film be as small as possible.
However, in the conventional method, since a plurality of insulating films are stacked and used as an ion implantation through film, the stopping parameters of the ion implantation species are inevitably large, which is a factor that prevents the impurity region from being formed stably. For this reason, especially in a mixed circuit of an enhancement type FET and a depletion type FET in which the threshold voltage difference of the FET is important, the operating voltage margin is not sufficient, and the malfunction cannot be completely prevented.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of simultaneously forming a plurality of impurity regions with a desired concentration and distribution shape by minimizing the number of stopping parameters of ion implantation species in a through film for ion implantation. The purpose is to provide.

[0011]

A method of manufacturing a semiconductor device according to the present invention comprises the steps of forming single-layer insulating films having different thicknesses at a plurality of locations on a semiconductor substrate; Implanting impurities through the insulating film to simultaneously form a plurality of impurity regions in the semiconductor substrate.

In the step of forming the single-layer insulating film, preferably, a sacrifice layer which is opened at a portion where the insulating film is formed is formed. A film is formed, and the insulating film on the sacrificial layer is removed together with the sacrificial layer. When the sacrificial layer is made of a resist, the insulating film is preferably formed at a temperature low enough to prevent the resist from being deformed and without deteriorating the removability. Preferably, a step of performing a heat treatment after forming the impurity region,
A step of removing the insulating film; and a step of etching a predetermined amount of the surface of the semiconductor substrate.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film on a semiconductor substrate and a step of forming, at least in one portion of the insulating film, a region having a different thickness from the periphery. And ion-implanting impurities through a plurality of insulating film regions having different film thicknesses to simultaneously form a plurality of impurity regions in the semiconductor substrate.

In the step of forming regions having different thicknesses in the insulating film, it is preferable that the thickness of at least one of the insulating film regions is smaller than the thickness at the time of film formation. For example, a mask layer opening on a predetermined region is formed on the insulating film,
The surface of the insulating film region exposed from the opening of the mask layer is preferably etched by a predetermined amount.

In these methods of manufacturing a semiconductor device, each of the insulating films as the ion implantation through film is a single layer film,
By simply controlling the film thickness and implanting ions, a plurality of impurity regions having different conductive characteristics can be formed. For this reason, a difference in characteristics such as conductivity between the plurality of impurity regions becomes nearly constant. When this method is applied to the formation of a channel forming impurity region of a transistor, the threshold voltage difference between transistors of different types, such as an enhancement type and a depletion type, takes a value close to a constant value. Therefore, by subsequently etching the substrate surface while monitoring the threshold voltage, variations among ion implantation lots or wafers can be reduced.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a plurality of impurity regions will be described.
Enhancement type field effect transistors (hereinafter, E-
An embodiment of the present invention will be described by taking as an example a case where a channel forming impurity region of a FET and a channel forming impurity region of a depletion field effect transistor (hereinafter referred to as a D-FET) are simultaneously formed on the same semiconductor substrate. explain.

First Embodiment FIGS. 1 and 2 are cross-sectional views showing the steps of manufacturing a semiconductor device according to a first embodiment.

In FIG. 1A, a semiconductor substrate 1 such as a GaAs wafer is prepared, and a resist pattern 2 having an opening on an E-FET formation region 1a of the semiconductor substrate is formed thereon. An insulating film 3 having a predetermined thickness is formed on the resist pattern 2 and the bottom of the opening. In this film formation, various film formation methods, such as sputtering, vapor deposition, or low-temperature CVD, which do not require high-temperature heating of the semiconductor substrate 1 and are not accompanied by alteration of the resist pattern 2 and deterioration that hinders peelability, are used.

The semiconductor substrate 1 is immersed in acetone or a resist stripper, and the resist pattern 2 and the insulating film portion on the resist pattern 2 are removed by a lift-off method. Thereby, the E-FET formation region 1a of the semiconductor substrate
An isolated pattern of the insulating film 3 is formed thereon.

In FIG. 1B, the DF of the semiconductor substrate
A resist pattern 4 having an opening is formed on the ET formation region 1b, and an insulating film 5 having a predetermined thickness different from the insulating film 3 is formed on the resist pattern 4 and on the bottom of the opening. This film formation also does not require high-temperature heating of the semiconductor substrate 1, such as sputtering, vapor deposition, or low-temperature CVD.
Various film forming methods that do not involve deformation that hinders deformation or peelability of the resist pattern 4 are used.

The semiconductor substrate 1 is immersed in acetone or a resist stripper, and the resist pattern 4 and the insulating film portion on the resist pattern 4 are removed by a lift-off method. Thereby, the D-FET formation region 1b of the semiconductor substrate
An isolated pattern of the insulating film 5 is formed thereon.

In FIG. 2D, resist patterns 6 each having an opening on the insulating films 3 and 5 are formed. Using resist pattern 6 as an ion implantation mask layer, n-type impurity ions such as silicon ions Si ⁺ are implanted under predetermined conditions. At this time, depending on the ion implantation conditions (ion species, implantation energy and dose), the type, film quality (composition) and film thickness of the insulating films 3 and 5, the impurity added regions 7 'and 8 having a predetermined concentration and distribution shape. Is formed in the E-FET formation region 1a and the D-FET formation region 1b, respectively. Annealing is performed under predetermined conditions after the resist is stripped, so that a conductive channel forming impurity region, that is, E-FE, is formed from the two impurity added regions 7 ′ and 8 ′.
A channel forming impurity region 7 of T and a channel forming impurity region 8 of D-FET are formed.

Thereafter, FET electrodes and the like are formed on the channel forming impurity regions 7 or 8. For example, FIG.
GaAs MESFET (Metal-Semicon) shown in (E-1)
In the case of a ductor FET, a source electrode 9 and a drain electrode 10 made of ohmic metal are formed separately from each other, and a Schottky gate electrode 11 is formed therebetween.
The ohmic metal is made of, for example, an AuGe alloy layer and Ni
It is obtained by heating a pattern consisting of layers and alloying it with a GaAs substrate. Schottky gate electrode 11
Is made of, for example, Al, Ti / Au or a refractory metal alloy (such as TiW).

The GaAs JFET (J shown in FIG.
In the case of unction FET), ap ⁺ gate impurity region 12 is formed on the surface of the channel forming impurity regions 7 and 8. This p
^In the formation of ⁺ gate impurity region 12, for example, a gas phase diffusion method using diethyl zinc (Zn (C ₂ H ₅ ) ₂ ) as a diffusion source is used. A source electrode 9 and a drain electrode 10 are formed as in the case of the MESFET, and, for example, Ti / Au is formed on the p ⁺ gate impurity region 12 between the electrodes.
The gate electrode 13 is formed.

Thereafter, FIGS. 2 (E-1) and 2 (E-
In each case 2), although not particularly shown, a lead wire or the like of an electrode is formed through an interlayer insulating film, and an overcoat film is formed on the outermost surface and a pad opening is formed.
The semiconductor device is completed.

In the method of manufacturing a semiconductor device according to the first embodiment, the channel forming impurity regions 7 and D
The channel forming impurity region 8 of the FET is formed in each of the FET forming regions 1a and 1b through ion implantation using a single-layer ion implantation through film (insulating film 3 or 5). The fact that the ion implantation through film is made of a single-layer insulating film is that the main stopping parameters of the ion species are as small as two kinds of the material and the film thickness of the single-layer film. It is easy to obtain the completed concentration and distribution shape etc. according to the device design.

The difference between the threshold voltage Vth of the E-FET and the threshold voltage Vth of the D-FET is determined by the difference between the thicknesses of the insulating films 3 and 5 if they are the same. Even if the conditions are slightly shifted, they are kept almost constant.

Therefore, assuming that the ion implantation conditions vary somewhat, the implantation energy or the dose amount is set to a relatively large value so that the threshold voltage Vth is increased (increased on the negative side). After the implantation, the threshold voltage Vth can be adjusted for each wafer. At this time, the threshold voltage Vth is measured, for example, as shown in FIG. Method can be used. When the voltage V applied between the two mercury probes 14 and 15 is increased, the depletion layer 1
6, and a large detection capacity is observed. When the depletion layer 16 reaches the entire depth of the channel forming impurity region 7 (or 8), the capacitance of the depletion layer rapidly decreases to a small value depending only on the side area. The applied voltage V at this capacitance change point
p corresponds to the threshold voltage Vth of the transistor. In the first embodiment, the difference between the threshold voltages Vth of the E-FET and the D-FET is kept substantially constant. It is possible to adjust the transistor threshold voltage of each wafer to an optimum value.

Second Embodiment FIG. 4 is a sectional view showing the steps of manufacturing a semiconductor device according to a second embodiment up to the formation of an impurity-added region.

In the second embodiment, as shown in FIG. 4A, a single-layer insulating film 20 is formed on the semiconductor substrate 1 by, for example, CVD. The thickness of the insulating film 20 is
E-F corresponds to the thickness of the insulating film 3 in the first embodiment.
The optimum value is set as the ion implantation through film for ET.

As shown in FIG. 4B, a resist pattern 21 having an opening in the D-FET formation region 1b is formed on the insulating film 20, and an opening 21a of the resist pattern 21 is formed.
A portion of the insulating film 20 exposed from the substrate is cut by a predetermined amount by etching. The remaining film thickness of the etching corresponds to the film thickness of the insulating film 5 in the first embodiment, and is set to an optimum value as the ion implantation through film of the D-FET.

In FIG. 4C, the resist pattern 2
2 is formed, and ion implantation is performed using the single-layer insulating film 20 in which the film thickness of a part of the region is reduced as a through film, thereby forming impurity-added regions 7 ′ and 8 ′ having a predetermined concentration and distribution shape. . After removing the resist pattern 22, a plurality of channel forming impurity regions having different conductive properties are obtained by annealing.

Thereafter, as in the first embodiment, the MES
The basic structure of the FET or JFET is completed through formation of various electrodes and the like.

In the method of manufacturing a semiconductor device according to the second embodiment, since different channel forming impurity regions are formed by using a single-layer ion-implanted through film, the stopping parameter of the ion species is changed in each region of the through film. Only the film thickness difference is smaller than in the first embodiment. If etching with high accuracy is performed to cause a difference in thickness of the through film, the threshold voltage difference between the E-FET and the D-FET can be set more accurately than in the first embodiment.

In the first and second embodiments described above, the transistors are not limited to MESFETs and JFETs, but may be GaAs HEMTs (High Electron Mobility Transistors).
stor), a silicon MOSFET, a bipolar transistor, or the like. The method of forming the impurity-added region of the present invention is not limited to the formation of the channel-forming impurity region of the transistor, and is widely applied to, for example, well formation, ion implantation for forming the source / drain impurity region and adjusting the threshold voltage. Applicable. The present invention is applicable not only to two types of impurity regions formed at the same time, but also to three types or more.

[0036]

According to the method of manufacturing a semiconductor device of the present invention, the number of stopping parameters of ion implantation species in a through film for ion implantation is reduced as much as possible, and a plurality of impurity regions are formed with a desired concentration and distribution shape. Can be simultaneously formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a process of manufacturing a semiconductor device according to a first embodiment up to the formation of an ion implantation through film.

FIG. 2 is a cross-sectional view showing up to the formation of the basic structure of the FET in the manufacturing process following FIG. 1;

FIG. 3 is a diagram for explaining a method of measuring a threshold voltage.

FIG. 4 is a cross-sectional view illustrating a process of manufacturing a semiconductor device according to a second embodiment up to the formation of an impurity-added region;

FIG. 5 is a cross-sectional view showing a manufacturing process when an enhancement type MESFET and a depletion type MESFET are formed on the same GaAs substrate by using a conventional manufacturing method.

FIG. 6 is a sectional view showing an embodiment of the technology described in the patent publication.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1a ... Enhancement type FET formation area, 1b ... Depletion type FET formation area, 2
4,6,21,22 ... resist pattern (sacrifice layer),
3,5 ... insulating film, 7,8 ... channel forming impurity region,
7 ', 8': impurity doped region, 9: source electrode, 10 ...
Drain electrode, 11 ... Schottky gate electrode, 12 ...
p ⁺ gate impurity region, 13 ... gate electrode, 14, 15
... Mercury probe, 16 ... depletion layer, 20 ... insulating film.

Claims (10)

[Claims] A step of forming single-layer insulating films having different thicknesses from each other at a plurality of locations on a semiconductor substrate; ion-implanting impurities through the plurality of single-layer insulating films;
Forming a plurality of impurity regions simultaneously in the semiconductor substrate. In the step of forming a single-layer insulating film, a sacrifice layer is formed at a location where the insulating film is formed, and the insulating film is formed on the semiconductor substrate portion and the sacrifice layer exposed by the opening of the sacrifice layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the film is formed, and the insulating film on the sacrificial layer is removed together with the sacrificial layer. 3. The method according to claim 2, wherein the sacrificial layer is formed of a resist, and the insulating film is formed at a temperature low enough not to cause pattern deformation of the resist and not to impede peelability.
13. The method for manufacturing a semiconductor device according to item 5. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment after the ion implantation forms impurity regions for determining the channel concentration of the field effect transistor at a plurality of locations on the semiconductor substrate. 5. The method of manufacturing a semiconductor device according to claim 4, wherein said impurity region includes a channel forming impurity region of an enhancement type field effect transistor and a channel forming impurity region of a depletion type field effect transistor. 6. The method according to claim 1, wherein said semiconductor substrate is made of GaAs. 7. The method of manufacturing a semiconductor device according to claim 1, further comprising: a step of performing a heat treatment after forming the impurity region; a step of removing the insulating film; and a step of etching a predetermined amount of the surface of the semiconductor substrate. Method. 8. A step of forming an insulating film on a semiconductor substrate; a step of forming a region having a thickness different from the periphery at least at one position of the insulating film; Implanting impurities through the film region to simultaneously form a plurality of impurity regions in the semiconductor substrate. 9. The semiconductor device according to claim 8, wherein in the step of forming regions having different thicknesses in the insulating film, the thickness of at least one of the insulating film regions is made smaller than the thickness at the time of film formation. Production method. 10. A method of manufacturing a semiconductor device comprising the steps of: forming a mask layer having an opening on a predetermined region on the insulating film when reducing the thickness of the insulating film; The method for manufacturing a semiconductor device according to claim 9, wherein constant-rate etching is performed.