JP2003297853A - Method of manufacturing field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a field effect transistor having a short gate length without being limited in terms of a device. <P>SOLUTION: The field effect transistor is provided with a source electrode and a drain electrode, which are separately formed on the surface of a semiconductor substrate, and a gate electrode which is brought into Schottky-contact with the semiconductor substrate on the semiconductor substrate between the electrodes. The method is provided with a process for forming the gate electrode of a metal film on an active layer on the surface of the semiconductor substrate, a process for etching the surface of the active layer so that a contact width between the gate electrode and a date length direction of the active layer becomes narrow by using the gate electrode as an etching mask and a process for making the solid-phase reaction of a lowermost metal in the gate electrode and the active layer remaining below the gate electrode by heat treatment and forming an alloy layer. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate of a field effect transistor (FET), and more particularly to a method of manufacturing a field effect transistor having a gate having a gate length shorter than a metal width of a formed gate electrode.

[0002]

2. Description of the Related Art MESFET (Metal Semiconducer) which is a Schottky field effect transistor using GaAs
tor FET) and HEMT (High Electron Mobility Transi)
Stor) is widely used as a constituent element of an MMIC (Monolithic Microwave IC), and it has recently become important to shorten the gate length in order to improve high frequency characteristics.

FIG. 3 is a sectional view of each step showing a method for manufacturing a MESFET. Si is ion-implanted on the GaAs substrate 1 to form the active layer 2 (N type), and the contact layer 3 (N ⁺ ) is formed by selectively implanting Si using a photoresist having a predetermined pattern as a mask. A mold) is formed (FIG. 3A).

On the contact layer 3, a source electrode 4 and a drain electrode 5 made of Au / Ge / Ni / Au which form an ohmic junction are formed by a lift-off method. Next, using a photoresist having a predetermined pattern as a mask, F
Selective ion implantation of B (boron) is performed outside the ET region to form an isolation layer 6 for element isolation (FIG. 3).
(B)).

Next, SiN is deposited on the entire surface, and the SiN film 7 on the active layer 2 is partially etched and opened by using a photoresist having a predetermined pattern as a mask. Ti forming Schottky junction with layer 6
The gate electrode 8 made of / Pt / Au is formed by the lift-off method (FIG. 3C). Although the active layer 2 is usually recess-etched before the gate electrode 8 is formed, it is omitted in the description.

As described above, in forming the gate of a field effect transistor such as MESFET or HEMT, the gate length of the FET has conventionally been determined by the width of the deposited metal.

[0007]

[Problems to be Solved by the Invention] MESFET and HEM
In field effect transistors such as T, FET characteristics such as high frequency characteristics are improved by shortening the gate length.
In order to shorten the gate length, it is necessary to shorten the width itself of the gate electrode metal to be deposited. However, the width of the gate electrode metal mainly depends on the accuracy of photolithography, and in order to shorten the gate length, an expensive and high-resolution exposure apparatus must be used, which is a limitation of the apparatus. Had.

As a countermeasure against this problem, a method has been proposed in which the gate electrode is used as an etching mask and the active layer under the gate electrode is side-etched to shorten the gate length. The contact area with and becomes smaller, and the gate length is shortened. However, in the manufacturing process of the field effect transistor, the side-etched portion is finally filled with the protective film and the like, so that there is an effect that the dielectric constant is somewhat reduced, but the contact portion between the side-etched portion and the gate electrode Since there is no great difference in the spread of the depletion layer, the side etching portion eventually contributes as a gate, and the effect of shortening the gate length was small.

In order to solve such a problem, the present invention provides a high-performance field effect transistor having a short gate length effectively even in the case of a gate electrode metal formed to have a certain width due to device limitations. It is intended to provide a method of manufacturing.

[0010]

According to the present invention, there are provided a source electrode and a drain electrode formed on a surface of a semiconductor substrate with a space therebetween, and a gate electrode which is in Schottky contact with the semiconductor substrate on the semiconductor substrate between the electrodes. A method of manufacturing a field effect transistor comprising: a step of forming a gate electrode of a metal film on an active layer on a surface of the semiconductor substrate; and using the gate electrode as an etching mask, the gate electrode and the gate of the active layer To reduce the contact width in the long direction,
A step of etching the surface of the active layer, and a step of performing a solid phase reaction between at least the lowermost metal of the gate electrode and the active layer remaining under the gate electrode by heat treatment to form an alloy layer. It is characterized by going out.
Further, at least the lowermost metal of the gate electrode is a Pt layer, and at least the active layer on which the alloy layer is formed is GaAs. By the above means, a field effect transistor having a gate length shorter than the metal width of the gate electrode can be manufactured.

[0011]

1 and 2 are sectional views of respective steps showing a method for manufacturing a MESFET according to an embodiment of the present invention. The active layer 2 (N type) is formed by ion-implanting Si on the GaAs substrate 1, and then, using a photoresist (not shown) having a predetermined pattern as a mask, Si is selectively ion-implanted. So contact layer 3
(N ⁺ type) is formed (FIG. 1A).

Next, using a photoresist having a predetermined pattern formed on the contact layer 3, Au / Ge / Ni / Au is vacuum-deposited as an electrode material by a lift-off method to remove the photoresist, and then heat treatment is performed. The source electrode 4 and the drain electrode 5 are formed. At this time, the contact layer 3, the source electrode 4 and the drain electrode 5 are alloyed to form ohmic contact.

Next, using a photoresist having a predetermined pattern as a mask, B (boron) ions are implanted outside the FET region to form an isolation layer 6 for element isolation (FIG. 1B. )).

Next, a SiN film 7 which is an insulating film is deposited on the entire surface by a plasma CVD method, and then a photoresist is spin-coated on the entire surface of the wafer. Then, after exposing and developing using a mask that removes the photoresist in the gate electrode formation region between the source electrode 4 and the drain electrode 5 to form an opening, the SiN of this opening is continuously formed.
The film 7 is removed by wet etching or reactive ion etching to expose the active layer 2.

Then, a gate electrode metal composed of Pt / Ti / Pt / Au is deposited and lifted off to form the gate electrode 8 (FIG. 1 (c)). Here, as the lowermost metal of the gate electrode 8, GaAs and 300 ° C. to 4 ° C.
Use Pt that can easily be solid-phase reacted at 00 ° C. to be alloyed to obtain a Schottky junction (for example, a Pt layer having a thickness of 5
0 Å).

Next, the active layer 2 is wet-etched with a mixed solution of phosphoric acid, hydrogen peroxide or the like using the gate electrode 8 and the SiN film 7 as a mask, and the active layer 2 under the gate electrode 8 is side-etched. The contact width in the gate length direction between the gate electrode 8 and the active layer 2 is narrowed. Any etching liquid may be used as long as it isotropically etched. The gate electrode width is determined by selecting conditions such as etching rate and etching time. For example, if the gate length of the gate electrode 6 before side etching is 0.4 μm,
The gate length can be set to about 0.3 μm by side etching 0.05 μm from both sides (FIG. 1).
(D)).

Next, by performing annealing (heat treatment) at 350 ° C. for about 10 minutes, G under the metal of the gate electrode is removed.
The aAs layer and Pt undergo a solid phase reaction to form the alloy layer 9 (FIG. 2). This alloy layer 9 becomes a gate that makes a Schottky contact with the GaAs layer.

In the case of the conventional side etching only, after the side-etched portion is finally filled with a protective film or the like in the manufacturing process, the side-etched portion also contributes as a substantial gate, and the effect of shortening the gate length is small. . On the other hand, in the present invention, in addition to the side etching, the GaAs layer and Pt are solid-phase-reacted with each other to form an alloy, so that the gate (Schottky junction) formed by the alloy layer 9 moves to the lower layer and the gate formed in the side-etched portion. The gate length can be substantially shortened regardless of. From the above, a high-performance FET having an effective gate length shorter than the vapor-deposited gate electrode metal width is manufactured.

The above-described embodiments are merely examples, and in the case of manufacturing by the method of forming the contact layer by self-alignment of the gate electrode, a step of performing recess etching before forming the gate electrode is added. Or Si
Even when an insulating film other than the N film is used, the manufacturing method of the present invention can be applied to a field effect transistor having a Schottky junction gate electrode.

The manufacturing method of the present invention is applicable not only to the case where the active layer is formed by ion implantation, but also to the case where the active layer is formed of an epitaxial layer or HEMT using a two-dimensional electron gas as a carrier. You can

[0021]

According to the present invention, in forming a gate of a field effect transistor, the width of the gate electrode metal is shorter than that of the formed gate electrode only by controlling side etching conditions and heat treatment conditions without using a high resolution exposure apparatus. A field effect transistor having a gate length can be easily formed with high precision. Further, this can improve the transistor performance such as high frequency characteristics. Further, in the present invention, when at least the lowermost metal of the gate electrode is the Pt layer and the alloy layer is formed on the active layer made of GaAs, the alloy layer can be formed easily and stably.

[Brief description of drawings]

FIG. 1 is a sectional view of each step of an embodiment of the present invention.

FIG. 2 is a sectional view of each step of the embodiment of the present invention.

FIG. 3 is a sectional view of each step showing a conventional method for manufacturing a field effect transistor.

[Explanation of symbols]

1. Semi-insulating GaAs substrate 2. Active layer 3, contact layer 4, source electrode 5, drain electrode 6, isolation layer 7, SiN film 8, gate electrode 9, alloy layer

Claims (2)

[Claims] 1. A method of manufacturing a field effect transistor comprising a source electrode and a drain electrode formed separately on a surface of a semiconductor substrate, and a gate electrode in Schottky contact with the semiconductor substrate on the semiconductor substrate between the electrodes. In the method, the step of forming a gate electrode of a metal film on the active layer on the surface of the semiconductor substrate, and using the gate electrode as an etching mask, the contact width of the gate electrode and the active layer in the gate length direction is narrowed. As described above, a step of etching the surface of the active layer, and a step of performing a solid phase reaction between at least the lowermost layer metal of the gate electrode by heat treatment and the active layer remaining under the gate electrode to form an alloy layer A method for manufacturing a field effect transistor, comprising: 2. The field effect transistor according to claim 1, wherein at least the lowermost metal of the gate electrode is a Pt layer, and at least the active layer on which the alloy layer is formed is GaAs. Production method.