JP2008103459A - Field effect transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a field effect transistor for reducing distance between a gate electrode and a trench to zero not depending on alignment accuracy and moreover for making narrower an aperture width of the trench not depending on aperture capability of a stepper. <P>SOLUTION: After an insulating film 18A and a resist layer R1 having an aperture H1 having an opening diameter L1 are formed (S1, S2) on a diffusing layer 17, an aperture is formed to the insulating film 18A using a resist layer R1 as a mask (S3). After the resist layer R1 is removed, a gate region 20A is formed to an exposed part of a diffusing layer 17 using the insulating film 18A as a mask (S4). After a resist layer R2 having an aperture H2 having an opening diameter L2 is formed (S5), a gate electrode 21 is formed to a part of the aperture H2 with the lift-off method (S6). A pair of trenches 19 are formed to both sides of the gate electrode 21 using the gate electrode 21 and insulating film 18A as masks (S7). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a field effect transistor having a trench between a gate drain and between a gate source and a method for manufacturing the same.

As shown in FIG. 25A, the switch IC used in the RF front end portion of a cellular phone is generally an FET ₁ (series-inserted between an input port P ₁ and an output port P ₂ ). Field effect transistor), and FET ₂ inserted in series between P ₁ and ground, and when P ₁ and P ₂ are on, the equivalent circuit is The CR circuit as shown in FIG.

One of the characteristics required for this switch IC is an insertion loss characteristic. The insertion loss of the switch IC is represented by the sum of DC resistance loss and AC capacitance loss. Therefore, it is important for the switch IC to reduce the on-resistance R3 of the FET ₁ in order to suppress DC resistance loss, and to reduce the off-capacitance C1 of the FET ₂ in order to suppress AC capacitance loss. It can be said that it is important.

In addition, not only the insertion loss characteristic but also the distortion characteristic has become important as the system is changed from the second generation to the third generation mobile phone. For example, as shown in FIG. 26, the front-end unit of a future mobile phone is a multi _- function system in which a second generation GSM system (S _GSM ) and a third generation W-CDMA system (S _W-CDMA ) are mixed. It may be a mode and multi-band system, or a multi-band system of only a third generation W-CDMA system (S _W-CDMA ) (not shown).

In a system for selecting transmission / reception signals by duplexer DPX, such as SW _-CDMA adopted in third-generation mobile phones, if a switch SW ₁ having non-linearity is used, interference waves existing in the atmosphere and transmission are transmitted. The wave is mixed and intermodulation distortion (IMD) is generated, which causes a problem of entering the reception path R _x1 . For example, the transmission wave (f _TX1 ) is 1.95 GHz and the reception wave (f _RX1 ) is 2.14 GHz. It is assumed that the duplexer DPX passes only signals of these two frequencies. Here, it is assumed that an interference wave (f _block ) of 190 MHz enters from the antenna ANT. The non-linearity of the switch SW ₁ causes frequency mixing, and a secondary IMD signal of f _IMD = f _TX1 + f _block = 1.95 GHz + 190 MHz = 2.14 GHz is generated. Since the frequency of the secondary IMD signal is the same as that of the received wave (f _RX1 ), the secondary IMD signal passes through the duplexer DPX and enters the reception path R _x1 as noise. Although harmonics generated by the nonlinear properties of the switch SW _1, a problem of the harmonic distortion is raised as one of the problems second generation mobile phone system.

In order to solve these distortion problems, it is considered effective to suppress the non-linearity of the off capacitance C ₁ of the FET ₂ . As an example to support this, it can be estimated from the simulation results shown in FIGS. 27 (A) and 27 (B). FIGS. 27A and 27B are spectra of reflected waves when two waves (f _TX1 and f _block ) having different frequencies are input to the capacitor at the same time. FIG. FIG. 27B shows the result of a non-linear capacitor whose capacitance depends on the voltage.

27A and 27B, even if two waves having different frequencies are put into a linear capacitor, only a reflected wave having the same frequency as the input wave is output, but the capacitance depends on the voltage, for example, the capacitance is It can be seen that IMD and harmonic distortion occur when two waves with different frequencies are put into the capacitor (nonlinear capacitance proportional to the voltage). From this, it can be said that the non-linearity of the off-capacitance C ₁ of the FET ₂ is one of the factors that generate IMD and harmonics.

Therefore, the following three points are important in order to provide a high-performance switch IC with low insertion loss and low IMD and harmonic distortion.
(1) Reduction of on-resistance R3 of FET1 (2) Reduction of off-capacitance C1 of FET2 (3) Reduction of non-linearity of off-capacitance C1 of FET2

By the way, as one of switch ICs for wireless communication devices, there is a pn junction gate type FET adopting a pHEMT (pseudomorphic high electron mobility transistor) process. This pn junction gate type FET has a parasitic capacitance C _gs between the gate and source, a parasitic capacitance C _gd between the gate and drain, and a parasitic capacitance C _ds between the drain and source. The off capacitance (C _off ) of this FET is From FIG. 28, it can be expressed as number (1).

From equation (1), it can be seen that the parasitic capacitances C _gs , C _gd and C _ds need to be reduced in order to reduce C _off . It can also be seen that it is important to suppress the non-linearity of the parasitic capacitances C _gs , C _gd and C _ds in order to suppress the non-linearity of C _off .

A pn junction gate type FET is disclosed in, for example, Patent Document 1.
Japanese Patent No. 3675078

So far, there has been reported a method of reducing the parasitic capacitance C _gd while suppressing an increase in on-resistance as much as possible in a pn junction gate type FET. This is to provide a trench between the gate and drain.

Specifically, after the buffer layer 1011, the lower doping layer 1012, the lower spacer layer 1013, the channel layer 1014, the upper spacer layer 1015, the upper doping layer 1016, and the diffusion layer 1017 are epitaxially stacked in this order on the substrate 1010, An insulating film 1018A is stacked thereover (FIG. 29A). Next, a resist layer R1 having an opening in a portion corresponding to a trench 1019 described later is formed over the insulating film 1018A by a lithography process (FIG. 29B). Then, using the resist layer R1 as a mask, a portion corresponding to the trench 1019 of the insulating film 1018A is etched by a reactive ion etching (RIE) method using, for example, a mixed gas obtained by adding H ₂ or O ₂ to CF ₄ . After that, a portion corresponding to the trench 1019 of the diffusion layer 1017 is etched by the RIE method or the wet etching method to form the trench 1019 (FIG. 30A).

  Next, after removing the resist layer R1, an insulating film 1018B is formed over the entire surface including the trench 1019 (FIG. 30B). Subsequently, a resist layer R2 having an opening in a portion corresponding to a gate region 1020 described later is formed over the insulating film 1018B by a lithography process (FIG. 31A). Then, using the resist layer R2 as a mask, portions of the insulating films 1018A and 1018B corresponding to the gate regions 1020 are etched by RIE to form openings 1018D (FIG. 31B). As a result, the diffusion layer 1017 is exposed at the bottom of the opening 1018D.

  Next, after removing the resist layer R2, the substrate 1010 is placed in a diffusion furnace (not shown) and heated to a temperature of around 600 ° C. in an atmosphere containing diethyl zinc (DEZ) and arsenic (As). Zn which is a p-type impurity is diffused into the diffusion layer 1017 through the opening 1018D to form a p-type gate region 1020 (FIG. 32A). Subsequently, a gate electrode 1021 made of a Ti / Pt / Au film is formed over the gate region 1020 through the opening 1018D (FIG. 32B).

  Next, an insulating film 1018C is formed over the entire surface including the gate electrode 1021, and the insulating layer 1018 is formed together with the insulating films 1018A and 1018B (FIG. 33A). Thereafter, a predetermined portion of the insulating layer 1018 is etched to form two openings (not shown), and the source electrode 1022 and the drain electrode made of AuGe / Ni / Au film are formed on the diffusion layer 1017 through these openings. 1023 is formed (FIG. 33B). Subsequently, a reaction region 1024 that electrically connects the source electrode 1022 and the drain electrode 1023 and the channel layer 1014 to each other is formed by alloying. In this way, the conventional pn junction gate type FET is manufactured.

Thus, in the pn junction gate type FET, by providing the trench 1019 between the gate and the drain, the resistance rises only in the portion immediately below the trench 1019, and the rise of the on-resistance can be suppressed as much as possible. Further, as shown in FIG. 34, by providing the trench 1019 in between the gate and the drain, it is possible to reduce the parasitic capacitance C _gd, further less voltage dependence of the parasitic capacitance C _gd, parasitic capacitance C _gd is There is an almost constant voltage range (the circled range in the figure). Therefore, it can be seen that in this range, the nonlinearity of the parasitic capacitance C _gd is suppressed.

From these facts, it can be said that it is preferable to provide a trench in order to provide a high-performance switch IC with low insertion loss and low IMD and harmonic distortion. Here, the following two points are key when providing the trench.
(1) The distance La between the gate electrode 1021 and the trench 1019 is short. (2) The opening width Lb of the trench 1019 is narrow.

  Although the shortest distance La is theoretically zero, in order to make the distance La zero, it is necessary to provide the trench 1019 in contact with the gate electrode 1021. However, as described above, the resist layer R1 used to form the trench 1019 and the resist layer R2 used to form the gate electrode 1021 cannot be shared, and need to be formed separately. Therefore, the distance La can be reduced only to about 0.2 μm by the current mass production technology because of the alignment accuracy. Further, the opening width Lb of the trench 1019 depends on the opening capability of the stepper, and can only be reduced to about 0.4 μm in the i-line stepper. Therefore, the above-described manufacturing method has a problem that it is not easy to mass-produce pn junction gate type FETs having an ideal trench structure.

  The present invention has been made in view of such a problem, and a first object of the present invention is to make the distance between the gate electrode and the trench zero without depending on the alignment accuracy. An object of the present invention is to provide a method of manufacturing a field effect transistor capable of narrowing the opening width of a trench without depending on the opening capability. A second object is to provide a field effect transistor with low insertion loss and low IMD and harmonic distortion.

The manufacturing method of the field effect transistor of the present invention includes the following steps (A) to (E).
(A) Step of forming an insulating film on the semiconductor layer (B) After forming a first mask having a first opening of a predetermined size on the insulating film, an exposed portion in the first opening of the insulating film (C) forming a second mask having a second opening smaller than the first opening corresponding to the exposed portion of the semiconductor layer after removing the first mask (D) A step of forming a gate electrode at a portion of the second opening and removing the second mask (E) A portion of the semiconductor layer directly under the gate electrode is etched by etching the semiconductor layer using the insulating film and the gate electrode as a mask. Forming trenches on both sides of the portion directly under the gate electrode

  In the field effect transistor manufacturing method of the present invention, a pair of trenches is formed by etching a semiconductor layer using an insulating film and a gate electrode as a mask.

  The field effect transistor of the present invention is configured by arranging a source electrode, a gate electrode, and a drain electrode in this order on a semiconductor layer. This transistor has a pair of trenches between a gate electrode and a source electrode and between a gate electrode and a drain electrode in a semiconductor layer, and these trenches are located in a portion of the semiconductor layer immediately below the gate electrode. Touching.

  In the field effect transistor of the present invention, a pair of trenches formed between the gate electrode and the source electrode and between the gate electrode and the drain electrode are in contact with a portion immediately below the gate electrode.

  According to the method for manufacturing a field effect transistor of the present invention, the semiconductor layer is etched using the insulating film and the gate electrode as a mask to form the pair of trenches. Therefore, the alignment between the gate electrode and the pair of trenches is performed. Without this, a pair of trenches can be formed in contact with the portion directly under the gate electrode. Further, since the insulating film and the gate electrode are used as a mask when forming the trench, the opening width of the trench and thus the width between the inner walls of the trench can be reduced without depending on the opening ability of the stepper.

  According to the field effect transistor of the present invention, the pair of trenches formed between the source electrode and the drain electrode and the gate electrode are provided in contact with the portion immediately below the gate electrode. Insertion loss can be reduced, and IMD and harmonic distortion can also be reduced. In particular, when the pair of trenches is formed using the above manufacturing method, the pair of trenches can be provided in exact contact with the portion directly under the gate electrode without depending on the alignment accuracy. The trench opening width can be reduced without depending on the opening capability, which can greatly reduce insertion loss, IMD, and harmonic distortion.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 shows a cross-sectional configuration of a field effect transistor 1 according to a first embodiment of the present invention. This field effect transistor 1 is a pn junction gate type FET adopting a pHEMT process, and a buffer layer 11, a lower doping layer 12, a lower spacer layer 13, a channel layer 14, an upper spacer layer 15, The upper doping layer 16 and the diffusion layer 17 are epitaxially stacked in this order.

  The substrate 10 is a semi-insulating substrate, for example, a GaAs substrate. The buffer layer 11 is formed on the surface of the substrate 10 in order to improve crystal growth. For example, the buffer layer 11 is formed by alternately and repeatedly laminating AlGaAs and GaAs. The buffer layer 11 is formed on the uppermost layer of this periodic structure. GaAs is formed. The lower doped layer 12 is made of, for example, n-type AlGaAs, the lower spacer layer 13 is made of, for example, undoped AlGaAs, the channel layer 14 is made of, for example, undoped InGaAs, the upper spacer layer 15 is made of, for example, undoped AlGaAs, and the upper doped layer 16 is made of, for example, The diffusion layer 17 is made of, for example, AlGaAs.

  In this field effect transistor 1, a gate electrode 21, a source electrode 22 and a drain electrode 23 are provided on the diffusion layer 17. The source electrode 22 and the drain electrode 23 are provided on both sides of the gate electrode 21 with a predetermined interval. A reaction region 24 is formed in a region of the upper spacer layer 15, the upper doping layer 16, and the diffusion layer 17 that faces the source electrode 22 and the drain electrode 23. A contact with the channel layer 14 can be made through the.

  Here, the gate electrode 21 is configured by stacking Ti, Pt, and Au in this order, and the source electrode 22 and the drain electrode 23 are configured by stacking AuGe, Ni, and Au in this order. As will be described later, the reaction region 24 is formed by forming the source electrode 22 and the drain electrode 23 on the diffusion layer 17 and then performing alloying.

  In the field effect transistor 1, a gate region 20 is formed in a portion of the diffusion layer 17 immediately below the gate electrode 21, and the upper portion of the gate region 20 is in contact with the lower portion of the gate electrode 21. The gate region 20 is made of, for example, p-type AlGaAs, and is formed by introducing a p-type impurity (for example, Zn) into the surface of the diffusion layer 17 as will be described later. The width (gate length) Lg of the gate region 20 may be equal to the width L3 of the gate electrode 21, but is preferably narrower than that. 1 illustrates a case where the gate length Lg is narrower than the width L3 of the gate electrode 21.

  A pair of trenches 19 are formed on both sides of the gate region 20 (specifically, between the gate region 20 and the source electrode 22 and between the gate region 20 and the drain electrode 23). The trench 19 is formed in contact with the gate region 20 that is a portion immediately below the gate electrode 21. That is, the distance La between the gate electrode 21 and the trench 19 is zero. The opening width Lb of the trench 19 may be wider than the width L3 of the gate electrode 21, but is preferably equal to the width L3 of the gate electrode 21 and more preferably narrower than that. The depth of the trench 19 may be shallower than the depth of the gate region 20, but is preferably equal to the depth of the gate region 20, and more preferably deeper than that. FIG. 1 illustrates a case where the depth of the trench 19 is deeper than the depth of the gate region 20.

  An insulating layer 18 is formed on the entire surface opposite to the substrate 20. The insulating layer 18 extends to the internal space of the pair of trenches 19, and the internal space of the trench 19 is filled with an insulating material constituting the insulating layer 18. The gate region 20 and the gate electrode 21 are entirely embedded in the insulating layer 18. The side surfaces of the source electrode 22 and the drain electrode 23 are covered with the insulating layer 18. Here, the insulating layer 18 is made of a material having a low dielectric constant, and is preferably made of a material having a dielectric constant lower than that of silicon nitride. In that case, the parasitic capacitance can be greatly reduced.

  The field effect transistor 1 having such a configuration can be manufactured, for example, as follows.

  2 and 3 are flowcharts showing an example of the manufacturing method of the field effect transistor 1 of the present embodiment. 4 to 9 are cross-sectional configuration diagrams for explaining the manufacturing process.

  First, the buffer layer 11, the lower doping layer 12, the lower spacer layer 13, the channel layer 14, the upper spacer layer 15, the upper doping layer 16, and the diffusion layer 17 are formed on the substrate 10 in this order by the molecular beam epitaxy (MBE) method. Then, after epitaxially laminating by metal organic chemical vapor deposition (MOCVD, MOVPE) or the like, an insulating film 18A is laminated thereon by CVD (Chemical Vapor Deposition) or the like (S1, FIG. 4A). Next, a resist layer R1 having an opening H1 having an opening diameter L1 (> Lg) is formed on the insulating film 18A in a portion where the gate region 20A (see FIG. 5B) is to be formed (lithography process) (see FIG. 5). S2, FIG. 4 (B)). Note that the opening diameter L1 is preferably a size that takes into account the alignment accuracy when forming an opening H2 described later in the gate region 20A.

Next, using the resist layer R1 as a mask, the insulating film 18A is selectively etched by reactive ion etching (RIE), for example, using a mixed gas in which H ₂ or O ₂ is added to CF ₄ , thereby insulating the insulating film 18A. An opening is formed in the film 18A (S3, FIG. 5A). Thereby, the diffusion layer 17 is exposed at the bottom of the opening of the insulating film 18A.

  Next, after removing the resist layer R1, using the insulating film 18A as a mask, vapor diffusion is performed on the exposed portion of the diffusion layer 17 using diethyl zinc (DEZ), which is an organometallic compound of Zn, to introduce Zn. Then, the gate region 20A is formed in the exposed portion of the diffusion layer 17 (S4, FIG. 5B).

  Next, a resist layer R2 having an opening H2 having an opening diameter L2 (Lg ≦ L2 <L1) is formed in a portion corresponding to the gate region 20A by a lithography process (S5, FIG. 6A). At this time, when the opening H2 is provided in the central portion of the gate region 20A, the opening H3 described later is formed symmetrically on both sides of the gate electrode 21, so that the pair of trenches 19 are formed symmetrically. Can do. If it is desired to form the pair of trenches 19 asymmetrically, the opening H2 may be provided in a portion other than the central portion of the gate region 20A.

  Next, after forming a Ti / Pt / Au metal film on the entire surface including the opening H2, the resist layer R2 is peeled off by lift-off to form the gate electrode 21 at the site of the opening H2 (S6, FIG. 6). (B)). At this time, the width L3 of the gate electrode 21 is equal to the opening diameter L2 of the opening H2. Further, an opening H3 is formed on both sides of the gate electrode 21 with the lift-off. As a result, the gate region 20A is exposed at the bottom of the opening H3.

  Next, using the gate electrode 21 and the insulating film 18A as a mask, the gate region 20A is etched through the opening H3 to form a pair of trenches 19 on both sides of the gate electrode 21, and the gate region 20 is formed immediately below the gate electrode 21. It forms (S7, FIG. 7 (A)). At this time, for example, when isotropic etching is performed using citric acid or the like, the portion immediately below the gate electrode 21 is slightly cut, so that the width (gate length) Lg of the gate region 20 is larger than the width L3 of the gate electrode 21. Narrow. Thus, the gate length Lg can be narrowed by using an isotropic etching method when forming the pair of trenches 19. Note that when anisotropic etching is performed using, for example, the RIE method, the portion immediately below the gate electrode 21 is hardly etched, so that the width (gate length) Lg of the gate region 20 is equal to the width L3 of the gate electrode 21. You can also

  When the trench 19 is formed, if it is desired to control the depth of the trench 19 by the structure, an etching stop layer (not shown) made of AlGaAs or InGaP having a high Al composition is provided in the diffusion layer 17. It is preferable to keep.

  Next, an insulating film 18B is formed on the entire surface including the trench 19 by a CVD method or the like (S8, FIG. 7B). As a result, the trench 19 is filled with an insulating material. Further, since the insulating layer 18 is formed together with the insulating film 18A, the gate electrode 21 is embedded in the insulating layer 18.

  Next, a resist layer R3 having openings in portions where the source electrode 22 and the drain electrode 23 are formed is formed on the insulating layer 18 by a lithography process (S9, FIG. 8A). Thereafter, using the resist layer R3 as a mask, the insulating layer 18 is selectively etched by RIE to form two openings in the insulating layer 18 (S10, FIG. 8B). As a result, the diffusion layer 17 is exposed at the bottom of each opening.

  Next, after an AuGe / Ni / Au metal film is formed on the entire surface including the exposed portion of the diffusion layer 17, the resist layer R3 is peeled off by lift-off, and a source electrode 22A and a drain electrode 23A are formed at the site of the opening. (S11, FIG. 9A). Subsequently, after alloying is performed to form the reaction region 24 (S12, FIG. 9B), the surface is flattened (S13, FIG. 1). In this way, the field effect transistor 1 of the present embodiment is formed.

  In the method of manufacturing the field effect transistor 1 according to the present embodiment, the pair of trenches 19 are formed by etching the diffusion layer 17 using the insulating film 18A and the gate electrode 21 as a mask. Without aligning with the pair of trenches 19, the pair of trenches 19 can be formed in contact with the gate region 20 immediately below the gate electrode 21. Further, since the insulating film 18A and the gate electrode 21 are used as a mask when forming the trench 19, the opening width Lb (opening diameter of the opening H3) of the trench 19 is reduced without depending on the opening capability of the stepper. be able to.

As a result, in the field effect transistor 1 of the present embodiment, the pair of trenches 19 are provided in exact contact with the gate region 20 immediately below the gate electrode 21, and the distance La between the gate electrode 21 and the trench 19 is zero. Therefore, it is possible to reduce the parasitic capacitances C _gs and C _gd while suppressing an increase in on-resistance as much as possible. Furthermore, voltage dependence (nonlinearity) of the parasitic capacitances C _gs and C _gd can be reduced. As a result, insertion loss, IMD, and harmonic distortion with respect to an input signal from the source electrode 22 or the drain electrode 23 can be reduced.

  By the way, for example, when the opening capability of the i-line stepper is about 0.4 μm, the width L3 of the gate electrode 1021 and the opening diameter Lb of the trench 1019 can be narrowed only to about 0.4 μm by the conventional method. could not. Further, the distance La between the gate electrode 1021 and the trench 1019 can be reduced only to about 0.2 μm by the current mass production technique because of the alignment accuracy. Therefore, conventionally, the on-resistance cannot be effectively reduced.

  On the other hand, in this embodiment, since the opening width Lb (opening diameter of the opening H3) of the trench 19 can be narrowed (for example, about 0.25 μm) without depending on the opening ability of the stepper, the on-resistance is effective. Can be reduced. Thereby, insertion loss can be further reduced.

  In the present embodiment, by using an isotropic etchant when forming the trench 19, the gate length Lg can be made smaller than the width L3 of the gate electrode 21, so that the gate length Lg is reduced to the gate electrode 21. The upper limit of the frequency that can be handled can be increased compared to the case where the width L3 is equal to or larger than the width L3.

  Hereinafter, other embodiments different from the above-described embodiment will be described. However, in the following, configurations, operations, and effects different from those in the above embodiment will be described in detail, and descriptions of configurations, operations, and effects similar to those in the above embodiment will be omitted as appropriate.

[Second Embodiment]
FIG. 10 shows a cross-sectional configuration of the field effect transistor 2 according to the second embodiment of the present invention. The field effect transistor 2 of the present embodiment has a transistor layer structure formed by performing selective ion implantation or the like on the substrate 30, and the transistor layer structure is formed by epitaxial growth on the substrate 10. This is different from the above embodiment.

  This field effect transistor 2 includes a channel layer 31, an ohmic contact layer 32 and a buried layer 33 formed by ion implantation, and a gate region 35 formed by vapor phase diffusion in a substrate 30.

The substrate 30 is a semi-insulating substrate, for example, a GaAs substrate. The channel layer 31 is formed by selectively ion-implanting Si into the surface layer on one side of the substrate 30 with, for example, an acceleration voltage of 80 kV and a dose of 1.5 × 10 ¹³ cm ⁻² . The ohmic contact layer 32 is a surface layer on one side of the substrate 30, and is formed on both sides of the channel layer 31 in contact with the channel layer 31. The ohmic contact layer 32 is formed deeper than the channel layer 31. For example, the ohmic contact layer 32 is formed by selective ion implantation of Si into the surface of the substrate 30 at an acceleration voltage of 150 kV and a dose of 3 × 10 ¹³ cm ^−2. ing. The buried layer 33 is formed at the boundary between the region where the channel layer 31 and the ohmic contact layer 32 are formed in the substrate 30 and the region where these are not formed. It is formed so as to cover the bottom and side surfaces. The buried layer 33 is formed by, for example, selective ion implantation of Mg into the surface of the substrate 30 at an acceleration voltage of 220 kV and a dose of 1.2 × 10 ¹² cm ⁻² . The gate region 35 is formed on the surface layer of the channel layer 31 by selectively performing vapor phase diffusion.

  In the field effect transistor 2, a gate electrode 36 is provided on the gate region 35, and a source electrode 38 and a drain electrode 39 are provided on the channel layer 31, respectively. The source electrode 38 and the drain electrode 39 are provided on both sides of the gate electrode 36 at a predetermined interval. Here, the gate electrode 36 is configured by stacking Ti, Pt, and Au in this order, and the source electrode 38 and the drain electrode 39 are configured by stacking AuGe, Ni, and Au in this order.

  In the field effect transistor 2, a pair of trenches 37 are formed on both sides of the gate electrode 36 (specifically, between the gate electrode 36 and the source electrode 38 and between the gate electrode 36 and the drain electrode 39). 36 in contact with. That is, the distance La between the gate electrode 36 and the trench 37 is zero. The opening width Lb of the trench 37 may be wider than the width L6 of the gate electrode 36, but is preferably equal to the width L6 of the gate electrode 36, and more preferably narrower than that. The depth of the trench 37 may be shallower than the bottom surface of the gate region 35 immediately below the gate electrode 36, but is preferably equal to the bottom surface of the gate region 35, and more preferably deeper than that. FIG. 10 illustrates a case where the depth of the trench 37 is deeper than the bottom surface of the gate region 35.

  When the depth of the trench 37 is deeper than the bottom surface of the gate electrode 36, the width (gate length) Lg of the gate region 35 may be equal to the width L3 of the gate electrode 45, but more than that. It is preferable that it is narrow. FIG. 10 illustrates a case where the gate length Lg is narrower than the width L6 of the gate electrode 21.

  An insulating layer 34 is formed on the entire surface opposite to the substrate 30. The insulating layer 34 extends to the internal space of the pair of trenches 37, and the internal space of the trench 37 is filled with an insulating material that constitutes the insulating layer 34. The gate electrode 36 and the gate region 35 immediately below the gate electrode 36 are entirely embedded in the insulating layer 34. The side surfaces of the source electrode 38 and the drain electrode 39 are covered with an insulating layer 34. Here, the insulating layer 34 is made of a material having a low dielectric constant, and is preferably made of a material having a dielectric constant lower than that of silicon nitride. In that case, the parasitic capacitance can be greatly reduced.

  The field effect transistor 2 having such a configuration can be manufactured, for example, as follows.

FIG. 11 to FIG. 14 are cross-sectional configuration diagrams for explaining a manufacturing process of the field effect transistor 1 of the present embodiment. First, after selective ion implantation of Si into a predetermined region of the surface of the substrate 30 with an acceleration voltage of 80 kV and a dose of 1.5 × 10 ¹³ cm ⁻² , for example, an acceleration voltage of 150 kV and a dose of 3 × 10 ¹³ cm ^−2. Then, selective ions are implanted into both sides of the region where Si is ion-implanted first, and further, for example, selective ions are implanted into the surface into which Mg is ion-implanted at an acceleration voltage of 220 kV and a dose of 1.2 × 10 ¹² cm ⁻² . Thereafter, the substrate 30 is placed in, for example, AsH ₃ / Ar / H ₂ gas, and heated to 840 degrees to perform capless annealing, whereby the channel layer 31, the ohmic contact layer 32, and the buried layer 33 are formed on the surface layer of the substrate 30. (FIG. 11A).

  Next, after the insulating film 34A is laminated on the entire surface by CVD or the like (FIG. 11B), an opening diameter L4 (> Lg) is formed in a portion where the gate electrode 36 and the trench 37 are to be formed on the insulating film 34A. The resist layer R4 having the opening H4 is formed by a lithography process (FIG. 11C). Note that the opening diameter L4 is preferably set in consideration of alignment accuracy when forming an opening H5 described later in the gate region 35A.

  Next, with the resist layer R4 as a mask, the insulating film 34A is selectively etched by RIE to form an opening in the insulating film 34A (FIG. 12A). As a result, the channel layer 31 is exposed at the bottom of the opening of the insulating film 34A.

  Next, after removing the resist layer R4, using the insulating film 34A as a mask, gas phase diffusion is performed on the exposed portion of the channel layer 31 using diethyl zinc (DEZ) to introduce Zn, thereby exposing the exposed portion of the channel layer 31. Then, a gate region 35A is formed (FIG. 12B).

  Next, a resist layer R5 having an opening H5 having an opening diameter L5 (Lg ≦ L5 <L4) is formed in a portion corresponding to the gate region 35A by a lithography process (FIG. 12C). At this time, when the opening H5 is provided in the central portion of the gate region 35A, an opening H6 described later is formed symmetrically on both sides of the gate electrode 36, so that the pair of trenches 37 are formed symmetrically. Can do. If it is desired to form the pair of trenches 37 asymmetrically, the opening H5 may be provided in a portion other than the central portion of the gate region 35A.

  Next, after a Ti / Pt / Au metal film is formed on the entire surface including the opening H6, the resist layer R5 is peeled off by lift-off to form a gate electrode 36 at the site of the opening H6 (FIG. 13A). )). At this time, the width L6 of the gate electrode 36 is equal to the opening diameter L5 of the opening H5. Further, an opening H6 is formed on both sides of the gate electrode 36 along with the lift-off. Thereby, the channel layer 31 is exposed at the bottom of the opening H6.

  Next, using the gate electrode 36 and the insulating film 34A as a mask, the channel layer 31 is etched through the opening H6 to form a pair of trenches 37 on both sides of the gate electrode 36, and a gate region 35 is formed immediately below the gate electrode 36. It is formed (FIG. 13B). At this time, for example, when isotropic etching is performed using citric acid or the like, the portion immediately below the gate electrode 36 is slightly cut, so the width (gate length) Lg of the portion (gate region 35) immediately below the gate electrode 36 is reduced. It becomes narrower than the width L6 of the gate electrode. Thus, the gate length Lg can be narrowed by using an isotropic etching method when forming the pair of trenches 37. For example, when anisotropic etching is performed using the RIE method or the like, the portion immediately below the gate electrode 36 is hardly etched, so the width (gate length) Lg of the portion (gate region 35) immediately below the gate electrode 36 is set to be small. It can be made equal to the width L6 of the gate electrode.

  When forming the trench 37, if it is desired to control the depth of the trench 37 by a structure, an etching stop layer (not shown) made of AlGaAs, InGaP or the like having a high Al composition is provided in the channel layer 31. It is preferable to keep.

  Next, an insulating film 34B is formed over the entire surface including the trench 37 by a CVD method or the like (FIG. 13C). As a result, the trench 37 is filled with an insulating material. Further, since the insulating layer 34 is formed together with the insulating film 34A, the gate electrode 36 is embedded in the insulating layer 34.

  Next, a resist layer R6 having openings in portions where the source electrode 38 and the drain electrode 39 are formed is formed on the upper surface of the insulating layer 34 by a lithography process (FIG. 14A). Thereafter, the insulating layer 34 is selectively etched by RIE using the resist layer R6 as a mask (FIG. 14B). As a result, the ohmic contact layer 32 is exposed at the bottom of the opening of the insulating layer 34.

  Next, after an AuGe / Ni / Au metal film is formed on the entire surface including the exposed portion of the ohmic contact layer 32, the resist layer R6 is peeled off by lift-off, and the source electrode 38A and the drain electrode 39A are formed at the openings. It is formed (FIG. 14C). Subsequently, alloying is performed to make contact between the source electrode 38A and drain electrode 39A and the ohmic contact layer 32, and then the surface is planarized (FIG. 10). In this manner, the field effect transistor 2 of the present embodiment is formed.

  In the method of manufacturing the field effect transistor 2 of the present embodiment, the channel layer 31 is etched using the insulating film 34A and the gate electrode 36 as a mask to form the pair of trenches 37. Without aligning with the pair of trenches 37, the pair of trenches 37 can be formed in contact with the gate electrode 36 and the gate region 35 immediately below the gate electrode 36. Further, since the insulating film 34A and the gate electrode 36 are used as a mask when forming the trench 37, the opening width Lb (opening diameter of the opening H6) of the trench 37 is reduced without depending on the opening capability of the stepper. be able to.

As a result, in the field effect transistor 2 of the present embodiment, the pair of trenches 37 is accurately provided in contact with the gate electrode 36 and the gate region 35 immediately below the gate electrode 36, and the distance La between the gate electrode 36 and the trench 37 is Since it is zero, it is possible to reduce the parasitic capacitances C _gs and C _gd while suppressing an increase in on-resistance as much as possible. Furthermore, voltage dependence (nonlinearity) of the parasitic capacitances C _gs and C _gd can be reduced. As a result, insertion loss, IMD, and harmonic distortion with respect to the input signal from the source electrode 38 or the drain electrode 39 can be reduced.

  Furthermore, in this embodiment, the on-resistance can be effectively reduced because the opening width Lb of the trench 37 (opening diameter of the opening H3) can be narrowed (for example, about 0.25 μm) without depending on the opening ability of the stepper. Can be reduced. Thereby, insertion loss can be further reduced.

  Further, in the present embodiment, by using an isotropic etchant when forming the trench 37, the gate length Lg can be made narrower than the width L6 of the gate electrode 36, so that the gate length Lg is reduced to the gate electrode 36. The upper limit of the frequency that can be handled can be increased compared to the case where the width L3 is equal to or larger than the width L3.

[Third Embodiment]
FIG. 15 illustrates a cross-sectional configuration of a field effect transistor 3 according to the third embodiment of the present invention. The field effect transistor 3 of the present embodiment is a Schottky gate type FET in which a gate electrode 45 is formed on the surface of a barrier layer 40 (described later) on the upper doping layer 16, and in that respect, on the gate region 20. This is different from the first embodiment, which is a pn junction gate type FET in which the gate electrode 21 is formed.

  The field effect transistor 3 includes a buffer layer 11, a lower doping layer 12, a lower spacer layer 13, a channel layer 14, an upper spacer layer 15, an upper doping layer 16, a barrier layer 40, and a first cap layer on one surface side of the substrate 10. 41, the etching stop layer 42 and the second cap layer 43 are epitaxially laminated in this order.

  The barrier layer 40 is made of, for example, undoped AlGaAs, the first cap layer 41 is made of, for example, undoped GaAs, the etching stop layer 42 is made of, for example, undoped AlGaAs, and the second cap layer 43 is made of, for example, n-type GaAs.

  The field effect transistor 3 also includes a gate electrode 45, a source electrode 47 and a drain electrode 48. The gate electrode 45 is provided on the barrier layer 40 exposed by selectively etching the second cap layer 43, the etching stop layer 42, and the first cap layer 41, and the source electrode 47 and the drain electrode 48 are the second one. It is provided on the cap layer 43. The source electrode 47 and the drain electrode 48 are provided on both sides of the gate electrode 45 at a predetermined interval. In the upper spacer layer 15, the upper doping layer 16, the barrier layer 40, the first cap layer 41, the etching stop layer 42, and the second cap layer 43, a reaction region 49 is formed in a region facing the source electrode 47 and the drain electrode 48. The source electrode 47 and the drain electrode 48 are in contact with the channel layer 14 through the reaction region 49.

  Here, the gate electrode 45 is configured by stacking Ti, Pt, and Au in this order, and the source electrode 47 and the drain electrode 48 are configured by stacking AuGe, Ni, and Au in this order. As will be described later, the reaction region 49 is formed by forming the source electrode 47 and the drain electrode 48 on the second cap layer 43 and then performing alloying.

  In this field effect transistor 3, a pair of trenches 46 are formed on both sides of the gate electrode 45 (specifically, between the gate electrode 45 and the source electrode 47 and between the gate electrode 45 and the drain electrode 48). 45 is formed in contact with. That is, the distance La between the gate electrode 45 and the trench 46 is zero. The opening width Lb of the trench 46 may be wider than the width L9 of the gate electrode 45, but is preferably equal to the width L9 of the gate electrode 45, and more preferably narrower than that. Further, the depth of the trench 46 is deeper than the bottom surface of the gate electrode 45 (see FIG. 15).

  When the depth of the trench 46 is deeper than the bottom surface of the gate electrode 45, the width (gate length) Lg of the portion of the barrier layer 40 immediately below the gate electrode 45 is equal to the width L3 of the gate electrode 45. However, it is preferably narrower than that. FIG. 15 illustrates a case where the gate length Lg is narrower than the width L6 of the gate electrode 21.

  An insulating layer 44 is formed on the surface of the first cap layer 41, the etching stop layer 42, and the second cap layer 43 where the source electrode 47 and the drain electrode 48 are not formed. The insulating layer 44 extends to the internal space of the pair of trenches 46, and the internal space of the trench 46 is filled with an insulating material that constitutes the insulating layer 44. Further, the entire gate electrode 45 and the portion immediately below the gate electrode 45 are embedded in the insulating layer 44. The side surfaces of the source electrode 47 and the drain electrode 48 are covered with an insulating layer 44. Here, the insulating layer 44 is made of a material having a low dielectric constant, and is preferably made of a material having a dielectric constant lower than that of silicon nitride. In that case, the parasitic capacitance can be greatly reduced.

  The field effect transistor 3 having such a configuration can be manufactured, for example, as follows.

  Each semiconductor layer exemplified in the above structure is formed by a molecular beam epitaxy (MBE) method or a metal organic chemical vapor deposition (MOCVD, MOVPE) method.

  First, on the substrate 10, the buffer layer 11, the lower doping layer 12, the lower spacer layer 13, the channel layer 14, the upper spacer layer 15, the upper doping layer 16, the barrier layer 40, the first cap layer 41, the etching stop layer 42, and The second cap layer 43 is epitaxially stacked in this order (FIG. 16A). Thereafter, a resist layer R7 having an opening with a predetermined diameter is formed thereon by a lithography process (FIG. 16B).

  Next, using the resist layer R7 as a mask, the second cap layer 43 is wet etched with, for example, citric acid, and then the etching stop layer 42 is etched (FIG. 17A). Thereby, a part of the first cap layer 41 is exposed. Next, after the insulating film 44A is stacked by CVD or the like (FIG. 17B), an opening having an opening diameter L7 (> Lg) is formed in a portion where the gate electrode 45 and the trench 46 are to be formed on the insulating film 44A. A resist layer R8 having a portion H7 is formed by a lithography process (FIG. 18A). The opening diameter L7 is preferably set to a size that takes into account the alignment accuracy when an opening H8 described later is formed inside the opening H7.

  Next, using the resist layer R8 as a mask, the insulating film 44A is selectively etched by the RIE method to form an opening in the insulating film 44A. Then, for example, citric acid is used in the opening of the etching stop layer 42. The exposed portion is wet etched (FIG. 18B). As a result, the barrier layer 40 is exposed at the bottom of the opening of the insulating film 44A.

  Next, after removing the resist layer R8, a resist layer R9 having an opening H8 having an opening diameter L8 (Lg ≦ L8 <L7) in a portion where the gate electrode 45 is to be formed is formed by a lithography process (FIG. 19 (A)). At this time, when the opening H8 is provided in the central portion of the opening H7, the opening H9 described later is formed symmetrically on both sides of the gate electrode 45, so that the pair of trenches 46 is formed symmetrically. Can do. If it is desired to form the pair of trenches 46 asymmetrically, the opening H8 may be provided in a portion other than the central portion of the opening H7.

  Next, after a Ti / Pt / Au metal film is formed on the entire surface including the opening H8, the resist layer R9 is peeled off by lift-off to form a gate electrode 45 at the site of the opening H9 (FIG. 19B). )). At this time, the width L9 of the gate electrode 45 is equal to the opening diameter L8 of the opening H8. Further, an opening H9 is formed on both sides of the gate electrode 45 along with the lift-off. As a result, the barrier layer 40 is exposed at the bottom of the opening H9.

  Next, using the gate electrode 45 and the insulating film 44A as a mask, the barrier layer 40 is etched through the opening H9 to form a pair of trenches 46 on both sides of the gate electrode 45, and a columnar portion is formed immediately below the gate electrode 45. They are formed (FIG. 20A). At this time, when isotropic etching is performed using, for example, citric acid or the like, the portion immediately below the gate electrode 45 is slightly shaved, so the width (gate length) Lg of the portion immediately below the gate electrode 45 is the width of the gate electrode 45. It becomes narrower than L9. Thus, the gate length Lg can be narrowed by using an isotropic etching method when forming the pair of trenches 46. For example, when anisotropic etching is performed using, for example, the RIE method, the portion immediately below the gate electrode 45 is hardly etched, so the width (gate length) Lg of the portion immediately below the gate electrode 45 is set to the width of the gate electrode 45. It can also be equal to L9.

  When forming the trench 46, if it is desired to control the depth of the trench 46 by the structure, an etching stop layer (not shown) made of AlGaAs, InGaP or the like having a high Al composition is provided in the barrier layer 40. It is preferable to keep.

  Next, an insulating film 44B is formed over the entire surface including the trench 46 by a CVD method or the like (FIG. 20B). As a result, the trench 46 is filled with an insulating material. Further, since the insulating layer 44 is formed together with the insulating film 44 </ b> A, the gate electrode 45 is embedded in the insulating layer 44.

  Next, in the same manner as in the first embodiment, a source electrode 47, a drain electrode 48, and a reaction region 49 are formed (FIG. 15). In this way, the field effect transistor 3 of the present embodiment is formed.

  In the method of manufacturing the field effect transistor 3 according to the present embodiment, the pair of trenches 46 are formed by etching the barrier layer 40 using the insulating film 44A and the gate electrode 45 as a mask. Without aligning with the pair of trenches 46, the pair of trenches 46 can be formed in contact with the gate electrode 45 and the portion immediately below the gate electrode 45. Further, since the insulating film 44A and the gate electrode 45 are used as a mask when forming the trench 46, the opening width Lb (opening diameter of the opening H9) of the trench 46 is reduced without depending on the opening capability of the stepper. be able to.

As a result, in the field effect transistor 3 of the present embodiment, the pair of trenches 46 are provided in exact contact with the gate electrode 45 and the portion immediately below the gate electrode 45, and the distance La between the gate electrode 45 and the trench 46 is zero. Therefore, it is possible to reduce the parasitic capacitances C _gs and C _gd while suppressing an increase in on-resistance as much as possible. Furthermore, voltage dependence (nonlinearity) of the parasitic capacitances C _gs and C _gd can be reduced. As a result, insertion loss, IMD, and harmonic distortion with respect to an input signal from the source electrode 47 or the drain electrode 48 can be reduced.

  Furthermore, in the present embodiment, since the opening width Lb of the trench 46 (opening diameter of the opening H6) can be narrowed (for example, about 0.25 μm) without depending on the opening capability of the stepper, the on-resistance is effective. Can be reduced. Thereby, insertion loss can be further reduced.

  In the present embodiment, the gate length Lg can be made narrower than the width L9 of the gate electrode 45 by using an isotropic etchant when the trench 46 is formed. The upper limit of the frequency that can be handled can be increased compared with the case where the width L9 is equal to or larger than the width L9.

[Fourth Embodiment]
FIG. 21 shows a cross-sectional configuration of a field effect transistor 4 according to the fourth embodiment of the present invention. The field effect transistor 4 of the present embodiment is a pn junction gate type FET having a gate electrode 51 on the surface of a gate layer 50 (described later) formed by epitaxial regrowth on the first cap layer 41. In that respect, unlike the first embodiment, which is a pn junction gate type FET having a gate electrode 21 on the surface of the gate region 21 formed by introducing impurities into the surface of the diffusion layer 17, This is also different from the third embodiment, which is a Schottky gate type FET having a gate electrode 45 on the layer 40.

  In this field effect transistor 4, a pair of trenches 52 are formed on both sides of the gate electrode 51 (specifically, between the gate electrode 51 and the source electrode 47 and between the gate electrode 51 and the drain electrode 48). 51 is formed in contact with. The opening width Lb of the trench 52 may be wider than the width L11 of the gate electrode 51, but is preferably equal to the width L11 of the gate electrode 51, and more preferably narrower than that. The depth of the trench 52 is deeper than the bottom surface of the gate layer 50 immediately below the gate electrode 51.

  The width (gate length) Lg of the gate layer 50 may be equal to the width L11 of the gate electrode 51, but is preferably narrower than that. 20 illustrates a case where the gate length Lg is narrower than the width L11 of the gate electrode 51.

  An insulating layer 53 is formed on the surface opposite to the substrate 10. The insulating layer 53 extends to the internal space of the pair of trenches 52, and the internal space of the trench 52 is filled with an insulating material constituting the insulating layer 53. The gate electrode 51 and the gate layer 50 immediately below the gate electrode 51 are entirely embedded in the insulating layer 53. The side surfaces of the source electrode 47 and the drain electrode 48 are covered with an insulating layer 53. Here, the insulating layer 53 is made of a material having a low dielectric constant, and is preferably made of a material having a dielectric constant lower than that of silicon nitride. In that case, the parasitic capacitance can be greatly reduced.

  The field effect transistor 4 having such a configuration can be manufactured, for example, as follows. Since the steps up to FIG. 18A of the third embodiment are the same, the subsequent steps are mainly described.

A resist having an opening H7 having an opening diameter L7 (> Lg) at a portion where the gate electrode 51 and the trench 52 are to be formed on the insulating film 44A after the insulating film 44A made of, for example, SiO ₂ is laminated by the CVD method or the like. The layer R8 is formed by a lithography process (FIG. 17A). Next, after removing the resist layer R8 (FIG. 22A), a gate layer 50A made of p-type GaAs using, for example, C (carbon) as a dopant is regrown by MOCVD or the like (FIG. 22B). .

  Next, a resist layer R10 having an opening H10 having an opening diameter L10 (Lg ≦ L10 <L7) is formed in a portion where the gate electrode 51 is to be formed by a lithography process (FIG. 23A). At this time, when the opening H10 is provided in the central portion of the gate layer 50A, the opening H11 described later is formed symmetrically on both sides of the gate electrode 51, so that the pair of trenches 52 is formed symmetrically. Can do. If it is desired to form the pair of trenches 52 asymmetrically, the opening H10 may be provided in a portion other than the central portion of the gate layer 50A.

  Next, after forming a Ti / Pt / Au metal film on the entire surface including the opening H8, the resist layer R10 is peeled off by lift-off, and a gate electrode 51 is formed at the site of the opening H10 (FIG. 23B). )). At this time, the width L11 of the gate electrode 51 is equal to the opening diameter L10 of the opening H10. Moreover, the opening part H11 is formed in the both sides of the gate electrode 51 with lift-off. As a result, the gate layer 50A is exposed at the bottom of the opening H11.

  Next, using the gate electrode 51 and the insulating film 44A as a mask, the gate layer 50A (further, the first cap layer 41) is etched through the opening H11 to form a pair of trenches 52 on both sides of the gate electrode 51 (FIG. 24). (A)). As a result, the gate layer 50 is formed immediately below the gate electrode 51. At this time, for example, when isotropic etching is performed using citric acid or the like, the portion immediately below the gate electrode 51 is slightly cut, so that the width (gate length) Lg of the gate layer 50 immediately below the gate electrode 51 is equal to the gate electrode 51. It becomes narrower than the width L11. Thus, the gate length Lg can be narrowed by using an isotropic etching method when forming the pair of trenches 52. Note that when anisotropic etching is performed using, for example, the RIE method, the portion immediately below the gate electrode 51 is hardly etched, so the width (gate length) Lg of the gate layer 50 immediately below the gate electrode 51 is set to the gate electrode 51. It can also be made equal to the width L11.

  When the trench 52 is to be formed and the depth of the trench 52 is to be controlled by the structure, an etching stop layer (not shown) made of AlGaAs, InGaP or the like having a high Al composition is formed in the first cap layer 41. It is preferable to provide it.

  Next, an insulating film 53A is formed over the entire surface including the trench 52 by a CVD method or the like (FIG. 24B). As a result, the trench 52 is filled with an insulating material. In addition, since the insulating layer 53 is formed together with the insulating film 44 </ b> A, the gate electrode 51 is embedded in the insulating layer 53.

  Next, a source electrode 47, a drain electrode 48, and a reaction region 49 are formed in the same manner as in the first embodiment (FIG. 21). In this way, the field effect transistor 4 of the present embodiment is formed.

  In the method of manufacturing the field effect transistor 4 of the present embodiment, the first cap layer 41 is etched using the insulating film 44A and the gate electrode 51 as a mask to form the pair of trenches 52. Then, without aligning with the pair of trenches 52, the pair of trenches 52 can be formed in contact with the gate electrode 51 and the gate layer 50 immediately below the gate electrode 51. Further, since the insulating film 44A and the gate electrode 51 are used as a mask when forming the trench 52, the opening width Lb (opening diameter of the opening H11) of the trench 52 is reduced without depending on the opening capability of the stepper. be able to.

As a result, in the field effect transistor 4 of the present embodiment, the pair of trenches 52 are provided in exact contact with the gate electrode 51 and the gate layer 50 immediately below the gate electrode 51, and the distance La between the gate electrode 51 and the trench 52 is Since it is zero, it is possible to reduce the parasitic capacitances C _gs and C _gd while suppressing an increase in on-resistance as much as possible. Furthermore, voltage dependence (nonlinearity) of the parasitic capacitances C _gs and C _gd can be reduced. As a result, insertion loss, IMD, and harmonic distortion with respect to an input signal from the source electrode 47 or the drain electrode 48 can be reduced.

  Furthermore, in this embodiment, the on-resistance can be effectively reduced because the opening width Lb of the trench 52 (opening diameter of the opening H11) can be narrowed (for example, about 0.25 μm) without depending on the opening capability of the stepper. Can be reduced. Thereby, insertion loss can be further reduced.

  Further, in the present embodiment, by using an isotropic etchant when forming the trench 52, the gate length Lg can be made narrower than the width L11 of the gate electrode 51. Therefore, the gate length Lg is reduced to the gate electrode 51. The upper limit of the frequency that can be handled can be increased compared with the case where the width L11 is equal to or larger than the width L11.

  The present invention has been described with reference to a plurality of embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made.

It is a section lineblock diagram of the field effect transistor concerning a 1st embodiment of the present invention. 2 is a flowchart for explaining a manufacturing process of the field effect transistor of FIG. 1. FIG. 3 is a flowchart for explaining a process subsequent to FIG. 2. FIG. 2 is a cross-sectional configuration diagram of a manufacturing process of the field effect transistor of FIG. 1. FIG. 5 is a cross-sectional configuration diagram of the process subsequent to FIG. 4. FIG. 6 is a cross-sectional configuration diagram of a process continued from FIG. 5. FIG. 7 is a cross-sectional configuration diagram of a process continued from FIG. 6. FIG. 8 is a cross-sectional configuration diagram of a process continued from FIG. 7. FIG. 9 is a cross-sectional configuration diagram illustrating a process continued from FIG. 8. It is a section lineblock diagram of a field effect transistor concerning a 2nd embodiment of the present invention. FIG. 11 is a cross-sectional configuration diagram of a manufacturing process of the field effect transistor of FIG. 10. FIG. 12 is a cross-sectional configuration diagram illustrating a process continued from FIG. 11. FIG. 13 is a cross-sectional configuration diagram of a process continued from FIG. 12. FIG. 14 is a cross-sectional configuration diagram of a step subsequent to FIG. 13. It is a section lineblock diagram of a field effect transistor concerning a 3rd embodiment of the present invention. FIG. 16 is a cross-sectional configuration diagram of a manufacturing process of the field effect transistor of FIG. 15. FIG. 17 is a cross-sectional configuration diagram illustrating a process continued from FIG. 16. FIG. 18 is a cross-sectional configuration diagram of the process following FIG. 17. FIG. 19 is a cross-sectional configuration diagram of a process continued from FIG. 18. FIG. 20 is a cross-sectional configuration diagram illustrating a process continued from FIG. 19. It is a section lineblock diagram of a field effect transistor concerning a 4th embodiment of the present invention. FIG. 22 is a cross-sectional configuration diagram of a manufacturing process of the field effect transistor of FIG. 21. FIG. 23 is a cross-sectional configuration diagram of a process continued from FIG. 22; FIG. 24 is a cross-sectional configuration diagram of a process continued from FIG. 23. It is a schematic block diagram of switch IC, and its equivalent circuit schematic. FIG. 26 is a functional block diagram for explaining an application example of the switch IC of FIG. 25. FIG. 26 is a frequency spectrum diagram of an output signal when signals having a plurality of frequencies are input to the switch IC of FIG. 25. It is an equivalent circuit diagram of the parasitic capacitance inside a field effect transistor. It is a cross-sectional block diagram of the manufacturing process of the conventional field effect transistor. FIG. 30 is a cross-sectional configuration diagram illustrating a process continued from FIG. 29. FIG. 31 is a cross-sectional configuration diagram of a process continued from FIG. 30. FIG. 32 is a cross-sectional configuration diagram of the process following FIG. 31. FIG. 33 is a cross-sectional configuration diagram of a process continued from FIG. 32. It is a characteristic view showing the voltage dependence of the parasitic capacitance Cgd when the trench is provided between the gate and the drain.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1-4 ... Field effect transistor 10, 30 ... Substrate, 11 ... Buffer layer, 12 ... Lower doping layer, 13 ... Lower spacer layer, 14, 31 ... Channel layer, 15 ... Upper spacer layer, 16 ... Upper doping layer, 17 ... Diffusion layer, 18, 34, 44, 53 ... Insulating layer, 18A, 18B, 34A, 34B, 44A, 44B, 53A ... Insulating film, 19, 37, 46, 52 ... Trench, 20, 20A, 35, 35A ... gate region, 21, 36, 45, 51 ... gate electrode, 22, 22A, 38, 38A, 47 ... source electrode, 23, 23A, 39, 39A, 48 ... drain electrode, 24, 49 ... reaction region, 32 ... Ohmic contact layer, 33 ... buried layer, 40 ... barrier layer, 41 ... first cap layer, 42 ... etching stop layer, 43 ... second cap layer, 50, 50A Gate layer, H1, H2, H4, H5, H7, H8 ... opening of resist layer, H3, H6, H9 ... opening between gate electrode and insulating film, La ... distance between gate electrode and trench, Lb ... trench opening width, Lg ... gate length, L1, L2, L4, L5, L7, L8, L10 ... resist layer opening width, L3, L6, L9, L11 ... gate electrode width, R1-R10 ... Resist layer.

Claims (11)

Forming an insulating film on the semiconductor layer;
After forming a first mask having a first opening of a predetermined size on the insulating film, the exposed portion in the first opening of the insulating film is removed to expose the semiconductor layer,
After removing the first mask, a second mask having a second opening smaller than the first opening corresponding to the exposed portion of the semiconductor layer is formed,
Forming a gate electrode at a portion of the second opening and removing the second mask;
Etching the semiconductor layer using the insulating film and the gate electrode as a mask to form trenches in contact with the portion immediately below the gate electrode of the semiconductor layer on both sides of the portion immediately below the gate electrode. A method for manufacturing a transistor. 2. The method of manufacturing a field effect transistor according to claim 1, wherein after forming a metal film on the entire surface including the second opening, a gate electrode is formed at a site of the second opening by lift-off. 3. The gate region containing p or n conductivity type impurities is formed in the exposed portion of the semiconductor layer after the semiconductor layer is exposed and before the first mask is removed. A method for producing the field effect transistor according to 1. The method of manufacturing a field effect transistor according to claim 3, wherein the gate region is formed by vapor phase diffusion. The method of manufacturing a field effect transistor according to claim 3, wherein the gate region is formed by crystal growth. The method of manufacturing a field effect transistor according to claim 3, wherein the trench is formed shallower, equal, or deeper than the gate region. 2. The method of manufacturing a field effect transistor according to claim 1, wherein a width of a portion immediately below the gate electrode is equal to or less than a width of the gate electrode. A field effect transistor comprising a gate electrode on a semiconductor layer, and a source electrode and a drain electrode provided on both sides of the gate electrode,
Of the semiconductor layer, having a pair of trenches provided between the gate electrode and the source electrode and between the gate electrode and the drain electrode,
The trench is provided in contact with a portion of the semiconductor layer immediately below the gate electrode. The field effect transistor according to claim 8, wherein a portion immediately below the gate electrode is a gate region containing p or n conductivity type impurities. The field effect transistor according to claim 9, wherein the trench has a depth shallower than the gate region, a depth equal to the gate region, or a depth deeper than the gate region. The field effect transistor according to claim 8, wherein a width of a portion immediately below the gate electrode is equal to or less than a width of the gate electrode.

Images