JP2009032729A - Switching element and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching element with little IMD and harmonic distortion. <P>SOLUTION: The switching element includes a shunt FET 1A inserted in series with a shunt circuit and a series FET 1B inserted in series with a series circuit. The shunt FET 1A has a gate electrode 30 on a gate region 34 inside a contact layer 17, a source electrode 31 and a drain electrode 32 on both sides of the gate electrode 30 on the contact layer 17, and a pair of recesses 35 on both sides of the gate region 34. The series FET 1B has a gate electrode 41 on a gate region 45 formed on the bottom of a recess 40 inside the contact layer 17 and a source electrode 42 and a drain electrode 43 on both sides of the recess 40 on the contact layer 17. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to one or more first field effect transistors inserted in series between an input end and a ground end, and one or more second field effect transistors inserted in series between an input end and an output end. The present invention relates to a switch element including the above and an electronic device incorporating the same.

  As shown in FIG. 35A, a switch IC used in an RF front end portion of a mobile phone is generally a series-side FET (series-side FET (inserted in series) between an input port Port1 and an output port Port2. Field effect transistor (Field effect transistor) 1 and a shunt-side FET 2 inserted in series between Port 1 and ground. When Port 1 and Port 2 are on, the equivalent circuit is The CR circuit is as shown in FIG.

  One of the characteristics required for this switch IC is an insertion loss characteristic. The insertion loss of the switch IC is represented by the sum of DC resistance loss and AC capacitance loss. Therefore, it is important for the switch IC to reduce the on-resistance R3 of the FET1 in order to suppress DC resistance loss, and it is important to reduce the off-capacitance C1 of the FET2 in order to suppress AC capacitance loss. It can be said that there is.

In addition, not only the insertion loss characteristic but also the distortion characteristic has become important as the system is changed from the second generation to the third generation mobile phone. For example, as shown in FIG. 34, a front-end unit of a future mobile phone is a multi-function that includes a second generation GSM system (S _GSM ) and a third generation W-CDMA system (S _W-CDMA ). It may be a mode and multi-band system, or a multi-band system of only a third generation W-CDMA system (S _W-CDMA ) (not shown).

In a system for selecting transmission / reception signals by the duplexer DPX, such as SW _-CDMA adopted in the third generation mobile phone, if a switch SW ₁ having non-linearity is used, interference waves existing in the atmosphere and transmission are transmitted. The wave is mixed and intermodulation distortion (IMD) is generated, which causes a problem of entering the reception path R _x1 .

For example, the transmission wave (f _TX1 ) is 1.95 GHz and the reception wave (f _RX1 ) is 2.14 GHz. It is assumed that the duplexer DPX passes only signals of these two frequencies. Here, it is assumed that an interference wave (f _block ) of 190 MHz enters from the antenna ANT. The non-linearity of the switch SW ₁ causes frequency mixing, and a secondary IMD signal of f _IMD = f _TX1 + f _block = 1.95 GHz + 190 MHz = 2.14 GHz is generated. Since the frequency of the secondary IMD signal is the same as that of the received wave (f _RX1 ), the secondary IMD signal passes through the duplexer DPX and enters the reception path R _x1 as noise. Although harmonics generated by the nonlinear properties of the switch SW _1, a problem of the harmonic distortion is raised as one of the problems second generation mobile phone system.

In order to solve these distortions problems, it is considered effective to suppress the non-linearity of the OFF capacitance C ₁ of the FET2. As an example to support this, it can be inferred from the simulation results shown in FIGS. FIGS. _36A and 36B are spectra of reflected waves when two waves (f _TX1 and f _block ) having different frequencies are input to the capacitor at the same time. FIG. FIG. 36B shows the result of a non-linear capacitor whose capacitance depends on the voltage.

36A and 36B, even if two waves having different frequencies are put into a linear capacitor, only a reflected wave having the same frequency as the input wave is output, but the capacitance depends on the voltage. It can be seen that IMD and harmonic distortion occur when two waves having different frequencies are put into a capacitor in a non-linear capacitance proportional to the voltage. From this, it can be said that the non-linearity of the off-capacitance C ₁ of the FET 2 is one of the factors that generate IMD and harmonics.

Therefore, the following four points are important in order to provide a high-performance switch IC with low insertion loss and low IMD and harmonic distortion.
(1) Reduction of on-resistance R3 of FET1 (2) Reduction of non-linearity of on-resistance R3 of FET1 (2) Reduction of off-capacitance C1 of FET2 (3) Reduction of non-linearity of off-capacitance C1 of FET2

By the way, as one of switch ICs for wireless communication devices, there is a pn junction gate type FET adopting a pHEMT (pseudomorphic high electron mobility transistor) process (Patent Document 1).
Japanese Patent No. 3675078

This pn junction gate type FET has a parasitic capacitance C _gs between the gate and source, a parasitic capacitance C _gd between the gate and drain, and a parasitic capacitance C _ds between the drain and source. The off capacitance (C _off ) of this FET is From FIG. 37, it can be expressed as number (1).

From equation (1), it can be seen that the parasitic capacitances C _gs , C _gd and C _ds need to be reduced in order to reduce C _off . It can also be seen that it is important to suppress the non-linearity of the parasitic capacitances C _gs , C _gd and C _ds in order to suppress the non-linearity of C _off .

In the pn junction gate type FET, although the on-resistance R _on is very small, the off-capacitance (C _off ) is large, and the non-linearity of the off-capacitance (C _off ) is not very good. Therefore, in the case of applying the FET to switch SW ₁ has a problem of IMD and harmonic distortion increases.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a switch element with less IMD and harmonic distortion and an electric device incorporating the switch element.

The first switch element of the present invention includes an input end, an output end, a ground end, one or more first field effect transistors inserted in series between the input end and the ground end, an input end and an output. And one or a plurality of second field-effect transistors inserted in series with the end. Here, the first field effect transistor and the second field effect transistor are formed on the same substrate, and the first field effect transistor in the first switch element is the following (A1) to (A5). The second field effect transistor in the first switch element includes the following components (B1) to (B5).
(A1) A laminated structure formed by including a lower electron supply layer, a channel layer, an upper electron supply layer and a contact layer in this order on the substrate. (A2) Contains p or n conductivity type impurities formed in the contact layer. The first source electrode and the first drain electrode (A5) formed on both sides of the first gate electrode on the contact layer of the first gate electrode (A4) formed on the first gate region (A3) A pair of electrodes formed between the first gate region and the first source electrode and between the first gate region and the first drain electrode and reaching at least the same depth as the first gate region from the upper surface of the contact layer. The first recess (B1) The p or n conductivity type formed at the bottom of the second recess in the second recess (B3) contact layer formed in the above-mentioned laminated structure (B2) contact layer Second gate region (B4) containing pure material Second gate electrode (B5) formed on the second gate region, second source electrode and second drain formed on both sides of the second recess on the contact layer electrode

A first electronic device of the present invention incorporates the first switch element connected to one element and another element.

  In the first switch element and the first electronic device of the present invention, the pair of first recesses are provided at both ends of the first gate region in the contact layer in the first field effect transistor, so that the parasitic capacitance is small. In addition, the voltage dependency of the parasitic capacitance is small and the nonlinearity of the parasitic capacitance is also small. In the second field effect transistor, since the second gate region is embedded in the contact layer, the on-resistance is low.

The second switch element of the present invention includes an input end, an output end, a ground end, one or more first field effect transistors inserted in series between the input end and the ground end, an input end and an output. And one or a plurality of second field-effect transistors inserted in series with the end. Here, the first field effect transistor and the second field effect transistor are formed on the same substrate, and the first field effect transistor in the second switch element is the following (C1) to (C4). The second field effect transistor in the second switch element has the following components (D1) to (D5).
(C1) A laminated structure formed by including a lower electron supply layer, a channel layer, an upper electron supply layer, and a contact layer in this order on a substrate (C2) a first recess reaching a predetermined depth from the upper surface of the contact layer ( C3) The first source electrode and the first drain electrode (D1) formed on both sides of the first recess on the first gate electrode (C4) contact layer formed on the bottom surface of the first recess. ) The second recess (D3) formed in the contact layer. The second gate region (D4) containing the p-type or n-conductivity type impurity formed at the bottom of the second recess in the contact layer. Second source electrode and second drain electrode formed on both sides of the second recess on the formed second gate electrode (D5) contact layer

  A second electronic device according to the present invention incorporates the second switch element connected to one element and another element.

  In the second switch element and the second electronic device according to the present invention, in the first field effect transistor, the first recess is provided around the first gate electrode formed on the upper electron supply layer. The capacitance is small, the voltage dependence of the parasitic capacitance is small, and the nonlinearity of the parasitic capacitance is also small. In the second field effect transistor, since the second gate region is embedded in the contact layer, the on-resistance is low.

  According to the first switch element and the first electronic device of the present invention, and the second switch element and the second electronic device of the present invention, the parasitic capacitance is small, and the voltage dependency of the parasitic capacitance is small. A first field effect transistor with low non-linearity is inserted in series between the input end and the ground end, and a second field effect transistor having a low on-resistance is inserted in series between the input end and the output end. Therefore, the on-resistance, insertion loss, IMD, and harmonic distortion can be sufficiently reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 shows a circuit configuration of a switch element 1 according to the first embodiment of the present invention. FIG. 2 shows a partial cross-sectional configuration of the switch element 1 of FIG.

  This switch element 1 is inserted in series between one or more shunt FETs 1A (first field effect transistors) inserted in series between the input terminal Port1 and the ground terminal GND, and between the input terminal Port1 and the output terminal Port2. And one or a plurality of series FETs 1B (second field effect transistors).

  A switching signal input terminal Vc1 is connected to the gate electrode 30 (described later) of the shunt FET 1A via a resistor R1, and a switching signal input terminal Vc2 is connected to the gate electrode 41 (described later) of the series FET 1B. Connected through.

  FIG. 1 illustrates the case where one shunt FET 1A and one series FET 1B are provided. FIG. 2 illustrates the case where the shunt FET 1A and the series FET 1B are formed adjacent to each other.

  Both the shunt FET 1A and the series FET 1B are formed on the same substrate 10 and are collectively formed by the pHEMT process.

(Shunt FET1A)
The shunt FET 1A is formed by epitaxially laminating a buffer layer 11, a lower electron supply layer 12, a lower spacer layer 13, a channel layer 14, an upper spacer layer 15, an upper electron supply layer 16, and a contact layer 17 in this order on one surface side of the substrate 10. Configured.

  The substrate 10 is a semi-insulating substrate, for example, a GaAs substrate. The buffer layer 11 is formed on the surface of the substrate 10 in order to improve crystal growth. For example, the buffer layer 11 is formed by alternately and repeatedly laminating AlGaAs and GaAs. The buffer layer 11 is formed on the uppermost layer of this periodic structure. GaAs is formed. The buffer layer 11 is preferably undoped, but may be one to which a sufficiently low concentration of impurities is added.

  In the present specification, “undoped” means that no dopant is supplied when the target semiconductor layer is manufactured, and no impurity is contained in the target semiconductor layer. It is also a concept that includes a case where impurities diffused from other semiconductor layers or the like are slightly included.

  The lower electron supply layer 12 is made of, for example, AlGaAs in which an n-type impurity is added to the entire region or a part of the thickness direction. The impurity distribution in the lower electron supply layer 12 may be uniform, or may change gradually (or stepwise) in the thickness direction. The lower spacer layer 13 is made of, for example, undoped AlGaAs, the channel layer 14 is made of, for example, undoped InGaAs, and the upper spacer layer 15 is made of, for example, undoped AlGaAs. The upper electron supply layer 16 is made of, for example, AlGaAs in which an n-type impurity is added to the entire region or a part of the thickness direction. The contact layer 17 is made of, for example, n-type AlGaAs.

  In the shunt FET 1A, a gate electrode 30, a source electrode 31, and a drain electrode 32 are provided on the contact layer 17. The gate electrode 30 is provided, for example, extending in one direction on the surface of the contact layer 17. The source electrode 32 and the drain electrode 32 are provided on both sides of the gate electrode 30 with a predetermined interval. A reaction region 33 is formed in a region facing the source electrode 31 and the drain electrode 32 in the upper spacer layer 15, the upper electron supply layer 16, and the contact layer 17, and the source electrode 32 and the drain electrode 32 are formed in the reaction region. The channel layer 14 can be contacted through 33.

  Here, the gate electrode 30 is configured by stacking Ti, Pt, and Au in this order, and the source electrode 31 and the drain electrode 32 are configured by stacking AuGe, Ni, and Au in this order. As will be described later, the reaction region 33 is formed by forming the source electrode 31 and the drain electrode 32 on the contact layer 17 and then performing alloying.

  Further, a gate region 34 is formed in the shunt FET 1A in a portion of the contact layer 17 immediately below the gate electrode 30, and the upper portion of the gate region 34 is in contact with the lower portion of the gate electrode 30. The gate region 34 is made of, for example, p-type AlGaAs, and is formed by introducing a p-type impurity (for example, Zn) into the surface of the contact layer 17 as will be described later. The width (gate length) L1 of the gate region 34 is preferably equal to or smaller than the width L2 of the gate electrode 30, but may be wider than the width L2. 2 illustrates a case where the gate length L1 is wider than the width L2 of the gate electrode 30. FIG. 3 illustrates a modification of FIG. The case where it is narrower than the width L2 is illustrated.

  A pair of recesses 35 are formed on both sides of the gate region 34 (specifically, between the gate region 34 and the source electrode 31 and between the gate region 34 and the drain electrode 32). The recess 35 may be formed at a predetermined distance from the gate region 34 that is directly under the gate electrode 21, but is preferably formed in contact with the gate region 34. Further, the opening width L3 of the recess 35 may be wider than the width L2 of the gate electrode 30, but is preferably equal to the width L2, and more preferably narrower than that. Further, the depth of the recess 35 is at least equal to the depth of the gate region 34, and more preferably deeper than the depth of the gate region 34. 2 and 3 exemplify cases where the depth of the recess 35 is deeper than the depth of the gate region 34.

(Series FET1B)
The series FET 1B has a buffer layer 11, a lower electron supply layer 12, a lower spacer layer 13, a channel layer 14, an upper spacer layer 15 and an upper electron supply layer 16 common to the shunt FET 1A on one surface side of the substrate 10 common to the shunt FET 1A. The contact layer 18 is epitaxially laminated in this order.

  The contact 18 has a structure in which, for example, a first contact layer 18A and a second contact layer 18B are sequentially stacked from the upper electron supply layer 16 side. The first contact layer 18A is made of, for example, n-type AlGaAs, and the second contact layer 18B is made of, for example, GaAs doped with a high-concentration n-type impurity. The second contact layer 18B is provided with, for example, a recess 40 having a width L4 extending in one direction in the laminated surface. The recess 40 is formed, for example, through the second contact layer 18B. For example, the depth of the recess 40 can be set to an appropriate value by adjusting the thickness of the second contact layer 18B.

  In the series FET 1B, a gate electrode 41, a source electrode 42, and a drain electrode 43 are provided on the contact layer 18. The gate electrode 41 is provided on the surface of the portion of the first contact layer 18A exposed in the recess 40. The source electrode 42 and the drain electrode 43 are provided on both sides of the recess 40 at a predetermined interval. A reaction region 44 is formed in a region of the upper spacer layer 15, the upper electron supply layer 16, and the contact layer 18 facing the source electrode 42 and the drain electrode 43, and the source electrode 42 and the drain electrode 43 are formed in the reaction region. A contact with the channel layer 14 can be made through 44.

  Here, the gate electrode 41 is configured by stacking Ti, Pt, and Au in this order, and the source electrode 42 and the drain electrode 43 are configured by stacking AuGe, Ni, and Au in this order. As will be described later, the reaction region 44 is formed by forming the source electrode 42 and the drain electrode 43 on the contact layer 18 and then performing alloying.

  In the series FET 1B, a gate region 45 is formed in a portion of the first contact layer 18A immediately below the gate electrode 41, and the upper portion of the gate region 45 is in contact with the lower portion of the gate electrode 41. The gate region 45 is made of, for example, p-type AlGaAs, and is formed by introducing p-type impurities (for example, Zn) into the surface of the portion corresponding to the bottom of the recess 40 in the first contact layer 18A as will be described later. is there. The width (gate length) L5 of the gate region 45 is preferably equal to or smaller than the width L6 of the gate electrode 30, but may be wider than the width L6. 2 and 3 exemplify cases in which the gate length L5 is wider than the width L6 of the gate electrode 30.

  An element isolation insulating film 19 is provided between the shunt FET 1A and the series FET 1B. The element isolation insulating film 19 is formed by, for example, LOCOS (local oxidation of silicon) or STI (Shallow Trench Isolation), and separates the shunt FET 1A and the series FET 1B from each other on the surface of the substrate 10. An insulating layer 50 is formed on the top surfaces of the shunt FET 1A and the series FET 1B. The insulating layer 50 is made of, for example, an insulating material such as silicon oxide or nitrogen nitride.

  The switch element 1 having such a configuration can be manufactured, for example, as follows. In the following, a method for manufacturing the switch element 1 shown in FIG. 3 will be described.

  Each semiconductor layer exemplified in the above structure is formed by a molecular beam epitaxy (MBE) method or a metal organic chemical vapor deposition (MOCVD, MOVPE) method.

  First, a buffer layer 11, a lower electron supply layer 12, a lower spacer layer 13, a channel layer 14, an upper spacer layer 15, an upper electron supply layer 16, a contact layer 17 (first contact layer 18A), and a contact are formed on the substrate 10. After the layers 18B are epitaxially stacked in this order, the portion corresponding to the region where the shunt FET 1A and the recess 40 are formed in the contact layer 18B is removed (FIG. 4). Subsequently, an insulating film 50A is stacked thereon by CVD (Chemical Vapor Deposition) or the like (FIG. 5).

  Next, an opening H1 having a width L7 (= L1 + 2 × L3) is formed in a portion where the gate region 34A (see FIG. 8) is to be formed on the insulating film 50A, and the gate region 45 is formed. A resist layer M1 having an opening H2 with a width L8 (= L6) in the portion is formed by a lithography process (FIG. 6).

Next, using the resist layer M1 as a mask, the insulating film 50A is selectively etched by reactive ion etching (RIE), for example, using a mixed gas in which H ₂ or O ₂ is added to CF ₄ , thereby insulating the insulating film 50A. Openings H3 and H4 are formed in the film 50A. As a result, the contact layer 17 (18A) is exposed at the bottom of the openings H3 and H4.

  Next, after removing the resist layer M1, vapor phase diffusion is performed using diethyl zinc (DEZ), which is an organometallic compound of Zn, on the exposed portion of the contact layer 17 (18A) using the insulating film 50A as a mask to form Zn. Then, gate regions 34A and 45 are formed in exposed portions of the contact layer 17 (18A) (FIG. 8).

  Next, a resist layer M2 having an opening H5 having a width L9 (= L2) in a portion corresponding to the gate electrode 30 and having an opening H6 having a width L10 (= L6) in a portion corresponding to the gate electrode 41 is lithography. It is formed by a process (FIG. 9). At this time, when the opening H5 is provided in the central portion of the gate region 34A, the opening H11 described later is formed symmetrically on both sides of the gate electrode 30, so that the pair of recesses 35 are formed symmetrically. Can do. If it is desired to form the pair of recesses 35 asymmetrically, the opening H3 may be provided in a portion other than the central portion of the gate region 34A.

  Next, after forming the Ti / Pt / Au metal film 51 on the entire surface including the openings H5 and H6 (FIG. 10), the resist layer M2 is peeled off by lift-off, and the gate electrode 30 is formed at the site of the opening H5. Then, the gate electrode 41 is formed at the site of the opening H6 (FIG. 11). Further, with the lift-off, openings H7 having a width L11 slightly narrower than the width L3 are formed on both sides of the gate electrode 30. As a result, the gate region 34A is exposed at the bottom of the opening H11.

  Next, using the gate electrodes 30 and 41 and the insulating film 50A as a mask, the gate region 34A is etched through the opening H11 to form a pair of recesses 35 on both sides of the gate electrode 30 (FIG. 12). Further, by this etching, a gate region 34 is formed immediately below the gate electrode 30. At this time, for example, when isotropic etching is performed using citric acid or the like, the portion immediately below the gate electrode 21 is slightly cut, so that the gate length L1 becomes narrower than the width L2 of the gate electrode 21. Thus, when an isotropic etching method is used when forming the pair of recesses 35, the gate length L1 can be made narrow. For example, when anisotropic etching is performed using the RIE method or the like, the portion immediately below the gate electrode 21 is hardly etched, so that the gate length L1 can be made equal to the width L2 of the gate electrode 21.

  When the recess 35 is formed, if it is desired to control the depth of the recess 35 by the structure, an etching stop layer (not shown) made of AlGaAs, InGaP or the like having a high Al composition is provided in the contact layer 17. It is preferable to keep it.

  Next, an insulating film 50B is formed on the entire surface including the recess 35 by a CVD method or the like (FIG. 13). As a result, the recess 35 is filled with an insulating material. Further, since the insulating layer 50 is formed together with the insulating film 50 </ b> A, the gate electrode 34 is embedded in the insulating layer 50.

  Next, a resist layer M3 having openings in portions where the source electrodes 31, 42 and the drain electrodes 32, 43 are formed is formed on the upper surface of the insulating layer 50 by a lithography process (FIG. 14). Thereafter, the insulating layer 50 is selectively etched by RIE using the resist layer M3 as a mask (FIG. 15). As a result, the contact layers 17 (18A) and 18B are exposed at the bottom of the opening of the insulating layer 50.

  Next, an AuGe / Ni / Au metal film is formed on the entire surface including the exposed portions of the contact layers 17 (18A) and 18B (FIG. 16). Subsequently, the resist layer M3 is peeled off by lift-off, and the source electrodes 31 and 42 and the drain electrodes 32 and 43 are formed at the openings (FIG. 17). Subsequently, alloying is performed to form reaction regions 33 and 44 (FIG. 18). In this way, the shunt FET 1A and the series FET 1B are formed.

  Thereafter, an element isolation insulating film 19 reaching the buffer layer 11 is formed between the shunt FET 1A and the series FET 1B (FIG. 3). In this way, the switch element 1 of the present embodiment is formed.

  In the switch element 1 having such a configuration, when an on signal is applied to the input terminal Vc1, the shunt FET 1A is turned on, the input terminal Port1 and the ground terminal GND are electrically connected to each other, and an off signal is applied to the input terminal Vc1. The shunt FET 1A is turned off, and the input terminal Port1 and the ground terminal GND are separated from each other. Further, when the ON signal is applied to the input terminal Vc2, the series FET 1B is turned on, the input terminal Port1 and the output terminal Port2 are electrically connected to each other, and when the OFF signal is applied to the input terminal Vc2, the series FET 1B is turned off and the input is performed. The end Port1 and the output end Port2 are separated from each other. Therefore, when an ON signal is applied to the input terminal Vc1 and an OFF signal is applied to the input terminal Vc2, the RF signal applied to the input terminal Port1 is dropped to the ground terminal GND and is not output to the output terminal Port2. On the other hand, when an off signal is applied to the input terminal Vc1 and an on signal is applied to the input terminal Vc2, the RF signal applied to the input terminal Port1 is output to the output terminal Port2 without being dropped to the ground terminal GND.

  In the above manufacturing method, when the shunt FET 1A is formed, the contact layer 17 is etched using the insulating film 50A and the gate electrode 30 as a mask to form the pair of recesses 35. The pair of recesses 35 can be formed in contact with the gate region 34 directly below the gate electrode 30 without aligning the pair of recesses 35 with each other. Further, since the insulating film 50A and the gate electrode 30 are used as a mask when forming the recess 35, the width L3 of the recess 35 (opening width of the opening H11) is reduced without depending on the opening capability of the stepper. Can do.

As a result, in the switch element 1 manufactured by the above manufacturing method, the pair of recesses 35 are provided in precise contact with the gate region 34 directly below the gate electrode 30 in the shunt FET 1A, so that the parasitic capacitances C _gs , C _gd is extremely small, and the voltage dependency of the parasitic capacitances C _gs and C _gd is very small. Furthermore, the parasitic capacitance C _gd is substantially constant within the range of the drive voltage, and the nonlinearity of the parasitic capacitance C _gd is extremely small within this range. As a result, in the shunt FET 1A, insertion loss, IMD, and harmonic distortion can be extremely reduced. Furthermore, when the width L3 of the recess 35 is made narrower than before, insertion loss, IMD, and harmonic distortion can be significantly reduced.

Further, in the manufacturing method described above, the width L3 can be narrowed, so that an increase in sheet resistance caused by providing the recess 35 can be reduced. Further, since the distance between the gate electrode 30 and the recess 35 can be shortened, the parasitic capacitances C _gs and C _gd can be made extremely small, and the voltage dependence of the parasitic capacitances C _gs and C _gd is also _achieved. Can be very small.

For example, when the opening capability of an i-line stepper is about 0.4 μm, the width of the gate electrode and the recess can be reduced only to about 0.4 μm by the conventional method. In addition, the distance between the gate electrode and the trench can be reduced only to about 0.2 μm by the current mass production technology because of the accuracy of alignment. On the other hand, in the above manufacturing method, the width of the recess 35 can be 0.4 μm or less, and the distance between the gate electrode 30 and the recess 35 is substantially zero (the gate electrode 30 and the recess 35 are mutually connected). Touching). Therefore, in the present embodiment, the increase in sheet resistance caused by providing the recess 35 can be reduced, and the parasitic capacitances C _gs and C _gd can be made extremely small, and the parasitic capacitance C _gs can be reduced. , C _gd voltage dependence can also be made extremely small.

As shown in FIG. 2, the parasitic capacitance C _gd is sufficiently small even when the pair of recesses 35 is provided at a slight distance from the gate region 34 directly below the gate electrode 30. The voltage dependency of the parasitic capacitance C _gd is also sufficiently small. Further, the parasitic capacitance C _gd is substantially constant within the drive voltage range, and the nonlinearity of the parasitic capacitance C _gd is sufficiently small in this range. As a result, even in the shunt FET 1A shown in FIG. 1, insertion loss, IMD, and harmonic distortion can be sufficiently reduced.

  Further, in the present embodiment, the shunt FET 1A and the series FET 1B have a structure in which the gate regions 34 and 45 are embedded in the contact layers 17 and 18, so that the on-resistance is low. Particularly, in the series FET 1B, since no recess is provided at both ends of the gate region 41, the on-resistance is extremely low as compared with the shunt FET 1A.

  As described above, in this embodiment, the shunt FET 1A having characteristics suitable for the shunt circuit is inserted in series between the input terminal Port1 and the ground terminal GND, and the series FET 1B having characteristics suitable for the series circuit is further input. Since it is inserted in series between the end Port1 and the output end Port2, compared with the case where the common FET is applied to the shunt circuit and the series circuit, the IMD and the harmonic distortion are effectively suppressed while suppressing the on-resistance. be able to.

[Second Embodiment]
FIG. 19 shows a circuit configuration of the switch element 2 according to the second exemplary embodiment of the present invention. FIG. 20 shows a partial cross-sectional configuration of the switch element 2 of FIG.

  The switch element 2 is inserted in series between one or a plurality of shunt FETs 2A (first field effect transistors) inserted in series between the input terminal Port1 and the ground terminal GND, and between the input terminal Port1 and the output terminal Port2. And one or a plurality of series FETs 2B (second field effect transistors).

  A switching signal input terminal Vc1 is connected to the gate electrode 37 (described later) of the shunt FET 2A via a resistor R1, and a switching signal input terminal Vc2 is connected to the gate electrode 41 (described later) of the series FET 2B. Connected through.

  FIG. 19 illustrates a case where one shunt FET 2A and one series FET 2B are provided. FIG. 20 illustrates a case where the shunt FET 2A and the series FET 2B are formed adjacent to each other.

  In the following, the same reference numerals are used for the same components as those in the above embodiment, and the description of the components having the same symbols as those in the above embodiment will be omitted as appropriate.

  Both the shunt FET 2A and the series FET 2B are formed on the same substrate 10 and are formed by the pHEMT process.

(Shunt FET2A)
The shunt FET 2A is formed by epitaxially laminating a buffer layer 11, a lower electron supply layer 12, a lower spacer layer 13, a channel layer 14, an upper spacer layer 15, an upper electron supply layer 16, and a contact layer 46 in this order on one surface side of the substrate 10. Configured.

  The contact layer 46 has a structure in which, for example, a first contact layer 46A, a second contact layer 46B, and a third contact layer 46C are stacked in this order from the upper electron supply layer 16 side. The first contact layer 46A is made of, for example, n-type InGaP, the second contact layer 46B is made of, for example, n-type AlGaAs, and the third contact layer 46C is made of, for example, GaAs doped with a high-concentration n-type impurity.

  The contact layer 46 is provided with a recess 36 extending in one direction within the laminated surface. The recess 36 is formed, for example, through the contact layer 46 and has a shape in which the width of the recess gradually decreases from the third contact layer 46C side to the first contact layer 46A side (for example, a mortar shape or a staircase). Shape). The depth of the recess 36 is not limited to the depth penetrating the contact layer 46, but is determined according to the magnitude of the threshold voltage to be set. Therefore, the recess 36 is the upper electron just below the contact layer 46. The depth may not reach the supply layer 16.

  In the shunt FET 2A, the gate electrode 37 is provided on the bottom surface of the contact layer 46 (on the upper electron supply layer 16 in FIG. 17), and the source electrode 38 and the drain electrode 39 are provided on the contact layer 46. . For example, the gate electrode 37 is provided to extend in one direction on the surface of a portion of the upper electron supply layer 16 exposed at the bottom of the recess 36. The source electrode 38 and the drain electrode 39 are provided on both sides of the recess 36 at a predetermined interval. A reaction region 33 is formed in a region facing the source electrode 38 and the drain electrode 39 in the upper spacer layer 15, the upper electron supply layer 16, and the contact layer 46, and the source electrode 38 and the drain electrode 39 are formed in the reaction region. The channel layer 14 can be contacted through 33.

  Here, the gate electrode 37 is configured by stacking Ti, Pt, and Au in this order, and the source electrode 38 and the drain electrode 39 are configured by stacking AuGe, Ni, and Au in this order.

(Series FET2B)
The series FET 2B has a buffer layer 11, a lower electron supply layer 12, a lower spacer layer 13, a channel layer 14, an upper spacer layer 15, and an upper electron supply layer 16 common to the shunt FET 1A on one surface side of the substrate 10 common to the shunt FET 2A. The contact layer 46 is epitaxially laminated in this order.

  The third contact layer 46C is provided with a recess 40 having a width L4 extending in one direction in the laminated surface. The recess 40 is formed, for example, through the third contact layer 46C. For example, the depth of the recess 40 can be set to an appropriate value by adjusting the thickness of the third contact layer 46C.

  In the series FET 2B, a gate electrode 41, a source electrode 42, and a drain electrode 43 are provided on the contact layer 46. The gate electrode 41 is provided on the surface of the portion of the third contact layer 46 </ b> C exposed in the recess 40. The source electrode 42 and the drain electrode 43 are provided on both sides of the recess 40 at a predetermined interval. A reaction region 44 is formed in a region facing the source electrode 42 and the drain electrode 43 in the upper spacer layer 15, the upper electron supply layer 16 and the contact layer 46, and the source electrode 42 and the drain electrode 43 are formed in the reaction region. A contact with the channel layer 14 can be made through 44.

  The series FET 2B further includes a gate region 45 formed immediately below the gate electrode 41 in the first contact layer 46A and the second contact layer 46B, and the upper portion of the gate region 45 is in contact with the lower portion of the gate electrode 41. Yes. As will be described later, the gate region 45 is formed by introducing p-type impurities (for example, Zn) into the surface of the portion of the first contact layer 46A and the second contact layer 46B corresponding to the bottom of the recess 40. is there.

  An element isolation insulating film 19 is provided between the shunt FET 2A and the series FET 2B. An insulating layer 53 is formed on the top surfaces of the shunt FET 2A and the series FET 2B. The insulating layer 53 is made of, for example, an insulating material such as silicon oxide or nitrogen nitride.

  The switch element 2 having such a configuration can be manufactured, for example, as follows.

  Each semiconductor layer exemplified in the above structure is formed by a molecular beam epitaxy (MBE) method or a metal organic chemical vapor deposition (MOCVD, MOVPE) method.

  First, the buffer layer 11, the lower electron supply layer 12, the lower spacer layer 13, the channel layer 14, the upper spacer layer 15, the upper electron supply layer 16, and the contact layer 46 are epitaxially stacked in this order on the substrate 10 (FIG. 21). ).

  Next, a resist layer M4 having openings H8 and H9 corresponding to a region including a portion where the gate electrodes 37 and 41 are to be formed is formed on the surface by a lithography process. Subsequently, using the resist layer M4 as a mask, the third contact layer 46C is selectively etched using, for example, citric acid to form an opening H10 corresponding to the opening H8 in the third contact layer 46C. At the same time, an opening H11 is formed corresponding to the opening H9 (FIG. 22).

  Next, after removing the resist layer M4, an insulating film 53A having an opening H12 having an opening width L12 (= width L6) smaller than the opening H11 is formed in the opening H11 (FIG. 23). Subsequently, by using this insulating film 53A as a mask, Zn is introduced into the exposed portion of the second contact layer 46B by vapor phase diffusion using diethyl zinc (DEZ), which is an organometallic compound of Zn, and the first contact layer is introduced. A gate region 45 is formed in a portion of 46A and second contact layer 46B corresponding to the portion immediately below the exposed portion (FIG. 23).

Next, a resist layer M5 having an opening H13 having an opening smaller than the opening H10 immediately above the opening H10 is formed on the surface (FIG. 24). Subsequently, using the resist layer M5 as a mask, portions of the insulating film 53A and the second contact layer 46B that are directly below the opening H13 are selectively removed, and the opening H14 is formed in the insulating film 53A and the second contact layer 46B. Is formed (FIG. 24). At this time, the second contact layer 46B is selectively removed using, for example, an H ₂ SO ₄ —H ₂ O ₂ —H ₂ O-based etching solution.

Next, after removing the resist layer M5, an opening H15 having an opening smaller than the opening H14 is provided in the opening H14, and an opening H16 having an opening width equivalent to the opening H12 is provided immediately above the opening H12. A resist layer M6 is formed (FIG. 25). Subsequently, the first contact layer 46A is selected using an etching solution (for example, HCl-H ₂ O-based etching solution) in which the dissolution rate of the first contact layer 46A is sufficiently faster than that of the second contact layer 46B. To remove. Thereby, the opening H17 having an opening wider than the opening of the opening H15 can be formed in the first contact layer 46A (FIG. 26).

  Next, after a Ti / Pt / Au metal film is formed on the entire surface including the openings H15 and H16, the resist layer M6 is peeled off by lift-off, and a gate electrode is formed in the opening H17 immediately below the opening H15. 37 is formed, and the gate electrode 41 is formed at the site of the openings H12 and H16 (FIG. 27). Further, a recess 36 is formed around the gate electrode 37 along with the lift-off.

  Next, after the insulating film 53B is formed on the entire surface including the recesses 36 and 40 and the insulating layer 53 is formed together with the insulating film 53A, the source electrodes 38 and 42 and the drain electrodes 39 and 43 are to be formed. A resist layer M7 having an opening is formed (FIG. 28).

  Next, using the resist layer M7 as a mask, the insulating layer 54 is selectively etched by RIE to expose the third contact layer 46C, and the entire surface including the exposed portion of the third contact layer 46C is exposed to AuGe / Ni / Au. After the metal film is formed, the resist layer M7 is peeled off by lift-off, and source electrodes 38 and 42 and drain electrodes 39 and 43 are formed at the openings (FIG. 29). Subsequently, alloying is performed to form reaction regions 33 and 44. In this way, the shunt FET 2A and the series FET 2B are formed.

  Thereafter, an element isolation insulating film 19 reaching the buffer layer 11 is formed between the shunt FET 2A and the series FET 2B. In this way, the switch element 2 of the present embodiment is formed.

  In the switch element 2 having such a configuration, when an on signal is applied to the input terminal Vc1, the shunt FET 2A is turned on, the input terminal Port1 and the ground terminal GND are electrically connected to each other, and an off signal is applied to the input terminal Vc1. The shunt FET 2A is turned off, and the input terminal Port1 and the ground terminal GND are separated from each other. Further, when the ON signal is applied to the input terminal Vc2, the series FET 2B is turned on, the input terminal Port1 and the output terminal Port2 are electrically connected to each other, and when the OFF signal is applied to the input terminal Vc2, the series FET 2B is turned off and the input is performed. The end Port1 and the output end Port2 are separated from each other. Therefore, when an ON signal is applied to the input terminal Vc1 and an OFF signal is applied to the input terminal Vc2, the RF signal applied to the input terminal Port1 is dropped to the ground terminal GND and is not output to the output terminal Port2. On the other hand, when an off signal is applied to the input terminal Vc1 and an on signal is applied to the input terminal Vc2, the RF signal applied to the input terminal Port1 is output to the output terminal Port2 without being dropped to the ground terminal GND.

By the way, in the switch element 2 of the present embodiment, since the recess 36 is provided around the gate electrode 37 in the shunt FET 2A, the parasitic capacitance C _gd is small and the voltage dependency of the parasitic capacitance C _gd is also small. . Further, the parasitic capacitance C _gd is substantially constant within the drive voltage range, and the nonlinearity of the parasitic capacitance C _gd is small in this range. As a result, insertion loss, IMD, and harmonic distortion can be reduced in the shunt FET 2A.

  Further, in the present embodiment, the series FET 2B has a structure in which the gate region 45 is embedded in the contact layer 46, so the on-resistance is low. In particular, in the series FET 2B, since no recess is provided at both ends of the gate region 45, the on-resistance is extremely low as compared with the shunt FET 2A.

  As described above, in this embodiment, the shunt FET 2A having characteristics suitable for the shunt circuit is inserted in series between the input terminal Port1 and the ground terminal GND, and the series FET 2B having characteristics suitable for the series circuit is further input. Since it is inserted in series between the end Port1 and the output end Port2, compared with the case where the common FET is applied to the shunt circuit and the series circuit, the IMD and the harmonic distortion are effectively suppressed while suppressing the on-resistance. be able to.

[Example]
Next, various characteristics of the shunt FET 1A and the series FET 1B in the above embodiment will be described.

In this example, Sample A and Sample C were prepared as the FETs subjected to the recess. In sample A, the impurity concentration of each of the lower electron supply layer 12 and the upper electron supply layer 16 is 3.0 × 10 ¹⁸ cm ⁻³ , the thickness of the contact layer 17 is 130 nm, and the depth of the recess 35 is 100 nm. The distance between the gate electrode 30 and the recess 35 was 0.05 μm, and the gate width was 4 mm. In Sample C, the impurity concentration of each of the lower electron supply layer 12 and the upper electron supply layer 16 is 2.4 × 10 ¹⁸ cm ⁻³ , the thickness of the contact layer 17 is 80 nm, and the depth of the recess 35 is The distance between the gate electrode 30 and the recess 35 was 0.05 μm, and the gate width was 4 mm.

Samples B and D were prepared as conventional FETs that were not recessed. In Sample B, the impurity concentration of each of the lower electron supply layer 12 and the upper electron supply layer 16 was 3.0 × 10 ¹⁸ cm ⁻³ , the thickness of the contact layer 17 was 130 nm, and the gate width was 4 mm. In Sample D, the impurity concentration of each of the lower electron supply layer 12 and the upper electron supply layer 16 is 2.4 × 10 ¹⁸ cm ⁻³ , the thickness of the contact layer 17 is 80 nm, and the gate width is 4 mm. .

  FIG. 30 shows a schematic configuration of a circuit used for measuring various characteristics in the shunt circuit of the sample A or the sample B described above. This circuit includes five ports: an input terminal Port1, an input terminal Port2, an output terminal Port3, an input terminal Vc1, and a ground terminal GND. The input terminal Port1 and the output terminal Port3 are connected in parallel to the input terminal Port2, and four samples A or B connected in series are connected in series between the input terminal Port2 and the ground terminal GND. Yes. Further, the gate electrode of the sample A or the sample B is connected to the input terminal Vc1 via the resistor R1.

An RF signal having a frequency f ₀ and a power P ₀ is input from the input terminal Port1, and an interference signal having a frequency f _b and a power P _b is input from the input terminal Port2 as an interference wave that interferes with the RF signal. Further, a negative voltage is input from the input terminal Vc1, and a reverse bias is applied to the sample A or the sample B to turn off the sample A or the sample B. At this time, the output from the output terminal Port3 is measured. . The measurement results at that time are shown in FIG.

In FIG. 31, ΔC _off / ΔV indicates the amount of change in off-capacitance per unit voltage (non-linear amount of off-capacitance) when the drain voltage is in the range of −1 V to +1 V.

FIG. 31 shows that sample A is superior to sample B in the off-capacitance C _off , the off-capacitance nonlinear amount ΔC _off / ΔV, and the secondary IMD, excluding the on-resistance R _on . Therefore, sample A was found to be suitable for a shunt circuit.

  FIG. 32 shows a schematic configuration of a circuit used for measuring various characteristics in the series circuit of the sample C or the sample D described above. This circuit includes five ports: an input terminal Port1, an input terminal Port2, an output terminal Port3, an input terminal Vc2, and a ground terminal GND. Four samples C or D connected in series are connected in series between the input port Port1 and the input port Port2, and the output port Port3 is connected in parallel to the input port Port1. Further, the gate electrode of the sample C or the sample D is connected to the input terminal Vc2 through the resistor R2.

An RF signal having a frequency f ₀ and a power P ₀ is input from the input terminal Port1, and an interference signal having a frequency f _b and a power P _b is input from the input terminal Port2 as an interference wave that interferes with the RF signal. Further, by inputting a positive voltage from the input terminal Vc2, and applying a reverse bias to the sample C or D, the sample C or D was turned on, and at this time, the output from the output terminal Port2 was measured. . The measurement results at that time are shown in FIG.

FIG. 33 shows that sample D is superior to sample C in the on-resistance R _on , the second-order IMD, and the third-order IMD except for the off-capacitance C _off and the nonlinear amount ΔC _off / ΔV of the off-capacitance. Therefore, sample D was found to be suitable for a series circuit.

[Application example]
Next, with reference to FIG. 34, the configuration of a communication device equipped with switch elements 1 and 2 (collectively referred to as switch element SW) according to the above-described embodiment or its modification will be described. FIG. 31 illustrates a block configuration of a communication device as an electronic device.

The communication apparatus shown in FIG. 34 includes a system switch that switches the switch element SW between the second generation GSM system (S _GSM ) and the third generation W-CDMA system (S _W-CDMA ), It is installed as a transmission / reception switch for the next generation GSM system (S _GSM ), such as a mobile phone, a personal digital assistant (PDA), and a wireless LAN device. The transmission / reception switch is formed of a semiconductor device.

For example, as shown in FIG. 34, the communication apparatus includes a transmission / reception antenna ANT, two switch elements SW (antenna switch element SW1, transmission / reception switch element SW2), a duplexer DPX, and a second generation GSM system. (S _GSM ) and a third generation W-CDMA system (S _W-CDMA ).

Here, the antenna switch element SW1 is connected between the antenna ANT and the third generation W-CDMA system (S _W-CDMA ) and the other switch SW, and the transmission / reception switch element SW2 is connected to the antenna switch element SW1. The second generation GSM system (S _GSM ) is connected between the transmission side wiring Tx2 and the reception side wiring Rx2.

In this communication apparatus, since the switch elements 1 and 2 according to the above-described embodiment or the modification thereof are used as the antenna switch element SW1 and the transmission / reception switch element SW2, the parasitic capacitance C in the antenna switch element SW1 and the transmission / reception switch element SW2 is used. _gs and C _gd are small, and the parasitic capacitances C _gs and C _gd have little voltage dependency. Furthermore, the parasitic capacitances C _gs and C _gd are substantially constant within the range of the driving voltage, and the nonlinearity of the parasitic capacitances C _gs and C _gd is small in this range. As a result, insertion loss, IMD, and harmonic distortion can be reduced in the antenna switch element SW1 and the transmission / reception switch element SW2.

  As described above, the switch element and the communication device according to the present invention have been described with reference to the embodiment, the modified example, and the application example. However, the present invention is not limited to the above-described embodiment and the like. The configuration of the communication device and the procedure related to the manufacturing method thereof can be freely modified as long as the same effects as those of the above-described embodiment can be obtained.

  Further, in the above application example, the case where the switch element of the present invention is applied to an electronic device typified by a communication device such as a mobile phone has been described. However, the present invention is not necessarily limited to this, and the electronic device other than the communication device is used. It is also possible to apply.

It is a circuit block diagram of the switch element which concerns on the 1st Embodiment of this invention. It is a cross-sectional block diagram of the switch element of FIG. FIG. 6 is a cross-sectional configuration diagram illustrating a modification of the switch element of FIG. 2. FIG. 4 is a cross-sectional configuration diagram for explaining a manufacturing process of the switch element of FIG. 3. FIG. 5 is a cross-sectional configuration diagram for explaining a process following FIG. 4. FIG. 6 is a cross-sectional configuration diagram for explaining a process following FIG. 5. FIG. 7 is a cross-sectional configuration diagram for explaining a process following FIG. 6. FIG. 8 is a cross-sectional configuration diagram for explaining a process following FIG. 7. FIG. 9 is a cross-sectional configuration diagram for describing a process following FIG. 8. FIG. 10 is a cross-sectional configuration diagram for describing a process following FIG. 9. It is a cross-sectional block diagram for demonstrating the process following FIG. It is a cross-sectional block diagram for demonstrating the process following FIG. FIG. 13 is a cross-sectional configuration diagram for describing a process following FIG. 12. It is a cross-sectional block diagram for demonstrating the process following FIG. It is a cross-sectional block diagram for demonstrating the process following FIG. FIG. 16 is a cross-sectional configuration diagram for explaining a process following FIG. 15. FIG. 17 is a cross-sectional configuration diagram for illustrating a process following the process in FIG. 16. FIG. 18 is a cross-sectional configuration diagram for explaining a process following FIG. 17. It is a circuit block diagram of the switch element which concerns on the 2nd Embodiment of this invention. FIG. 20 is a cross-sectional configuration diagram of the switch element of FIG. 19. FIG. 21 is a cross-sectional configuration diagram for describing a manufacturing process of the switch element of FIG. 20. FIG. 22 is a cross-sectional configuration diagram for illustrating a process following the process in FIG. 21. FIG. 23 is a cross-sectional configuration diagram for describing a process following the process in FIG. 22. FIG. 24 is a cross-sectional configuration diagram for illustrating a process following the process in FIG. 23. FIG. 25 is a cross-sectional configuration diagram for describing a process following FIG. 24. FIG. 26 is a cross-sectional configuration diagram for illustrating a process following the process in FIG. 25. FIG. 27 is a cross-sectional configuration diagram for describing a process following FIG. 26. FIG. 28 is a cross-sectional configuration diagram for describing a process following FIG. 27. FIG. 29 is a cross-sectional configuration diagram for describing a process following the process in FIG. 28. It is a circuit block diagram for measuring various characteristics in the shunt circuit of shunt FET1A and series FET1B which concern on one Example. It is a figure showing the measured value in the circuit structure of FIG. It is a circuit block diagram for measuring the various characteristics in the series circuit of shunt FET1A and series FET1B which concern on one Example. It is a figure showing the measured value in the circuit structure of FIG. It is a circuit block diagram of the communication apparatus which concerns on one application example of a switch element. It is the circuit block diagram of the conventional switch element, and an equivalent circuit schematic. FIG. 36 is a characteristic diagram for explaining an example of a frequency characteristic of the switch element of FIG. 35. It is an equivalent circuit diagram of a transistor.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 2 ... Switch element, 1A, 2A ... Shunt FET, 1B, 2B ... Series FET, 10 ... Substrate, 11 ... Buffer layer, 12 ... Lower electron supply layer, 13 ... Lower spacer layer, 14 ... Channel layer, 15 ... Upper spacer layer, 16 ... upper electron supply layer, 17, 18, 46 ... contact layer, 18A, 46A ... first contact layer, 18B, 46B ... second contact layer, 46C ... third contact layer, 19 ... element isolation insulation Film, 30, 37, 41 ... gate electrode, 31, 38, 42 ... source electrode, 32, 39, 43 ... drain electrode, 33, 44 ... reaction region, 34, 45 ... gate region, 35, 36, 40 ... recess .

Claims (8)

An input end;
An output end;
The ground edge,
One or more first field effect transistors inserted in series between the input end and the ground end;
One or more second field effect transistors inserted in series between the input end and the output end,
The first field effect transistor and the second field effect transistor are formed on the same substrate,
The first field effect transistor is:
A laminated structure formed by including a lower electron supply layer, a channel layer, an upper electron supply layer, and a contact layer in this order on the substrate;
A first gate region containing p or n conductivity type impurities formed in the contact layer;
A first gate electrode formed on the first gate region;
A first source electrode and a first drain electrode formed on both sides of the first gate electrode on the contact layer;
A depth formed between the first gate region and the first source electrode, between the first gate region and the first drain electrode, and at least equal to the first gate region from the upper surface of the contact layer. A pair of first recesses reaching up to
The second field effect transistor is:
The laminated structure;
A second recess formed in the contact layer;
A second gate region containing a p-type or n-type impurity formed at the bottom of the second recess in the contact layer;
A second gate electrode formed on the second gate region;
A switch element comprising: a second source electrode and a second drain electrode formed on both sides of the second recess on the contact layer. The width of the first gate region is wider than the width of the first gate electrode,
The switch element according to claim 1, wherein the width of the second gate region is wider than the width of the second gate electrode. A width of the first gate region is equal to or smaller than a width of the first gate electrode;
The switch element according to claim 1, wherein the width of the second gate region is wider than the width of the second gate electrode. The switch element according to claim 3, wherein the pair of first recesses are in contact with the first gate region. An input end;
An output end;
The ground edge,
One or more first field effect transistors inserted in series between the input end and the ground end;
One or more second field effect transistors inserted in series between the input end and the output end,
The first field effect transistor and the second field effect transistor are formed on the same substrate,
The first field effect transistor is:
A laminated structure formed by including a lower electron supply layer, a channel layer, an upper electron supply layer, and a contact layer in this order on the substrate;
A first recess reaching a predetermined depth from the upper surface of the contact layer;
A first gate electrode formed on a bottom surface of the first recess;
A first source electrode and a first drain electrode formed on both sides of the first recess on the contact layer;
The second field effect transistor is:
The laminated structure;
A second recess formed in the contact layer;
A second gate region containing a p-type or n-type impurity formed at the bottom of the second recess in the contact layer;
A second gate electrode formed on the second gate region;
A switch element comprising: a second source electrode and a second drain electrode formed on both sides of the second recess on the contact layer. The switch element according to claim 1, wherein the width of the second gate region is wider than the width of the second gate electrode. An electronic device including a switch element connected to one element and another element,
The switch element is
An input end;
An output end;
The ground edge,
One or more first field effect transistors inserted in series between the input end and the ground end;
One or more second field effect transistors inserted in series between the input end and the output end,
The first field effect transistor and the second field effect transistor are formed on the same substrate,
The first field effect transistor is:
A laminated structure formed by including a lower electron supply layer, a channel layer, an upper electron supply layer, and a contact layer in this order on the substrate;
A first gate region containing p or n conductivity type impurities formed in the contact layer;
A first gate electrode formed on the first gate region;
A first source electrode and a first drain electrode formed on both sides of the first gate electrode on the contact layer;
A depth formed between the first gate region and the first source electrode, between the first gate region and the first drain electrode, and at least equal to the first gate region from the upper surface of the contact layer. A pair of first recesses reaching up to
The second field effect transistor is:
The laminated structure;
A second recess formed in the contact layer;
A second gate region containing a p-type or n-type impurity formed at the bottom of the second recess in the contact layer;
A second gate electrode formed on the second gate region;
An electronic apparatus comprising: a second source electrode and a second drain electrode formed on both sides of the second recess on the contact layer. An electronic device including a switch element connected to one element and another element,
The switch element is
An input end;
An output end;
The ground edge,
One or more first field effect transistors inserted in series between the input end and the ground end;
One or more second field effect transistors inserted in series between the input end and the output end,
The first field effect transistor and the second field effect transistor are formed on the same substrate,
The first field effect transistor is:
A laminated structure formed by including a lower electron supply layer, a channel layer, an upper electron supply layer, and a contact layer in this order on the substrate;
A first recess reaching a predetermined depth from the upper surface of the contact layer;
A first gate electrode formed on a bottom surface of the first recess;
A first source electrode and a first drain electrode formed on both sides of the first recess on the contact layer;
The second field effect transistor is:
The laminated structure;
A second recess formed in the contact layer;
A second gate region containing a p-type or n-type impurity formed at the bottom of the second recess in the contact layer;
A second gate electrode formed on the second gate region;
An electronic apparatus comprising: a second source electrode and a second drain electrode formed on both sides of the second recess on the contact layer.

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